Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1-12 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A broad range or limitation together with a narrow range or limitation that falls within the broad range or limitation (in the same claim) may be considered indefinite if the resulting claim does not clearly set forth the metes and bounds of the patent protection desired. See MPEP § 2173.05(c). In the present instance, claim 1 recites the broad recitation “flexible substrate”, and the claim also recites “which may be a Kapton film” which is the narrower statement of the range/limitation. The claim(s) are considered indefinite because there is a question or doubt as to whether the feature introduced by such narrower language is (a) merely exemplary of the remainder of the claim, and therefore not required, or (b) a required feature of the claims.
It is assumed that “may be” means that it is merely exemplary and it is not required to be a Kapton film. The Examiner notes that if the claim were amended to state “a flexible substrate which comprises a Kapton film” that would require the Kapton film.
Claim 2 recites “wherein said one or more semiconductor membranes block incident waves at radio frequencies (RF) while detecting infrared and visible radiation” however the Examiner notes that if the membrane absorbs the RF, then that affects the current because of the energy absorbed, thus even if the infrared and visible radiation are also detected, thus it is not clear how the Applicant can claim blocking unless the blocking and the detection is by different ones of a plurality of membranes.
Allowable Subject Matter
Claims 13-19 allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The method of manufacture of 2D material on semiconductor and attached to a flexible substrate was not considered to be obvious.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ordonez et al. (US 9704964 B1) hereafter referred to as Ordonez.
In regard to claim 1 Ordonez teaches [see Fig. 3A, compare structure of Fig. 3A upside down to Fig. 5 of the instant Application, see Ordonez “graphene field effect transistors with no physical gate (i.e. 2-terminal device biased by external electromagnetic source 290)” , see absorption of graphene] a layered material comprising:
a flexible substrate [“In some embodiments, encasing material 270 comprises a polymer, an example of which is polyimide. Other non-limiting examples of encasing materials 270 include PET, PDMS, TPE, and PMMA”, the flexibility is inherent] which may be a Kapton film;
subsequent layers include a first [“liquid metal contacts 250 and 260 may comprise a gallium-based alloy. In some embodiments, the gallium-based alloy includes a combination of two or more of gallium, indium, and tin, such as the commercially-available Galinstan” “at least one conductive trace 230 and 240 proximate to layer of graphene 220 that can connect device 200 to other circuitry, one or more liquid metal contacts 250 and 260 each electrically connecting layer of graphene 220 and a separate one of conductive trace 230 and 240, and an encasing material 270 disposed over and enclosing liquid metal contacts 250 and 260”] and second electrode, a dielectric [“Device 200 includes dielectric layer 210”], a two-dimensional material [“a layer of graphene (e.g. monolayer graphene, multilayer graphene, micro-structure, nano-structure, or other carbon structure) 220”], and
but does not state one or more semiconductor membranes,
however see “Device 200 further includes a substrate layer 280 for electronic gating disposed on the underside of substrate 210” see Ordonez teaches that 280 can be CMOS “Some embodiments of the devices discussed above can explore platforms for growth and processing of monolayer graphene, multilayer graphene, and graphene micro-structure or nano-structures over large area CMOS architecture in an effort to achieve electromagnetic sensing. Platforms can be investigated to improve read sensitivity to detect electromagnetic energy of faint targets such as military, space, and biological applications, therefore, reducing the need for complex noise reducing hardware or software algorithms and reducing the strain on additional systems. The development and hybridization of low-power MOS, CMOS, or VLSI readout integrated circuit (ROIC) may also be integrated to achieve ultrafast charge transfer rates in any portion of the electromagnetic spectrum” “2-terminal device biased by external electromagnetic source 290”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ordonez to include that 280 is Silicon CMOS type substrate.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Silicon CMOS substrate is standard and gives good results for electronic gating, readout integrated circuit (ROIC) to achieve electromagnetic sensing.
Claim(s) 1-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ordonez et al. (US 9704964 B1) hereafter referred to as Ordonez in view of Biricik et al. (US 5173443 A) hereafter referred to as Biricik
In regard to claim 1 Ordonez teaches [see Fig. 3A, compare structure of Fig. 3A upside down to Fig. 5 of the instant Application, see Ordonez “graphene field effect transistors with no physical gate (i.e. 2-terminal device biased by external electromagnetic source 290)” , see absorption of graphene] a layered material comprising:
a flexible substrate [“In some embodiments, encasing material 270 comprises a polymer, an example of which is polyimide. Other non-limiting examples of encasing materials 270 include PET, PDMS, TPE, and PMMA”, the flexibility is inherent] which may be a Kapton film;
subsequent layers include a first [“liquid metal contacts 250 and 260 may comprise a gallium-based alloy. In some embodiments, the gallium-based alloy includes a combination of two or more of gallium, indium, and tin, such as the commercially-available Galinstan” “at least one conductive trace 230 and 240 proximate to layer of graphene 220 that can connect device 200 to other circuitry, one or more liquid metal contacts 250 and 260 each electrically connecting layer of graphene 220 and a separate one of conductive trace 230 and 240, and an encasing material 270 disposed over and enclosing liquid metal contacts 250 and 260”] and second electrode, a dielectric [“Device 200 includes dielectric layer 210”], a two-dimensional material [“a layer of graphene (e.g. monolayer graphene, multilayer graphene, micro-structure, nano-structure, or other carbon structure) 220”], and
but does not state one or more semiconductor membranes,
however see “Device 200 further includes a substrate layer 280 for electronic gating disposed on the underside of substrate 210” see Ordonez teaches that 280 can be CMOS “Some embodiments of the devices discussed above can explore platforms for growth and processing of monolayer graphene, multilayer graphene, and graphene micro-structure or nano-structures over large area CMOS architecture in an effort to achieve electromagnetic sensing. Platforms can be investigated to improve read sensitivity to detect electromagnetic energy of faint targets such as military, space, and biological applications, therefore, reducing the need for complex noise reducing hardware or software algorithms and reducing the strain on additional systems. The development and hybridization of low-power MOS, CMOS, or VLSI readout integrated circuit (ROIC) may also be integrated to achieve ultrafast charge transfer rates in any portion of the electromagnetic spectrum” “2-terminal device biased by external electromagnetic source 290”, see the “at least one conductive trace 230 and 240” are accessible from the top like in a flip-chip design.
See Biricik teaches “Transparent conductive windows through which optical energy must pass and which have good electrical conductivity have utility in a number of applications. These include resistance heated windows, electro magnetic interference (EMI) shielded windows” “While the semiconductor materials utilized for the coatings of the present invention typically have higher resistivity than metallic coatings, because they have greater optical transparency they can be utilized as thicker coatings and as such the final coating will have a sheet resistance equal to or lower than the sheet resistance for a similar metal coating but will also enjoy a greater optical transparency” “In preparing windows of the invention by depositing a doped coating onto a surface of a substrate, the doped coating can be deposited utilizing a variety of homoepitaxy or heteroepitaxy procedures. Examples of homoepitaxy include, but are not limited to, doped silicon on silicon, doped germanium on germanium, doped gallium arsenide on gallium arsenide; i.e., the deposited layer is, in essence, chemically identical to the substrate host, with the addition of a trace amount of a dopant species. Examples of heteroepitaxy include, but are not limited to, gallium arsenide on germanium, gallium aluminum arsenide on gallium arsenide, and germanium on zinc sulfide or zinc selenide; i.e., the deposited layer is chemically different, but structurally similar to the substrate host, on an atomic scale” “Useful for the semiconductor coatings are gallium arsenide, gallium aluminum arsenide, silicon, germanium, semiconducting diamond and semiconducting silicon carbide” “Depending on the particular substrate and coating selected, windows of the invention will include transparency up to about 16 microns as, for instance, in a range of from about 2 microns to about 16 microns” “windows of the inventions included infrared transparency from near to long IR (infrared)”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ordonez to include that 280 is Silicon CMOS type substrate with an area which is an electro magnetic interference (EMI) shielded window in the Silicon substrate to allow light to reach the graphene, wherein the “at least one conductive trace 230 and 240” are accessible from the top like a flip-chip.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that Silicon CMOS substrate is standard and gives good results for electronic gating, readout integrated circuit (ROIC) to achieve electromagnetic sensing, and is also ideal for implementing electro magnetic interference (EMI) shielded window to minimize noise to the graphene for infrared and visible light detection from the bottom.
In regard to claim 2 Ordonez and Biricik as combined teaches wherein said one or more semiconductor membranes block incident waves [see combination, see “Transparent conductive windows through which optical energy must pass and which have good electrical conductivity have utility in a number of applications. These include resistance heated windows, electro magnetic interference (EMI) shielded windows” “Depending on the particular substrate and coating selected, windows of the invention will include transparency up to about 16 microns as, for instance, in a range of from about 2 microns to about 16 microns” “windows of the inventions included infrared transparency from near to long IR (infrared)” thus EMI at radio frequencies (RF) is shielded, see Ordonez “graphene field effect transistors with no physical gate (i.e. 2-terminal device biased by external electromagnetic source 290)” , see absorption of graphene] at radio frequencies (RF) while detecting infrared and visible radiation.
In regard to claim 3 Ordonez and Biricik as combined teaches wherein said material comprises at least one uniformly and single-crystalline semiconductor membrane [see combination, see “As a general rule, the germanium films having the highest mobilities are monocrystalline with a relatively low density of microstructural defects, as fabricated by either deposition method” “Transparent conductive windows through which optical energy must pass and which have good electrical conductivity have utility in a number of applications. These include resistance heated windows, electro magnetic interference (EMI) shielded windows” “Depending on the particular substrate and coating selected, windows of the invention will include transparency up to about 16 microns as, for instance, in a range of from about 2 microns to about 16 microns” “windows of the inventions included infrared transparency from near to long IR (infrared)” thus RF waves with frequencies ranging between the X and the W band are shielded] serves as an IR transparent shield of RF waves with frequencies ranging between the X and the W band of the electromagnetic spectrum,
but does not state degenerately doped, however higher doping means higher conduction.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “degenerately doped ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 4 Ordonez and Biricik as combined teaches wherein said material integrates at least one single-crystalline semiconductor membrane with non-uniform doping [see combination, see for example Biricik “As a general rule, the germanium films having the highest mobilities are monocrystalline with a relatively low density of microstructural defects, as fabricated by either deposition method” “A doped semiconductor layer 14 which may be doped by phosphorous, arsenic or antimony for either substrate is vacuum deposited or carried to the surface of the substrate in an inert gaseous or liquid medium. It is diffused into the substrate to a considerably greater depth than in the prior art. The doped layer is diffused to depths between 10 and 50 microns and in the preferred embodiments is of the order of 25 microns thick” “Transparent conductive windows through which optical energy must pass and which have good electrical conductivity have utility in a number of applications. These include resistance heated windows, electro magnetic interference (EMI) shielded windows” “Depending on the particular substrate and coating selected, windows of the invention will include transparency up to about 16 microns as, for instance, in a range of from about 2 microns to about 16 microns” “windows of the inventions included infrared transparency from near to long IR (infrared)” thus RF waves with frequencies ranging between the X and the W band are shielded] across its thickness that serves as an optically transparent shield of RF waves with frequencies ranging between the X and the W band of the electro- magnetic spectrum.
In regard to claim 5 Ordonez and Biricik as combined teaches wherein said at least one semiconductor membrane [see for example Biricik “A gallium arsenide layer was epitaxially grown thereon to a thickness of about 5 microns. During growth of this layer it was doped with silicon at about 1.5.times.10.sup.16 /cm.sup.3 to form an n gallium arsenide conductive layer.”] is completely doped.
In regard to claim 6 Ordonez and Biricik as combined teaches wherein said at least one semiconductor membrane has a thickness [see claim 5, see this can be divided into multiple layers, see for example claim 8 “multi-layer shield may be conformed of same or different materials with same or different thickness and conductivities”] ranging between 100 nm and 300 nm.
In regard to claim 7 Ordonez and Biricik as combined teaches [see for example Biricik “A gallium arsenide layer was epitaxially grown thereon to a thickness of about 5 microns. During growth of this layer it was doped with silicon at about 1.5.times.10.sup.16 /cm.sup.3 to form an n gallium arsenide conductive layer.” see this can be divided into multiple layers of small thicknesses] wherein said one or more semiconductor membranes may be stacked to form a multi-layer shield.
In regard to claim 8 Ordonez and Biricik as combined teaches [see for example Biricik “A gallium arsenide layer was epitaxially grown thereon to a thickness of about 5 microns. During growth of this layer it was doped with silicon at about 1.5.times.10.sup.16 /cm.sup.3 to form an n gallium arsenide conductive layer.” see this can be divided into multiple layers of small thicknesses] wherein said multi-layer shield may be conformed of same or different materials with same or different thickness and conductivities.
In regard to claim 9 Ordonez and Biricik as combined teaches wherein said 2D material serves as a photodiode or photoconductive detector [ see Ordonez “graphene field effect transistors with no physical gate (i.e. 2-terminal device biased by external electromagnetic source 290)”, see absorption of graphene] of infrared (IR) and/or visible light.
In regard to claim 10 Ordonez and Biricik as combined teaches wherein said 2D material is a homojunction diode [ see Ordonez “graphene field effect transistors with no physical gate (i.e. 2-terminal device biased by external electromagnetic source 290)” , see absorption of graphene, see that one side of the graphene is biased higher than the other, thus the photogenerated holes/electrons move in opposite directions, this is diode behavior because one side has more holes, the other side has more electrons] or a semiconductor/2D material heterojunction.
Claim(s) 11, 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ordonez and Biricik as combined and further in view of Hou et al. (see PTO-892 “Multilayer Black Phosphorus Near-Infrared Photodetectors”)
In regard to claim 11 Ordonez and Biricik as combined does not teach wherein said 2D material is black phosphorus.
See Hou “Compared with other 2D materials, black phosphorus not only has higher mobility in the order of 10,000 cm2/(Vs) [1], but also has broadband photo-response owing to its thickness dependent direct bandgap ranging from 0.3 eV to 2 eV”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Ordonez to include wherein said 2D material is black phosphorus.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that black phosphorus is known to give excellent results for detection.
In regard to claim 12 Ordonez Biricik and Hou as combined in claim 11 teaches wherein said 2D material is black phosphorus and said at least one semiconductor membrane is [see for example Biricik “A gallium arsenide layer was epitaxially grown thereon to a thickness of about 5 microns. During growth of this layer it was doped with silicon at about 1.5.times.10.sup.16 /cm.sup.3 to form an n gallium arsenide conductive layer.”] completely doped.
Conclusion
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893