Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Response to Arguments
The applicant's arguments filed September 3, 2026 regarding the Requirement
for Restriction/Election filed July 7, 2026 have been fully considered and are respectfully found persuasive. The Requirement for Restriction/Election is hereby withdrawn.
DETAILED ACTION
Specification
Title is objected to for failure to be sufficiently descriptive.
The specification has not been checked to the extent necessary to determine the
presence of all possible minor errors. The applicant's cooperation is requested in correcting any errors of which the applicant may become aware in the specification.
Claim Objections
Claim 24 is objected to because of the following informality:
In line 1, “the group” should be --a group--
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of AIA 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-15, 19, 21, and 24-30 are rejected under AIA 35 U.S.C. 102(a)(2) as
being anticipated by Kitajima et al. (U.S. Publication No. 20240105628; hereinafter “Kitajima”).
Regarding claim 1, Kitajima discloses a device, comprising: a first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a piezoelectric material (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); a first electrode ([0113] – first “IDT electrode”) disposed on ([0113]) the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); a second substrate (Fig. 7, 45); a first via (Fig. 7, first 46) extending through (Fig. 7) the second substrate (Fig. 7, 45) and coupled (Figs. 4/7; [0113]) to the first electrode ([0113] – first “IDT electrode”); and a first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) electrically coupled (Figs. 4/7; [0113]) to the first via (Fig. 7, first 46) and disposed between (Figs. 4/7; [0113]) the second substrate (Fig. 7, 45) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) of the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”).
Regarding claim 2, Kitajima discloses the device of claim 1, wherein the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) comprises a capacitor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]).
Regarding claim 3, Kitajima discloses the device of claim 1, wherein the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) comprises an inductor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]).
Regarding claim 4, Kitajima discloses the device of claim 1, wherein the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) comprises an interconnect (Fig. 7, 31) extending parallel (Figs. 4/7; [0113]) to the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”).
Regarding claim 5, Kitajima discloses the device of claim 1, further comprising an insulating material (Fig. 7, 3A’s spacer layer; [0108]) disposed between (Figs. 4/7; [0113]) the second substrate (Fig. 7, 45) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) of the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”), wherein the insulating material (Fig. 7, 3A’s spacer layer; [0108]) is disposed between (Figs. 4/7; [0113]) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”).
Regarding claim 6, Kitajima discloses the device of claim 5, wherein the insulating material (Fig. 7, 3A’s spacer layer; [0108]) is further disposed between (Figs. 4/7; [0113]) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) and the second substrate (Fig. 7, 45) of the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”).
Regarding claim 7, Kitajima discloses the device of claim 1, further comprising a first air cavity (Fig. 7; [0108] – first “air” “space” ) between (Fig. 7; [0108] – first “air” “space” ) the first electrode ([0113] – first “IDT electrode”) and the second substrate (Fig. 7, 45).
Regarding claim 8, Kitajima discloses the device of claim 7, wherein the first electrode ([0113] – first “IDT electrode”) is disposed in (Fig. 7; [0108]) the first air cavity (Fig. 7; [0108] – first “air” “space” ) surrounded by (Fig. 7; [0108]) the insulating material (Fig. 7, 3A’s spacer layer; [0108]).
Regarding claim 9, Kitajima discloses the device of claim 5, wherein the insulating material (Fig. 7, 3A’s spacer layer; [0108]) comprises a polymer (Fig. 7, 3A’s spacer layer; [0108]).
Regarding claim 10, Kitajima discloses the device of claim 7, further comprising a metal layer (Fig. 7, 5; [0077]) between (Fig. 7) the first air cavity (Fig. 7; [0108] – first “air” “space” ) and the second substrate (Fig. 7, 45).
Regarding claim 11, Kitajima discloses the device of claim 10, wherein the metal layer (Fig. 7, 5; [0077]) is coupled (Fig. 7) to a terminal (Fig. 7, ground terminal; [0077]) configured to couple (Fig. 7) to a reference voltage (Fig. 7, voltage at ground terminal; [0077]).
Regarding claim 12, Kitajima discloses the device of claim 7, further comprising: a second electrode ([0113] – second “IDT electrode”) disposed on the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); and a second air cavity (Fig. 7; [0108] – second “air” “space” ) separate from the first air cavity (Fig. 7; [0108] – first “air” “space” ) between the second electrode ([0113] – second “IDT electrode”) and the second substrate (Fig. 7, 45).
Regarding claim 13, Kitajima discloses the device of claim 12, further comprising: a third electrode ([0113] – third “IDT electrode”) in the first air cavity (Fig. 7; [0108] – first “air” “space” ); and a fourth electrode ([0113] – fourth “IDT electrode”) in the second air cavity (Fig. 7; [0108] – second “air” “space” ), wherein: the first ([0113] – first “IDT electrode”) and third electrodes ([0113] – third “IDT electrode”) comprise a first resonator (Fig. 4, first resonator in filters 121-123/131-132; Fig. 7, first resonator in 3A; [0070; [0113]) having a first resonant frequency (Fig. 4, first resonant frequency of first resonator in filters 121-123/131-132; Fig. 7, first resonant frequency of first resonator in 3A; [0070; [0113]); and the second ([0113] – second “IDT electrode”) and fourth electrodes ([0113] – fourth “IDT electrode”) comprise a second resonator (Fig. 4, second resonator in filters 121-123/131-132; Fig. 7, second resonator in 3A; [0070; [0113]) having a second resonant frequency (Fig. 4, second resonant frequency of second resonator in filters 121-123/131-132; Fig. 7, second resonant frequency of second resonator in 3A; [0070; [0113]).
Regarding claim 14, Kitajima discloses the device of claim 12, further comprising at least a third air cavity (Fig. 7; [0108] – third “air” “space”).
Regarding claim 15, Kitajima discloses the device of claim 12, further comprising: a wall (Fig. 7, 3A’s spacer layer wall; [0108]) comprising the insulating material (Fig. 7, 3A’s spacer layer; [0108]) disposed between (Fig. 7) the first air cavity (Fig. 7; [0108] – first “air” “space” ) and the second air cavity (Fig. 7; [0108] – second “air” “space” ); and a second via (Fig. 7, second 46) disposed through (Fig. 7) the second substrate (Fig. 7, 45) and through (Fig. 7) the wall (Fig. 7, 3A’s spacer layer wall; [0108]) and coupled (Fig. 7) to the second electrode ([0113] – second “IDT electrode”).
Regarding claim 19, Kitajima discloses the device of claim 1, wherein the first via (Fig. 7, first 46) comprises a monolithic metal via (Fig. 7, first 46; [0152]).
Regarding claim 21, Kitajima discloses the device of claim 1, further comprising a contact (Fig. 7, 43) on the second substrate (Fig. 7, 45), coupled (Fig. 7) to the first via (Fig. 7, first 46), and configured to couple (Fig. 7) the first via (Fig. 7, first 46) to an external circuit (Fig. 7, external circuit coupled to 3C; Fig. 4, 92 [0035]).
Regarding claim 24, Kitajima discloses the device of claim 1 integrated into a device selected from the group consisting of: a set-top box; an entertainment unit; a navigation device; a communications device; a fixed location data unit; a mobile location data unit; a global positioning system (GPS) device; a mobile phone ([0023]); a cellular phone; a smartphone ([0023]); a session initiation protocol (SIP) phone; a tablet; a phablet; a server; a computer; a portable computer; a mobile computing device; a wearable computing device ([0023]); a desktop computer; a personal digital assistant (PDA); a monitor; a computer monitor; a television; a tuner; a radio; a satellite radio; a music player; a digital music player; a portable music player; a digital video player; a video player; a digital video disc (DVD) player; a portable digital video player; an automobile; a vehicle component; an avionics system; a drone; and a multicopter.
Regarding claim 25, Kitajima discloses a method of fabricating a device, comprising: forming a first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a piezoelectric material (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); forming (Fig. 7) a first electrode ([0113] – first “IDT electrode”) on the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); forming (Fig. 7) a second substrate (Fig. 7, 45); forming (Fig. 7) a first via (Fig. 7, first 46) extending through (Fig. 7) the second substrate (Fig. 7, 45) and coupled (Fig. 7) to the first electrode ([0113] – first “IDT electrode”); and forming (Fig. 7) a first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) electrically coupled (Fig. 7) to the first via (Fig. 7, first 46) and between (Fig. 7) the second substrate (Fig. 7, 45) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) of the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”).
Regarding claim 26, Kitajima discloses the method of claim 25, further comprising forming (Fig. 7) an insulating material (Fig. 7, 3A’s spacer layer; [0108]) between (Fig. 7) the second substrate (Fig. 7, 45) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) of the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”), wherein: forming (Fig. 7) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) further comprises forming (Fig. 7) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) on the second substrate (Fig. 7, 45); and forming (Fig. 7) the insulating material (Fig. 7, 3A’s spacer layer; [0108]) further comprises forming (Fig. 7) the insulating material (Fig. 7, 3A’s spacer layer; [0108]) on (Fig. 7) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]).
Regarding claim 27, Kitajima discloses the method of claim 26, wherein forming (Fig. 7) the insulating material (Fig. 7, 3A’s spacer layer; [0108]) and the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) further comprises: forming (Fig. 7) a first portion (Fig. 7, first portion of 3A’s spacer layer; [0108]) of the insulating material (Fig. 7, 3A’s spacer layer; [0108]) on the second substrate (Fig. 7, 45); forming (Fig. 7) the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) on the first portion (Fig. 7, first portion of 3A’s spacer layer; [0108]) of the insulating material (Fig. 7, 3A’s spacer layer; [0108]); and forming (Fig. 7) a second portion (Fig. 7, second portion of 3A’s spacer layer; [0108]) of the insulating material (Fig. 7, 3A’s spacer layer; [0108]) on the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]).
Regarding claim 28, Kitajima discloses the method of claim 25, further comprising: disposing (Fig. 7) the second substrate (Fig. 7, 45) comprising the insulating material (Fig. 7, 3A’s spacer layer; [0108]) and the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) on the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising the first electrode ([0113] – first “IDT electrode”), wherein forming (Fig. 7) the first via (Fig. 7, first 46) further comprises: forming (Fig. 7) a void (Fig. 7, first 46; [0150]) through (Fig. 7) the second substrate (Fig. 7, 45) and the insulating material (Fig. 7, 3A’s spacer layer; [0108]) to the first electrode ([0113] – first “IDT electrode”); and forming (Fig. 7) a metal (Fig. 7, first 46; [0152]) in the void (Fig. 7, first 46; [0150]).
Regarding claim 29, Kitajima discloses an acoustic filter package, comprising: a package substrate (Fig. 7, 2); and a device (Fig. 7, 3A) comprising: a first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) comprising a piezoelectric material (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); a first electrode ([0113] – first “IDT electrode”) disposed on (Figs. 4/7; [0113]) the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); a second substrate (Fig. 7, 45); a first via (Fig. 7, first 46) extending through (Figs. 4/7; [0113]) the second substrate (Fig. 7, 45) and coupled to (Figs. 4/7; [0113]) the first electrode ([0113] – first “IDT electrode”); a first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) electrically coupled (Figs. 4/7; [0113]) to the first via (Fig. 7, first 46) and disposed between (Figs. 4/7; [0113]) the second substrate (Fig. 7, 45) and the first surface (Fig. 4, first surface of cover of first substrate of 121-123/131-132; Fig. 7, first surface of cover of first substrate of 3A; [0070; [0113] – “piezoelectric substrate”) of the first substrate (Fig. 4, first substrate of 121-123/131-132; Fig. 7, first substrate of 3A; [0070; [0113] – “piezoelectric substrate”); and a contact (Fig. 7, first 43) coupling (Figs. 4/7; [0113]) the first via (Fig. 7, first 46) to the package substrate (Fig. 7, 2).
Regarding claim 30, Kitajima discloses the acoustic filter package of claim 29, wherein the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) comprises one of a capacitor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) and an inductor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-17 and 22-23 are rejected under 35 U.S.C. 103 as being
unpatentable over Kitajima in view of Eid et al. (U.S. Publication No. 20200235716; hereinafter “Eid”).
Regarding claim 16, Kitajima discloses the device of claim 1. Kitajima does not teach wherein the second substrate comprises a material having a thermal conductivity greater than twenty (20) watts per meter-kelvin (W/(m⋅K)).
Eid, however, does teach wherein the second substrate (Fig. 1, 104; [0044]) comprises a material having a thermal conductivity greater than twenty (20) watts per meter-kelvin (W/(m⋅K)) (Fig. 1, 104; [0044]).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the substrate material of Eid because it is hermetic and may not require an additional coating of the cavity with a hermetic material around the resonator in order to hermetically seal the resonator thereby reducing size and cost and increasing simplicity (Eid [0044]).
Regarding claim 17, Kitajima discloses the device of claim 1. Kitajima does not teach wherein the second substrate comprises a material having a thermal conductivity greater than thirty (30) watts per meter-kelvin (W/(m⋅K)).
Eid, however, does teach wherein the second substrate (Fig. 1, 104; [0044]) comprises a material having a thermal conductivity greater than thirty (30) watts per meter-kelvin (W/(m⋅K)) (Fig. 1, 104; [0044]).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the substrate material of Eid because it is hermetic and may not require an additional coating of the cavity with a hermetic material around the resonator in order to hermetically seal the resonator thereby reducing size and cost and increasing simplicity (Eid [0044]).
Regarding claim 22, Kitajima discloses the device of claim 1. Kitajima does not teach wherein the second substrate comprises one of high-resistivity silicon (HRS), porous silicon (pSi), and alumina.
Eid, however, does teach wherein the second substrate (Fig. 1, 104; [0044])comprises one of high-resistivity silicon (HRS), porous silicon (pSi), and alumina (Fig. 1, 104; [0044]).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the substrate material of Eid because it is hermetic and may not require an additional coating of the cavity with a hermetic material around the resonator in order to hermetically seal the resonator thereby reducing size and cost and increasing simplicity (Eid [0044]).
Regarding claim 23, Kitajima discloses the device of claim 1, further comprising a filter comprising a surface acoustic wave (SAW) resonator comprising the first electrode ([0113] – first “IDT electrode”) coupled to the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]), wherein the first circuit element (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) comprises at least one of capacitor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]) and an inductor (Fig. 4, 15; Fig. 7, 3B; [0038]; [0071]). Kitajima does not teach a metal-insulator-metal (MIM).
Eid, however, does teach a metal-insulator-metal (MIM) (Fig. 1, 150).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the metal-insulator-metal (MIM) of Eid because it would provide a loss tangent dielectric material thereby decreasing loss tangent (Eid [0078]).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over
Kitajima in view of Hsu et al. (U.S. Publication No. 20200153409; hereinafter “Hsu”).
Regarding claim 18, Kitajima teaches the device of claim 1. Kitajima does not teach wherein a thickness of the second substrate is in a range of sixty (60) to one hundred twenty-five (125) microns.
Hsu, however, does teach wherein a thickness of the second substrate is in a range of sixty (60) to one hundred twenty-five (125) microns (Fig. 3C, 41; [0049]).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the substrate thickness of Hsu because it is ultrathin thereby reducing size and cost and increasing simplicity (Hsu [0049]).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over
Kitajima in view of Takano et al. (U.S. Publication No. 20200127633; hereinafter “Takano”).
Regarding claim 20, Kitajima teaches the device of claim 1, wherein the first via (Fig. 7, first 46) comprises a cylindrical layer (Fig. 7, first 46; [0152]). Kitajima does not teach wherein the first via comprising a first metal and a core comprising a second material.
Takano, however, does teach wherein the first via (Fig. 3B, 26) comprising a first metal (Fig. 3B, side walls 22; [0059]) and a core (Fig. 3B, 43) comprising a second material (Fig. 3B, 43; [0069]).
It would have been obvious to one with ordinary skill in the art before the effective filing date of the claimed invention to have modified the device of Kitajima to include the core of Takano because it fills the via while leaving the via’s dimensions unchanged thereby increasing protection while maintaining conductivity (Takano [0069]).
Conclusion
Any inquiry concerning this communication should be directed to MONICA MATA
whose telephone number is (571) 272-8782. The examiner can normally be reached on Monday thru Friday from 7:30 AM to 5:00 PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s
supervisor, Dedei Hammond, can be reached on (571) 270-7938. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/MONICA MATA/
Patent Examiner, Art Unit 2837
29 September 2026
/EMILY P PHAM/Primary Examiner, Art Unit 2837
