DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oue et al. (US 2019/0281248).
Regarding claims 1, 7, and 8, Oue discloses a non-transitory computer readable medium storing a program causing a computer to execute a process for controlling an image processing apparatus, a method for controlling an image processing apparatus, and an image processing apparatus comprising:
a memory (see Fig. 1 and para 20, DRAM 50);
a processor (see Fig. 1 and paras 21 and 24, DMA controller 20 which is a CPU); and
a first cache memory used by the processor (see Fig. 1 and paras 21 and 31, an image processing line buffer located in DRAM 50 is a cache memory),
wherein the processor is configured to:
store, in the first cache memory, pixel data items arranged in a line in a main-scanning direction, the pixel data items being stored in units of a plurality of lines (see paras 20-22, 30-32, and 36, line buffer located in DRAM 50 is a cache memory for storing pixel data for lines of a color image);
execute a shift process on a plurality of pixel data items stored in the first cache memory for each of pixel blocks to prevent deviation in a sub-scanning direction in forming an image, the pixel block being composed of a predetermined number of pixel data items and serving as a processing unit (see paras 27-28 and 30-32, sub-scanning shift processing is performed on the pixel block data stored in the line buffer); and
perform a storing process in which among the pixel data items in the plurality of lines that are stored in the first cache memory, pixel data items to be stored in an area with consecutive addresses in the memory as a result of the shift process are collectively stored in the memory (see paras 36, 38, 45-49, and 69-70, a row buffer is used to store pixel data in an area with consecutive addresses as a result of shift processing).
Regarding claim 2, Oue further discloses wherein the processor is configured to: in the storing process, collectively store, in the memory for each pixel block, pixel data items in the pixel block and pixel data items in a neighboring pixel block neighboring the pixel block, the pixel block and the neighboring pixel block having consecutive addresses, the pixel data items being collectively stored in the main-scanning direction in order from a position of an origin in the pixel data items in the plurality of lines that are stored in the first cache memory (see paras 32, 36, 38, 45-49, 52-53, and 69-70, a row buffer is used to store pixel data in an area with consecutive addresses as a result of shift processing, neighboring pixel blocks, are processed in consecutive order).
Regarding claim 3, Oue further discloses wherein the processor is configured to: provide each of the pixel data items already stored in the memory with an identification indicating that the pixel data item has been stored and exclude the pixel data item provided with the identification from a target for the storing process (see paras 32-33, addresses are allocated to respective pixel data in order from the head pixel for each line).
Regarding claim 4, Oue further discloses wherein the first cache memory has a lower capacity than a capacity of an entire data amount of the image (see paras 36-39, the line buffer has less memory capacity than the storage area of DRAM 50, which is less than the entire data amount of the image).
Regarding claim 5, Oue further discloses wherein the processor is configured to: in response to completion of the storing process for all of the pixel data items in one line of the pixel data items in the plurality of lines that are stored in the first cache memory, store, in an area of the first cache memory, pixel data items in a line succeeding a line of the pixel data items stored in the first cache memory, the area having been used to store the pixel data items in the line for which the storing process is completed, the pixel data items being stored at a time point when the storing process for all of the pixel data items in the line is completed (see paras 36-38, 45-49, and 69-70, sub-scanning shift processing is performed on the pixel block data stored in the line buffer, a row buffer is used to store pixel data in an area with consecutive addresses as a result of shift processing).
Regarding claim 6, Oue further discloses wherein the memory has a second cache memory, and wherein the processor is configured to: store the pixel data items in the second cache memory in the storing process (see Fig. 1 and paras 38, 47-49, and 69-70, a row buffer, which is a second cache memory, is used to store pixel data in an area with consecutive addresses as a result of shift processing).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. To further show the state of the art please refer to the attached Notice of References Cited.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARK R MILIA whose telephone number is (571) 272-7408. The examiner can normally be reached Monday-Friday, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Akwasi Sarpong can be reached at 571-270-3438. The fax number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MARK R MILIA/ Primary Examiner, Art Unit 2681
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