Detailed Action
The current Office Action is in response to the papers submitted 07/17/2026. Claims 1, 3 – 8, 10 – 15, and 17 - 21 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3 – 4, 6 – 8, 10 – 11, 13 – 15, 17 – 18, and 20 - 21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roh (Pub. No.: 2017/0060443) referred to as Roh in view of Hida et al. (Pub. No.: 2012/0260025) referred to as Hida in view of Sheperek et al. (Pub. No.: 2020/0133754) referred to as Sheperek in view of Lee (EP 3706003) referred to as Lee.
Regarding claim 1, Roh teaches a memory management method used for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, and the memory management method comprising [Fig. 1; 0038-0039; A flash-based SSD comprising physical blocks and a controller]:
in an initialization operation, setting multiple physical units including a first physical unit among the plurality of physical units to be operated in a first operation mode, wherein in the first operation mode, the multiple physical units are programmed based on a first programming mode, and the first physical unit comprises only a part of the multiple physical units [Paragraphs 0037 - 0039, 0043 – 0044, 0058, 0065, and 0070 – 0074; The SSD is configured to perform write operations using different operating modes. The modes correspond to different levels of performance and correspond to use of m-bit cell modes and single-bit cell modes. It is recognized that read/write performance in the SLC mode is higher, with the drawback of lower capacity and service life. MLC, TLC, and QLC provide greater capacities and lifespans with lower performance. The SSD is initially configured to use one of the modes as a preset operating mode. The preset mode is one in which the bandwidth is most restricted for the host’s target bandwidth. Hence, Roh discloses initially setting multiple physical cells of physical blocks of the SSD to use a higher capacity operating mode associated with a lower bandwidth writing mode which leads to lower performance and higher lifespan associated with increased ISPP program times. The SSD is a non-volatile that includes flash memory organized into blocks. Each block is a physical unit of storage. Each block is also a part of the plurality of physical units that make up the SSD device];
receiving a plurality of commands from a host system, wherein the plurality of commands comprise a first command and a second command, the first command instructs to store a first data to a first storage unit, and the second command instructs to mark a second data stored in a second storage unit as an invalid data [Paragraphs 0034 – 0035; Host device transmits data I/O requests, including write, read, and erase commands. A host write command corresponds to the first command to store data. A host erase command corresponds to the second command to mark data invalid]; and
setting the first physical unit to be operated in a second operation mode, wherein in the second operation mode, the first physical unit is programmable based on a second programming mode, and the first programming mode is different from the second programming mode [Paragraphs 0043, 0070, 0072 – 0074; Roh discloses switching from MLC operating mode to SLC operating mode based on a comparison of the target bandwidth of the host and the maximum bandwidth of the storage device. When target bandwidth is set high, MLC blocks need to be set to SLC writing mode to provide increased write bandwidth (e.g., by setting ISPP to the minimum time to achieve maximum throughput to handle the increased write traffic, wherein a higher performance mode is achieved by using SLC writing mode to write to the memory. The changing of modes shows the programming modes are different from each other and units of storage are programmable based on the mode they are in].
Row may not specifically disclose the limitation(s) of storing data in logical units, marking data in a logical unit as invalid data, in response to that a total number of the second command reaches a first threshold or a total amount of the second data reaches a second threshold, triggering an operation of changing an operation mode of the first physical unit, and in the operation of changing the operation mode of the first physical unit temporarily setting the first physical unit to be operated in the second operation mode and after exceeding a time frame, reverting the first physical unit to be operated in the first operation mode.
Hida discloses storing data in logical units and marking data in a logical unit as invalid data [Paragraphs 003, 0019, 0024, and 0030; Hida discloses that host commands employ logical block addressing, wherein separating logical capacity from physical capacity permits improved management of user data by a controller of an SSD and the use of host erase commands (e.g. trim commands) for marking blocks as containing invalid data. Support for trim commands eliminates useless data copying thus improving device lifetime. Hida further discloses that execution of the trim command may add write activity which may cause increased load associated with executing commands. Blocks of the cache area may be managed using SLC control while blocks of the user data area may be managed using MLC control].
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to employ trim commands and logical addressing as taught by Hida in the host commands of Roh in order to eliminate useless data copying and improve management of user data in the storage device.
Roh and Hida may not specifically disclose the limitations of in response to that a total number of the second command reaches a first threshold or a total amount of the second data reaches a second threshold, triggering an operation of changing an operation mode of the first physical unit, and in the operation of changing the operation mode of the first physical unit temporarily setting the first physical unit to be operated in the second operation mode and after exceeding a time frame, reverting the first physical unit to be operated in the first operation mode.
Sheperek discloses in response to that a total number of the second command reaches a first threshold or a total amount of the second data reaches a second threshold, triggering an operation of changing an operation mode of the first physical unit, and in the operation of changing the operation mode of the first physical unit, temporarily setting the first physical unit to be operated in the second operation mode [Paragraph 0043; Program/erase count information is the number of second command since it erases the data at a given location with new data that is considered valid or is data that the system uses to know the location is considered erased. The programming mode is based on the program/erase count and is temporary during the age of the memory switching between SLC, MLC, TLC, and QLC].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sheperek in Roh in view of Hida, because it aids in maintaining optimum performance of the memory based on the age and use of the memory [Paragraph 0043].
However, Roh and Hida and Sheperek may not specifically disclose the limitation(s) of after exceeding a time frame, reverting the first physical unit to be operated in the first operation mode.
Lee discloses after exceeding a time frame, reverting the first physical unit to be operated in the first operation mode [Paragraphs 0055 – 0058; Storage is converted from TLC to SLC temporarily for a time frame that the faster access of SLC is needed. Once the time frame of the need is exceeded the memory in an SLC mode is converted back to the original TLC mode].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing data of the claimed invention to incorporate Lee in Roh and Hida and Sheperek, because it increases write performance during periods of high write traffic.
Regarding claim 3, Roh teaches setting the first physical unit to be operated in a second operation mode, wherein in the second operation mode, the first physical unit is programmable based on a second programming mode, and the first programming mode is different from the second programming mode [Paragraphs 0043, 0070, 0072 – 0074].
Hida discloses storing data in logical units and marking data in a logical unit as invalid data [Paragraphs 003, 0019, 0024, and 0030].
Sheperek discloses in response to that a total number of the second command reaches a first threshold or a total amount of the second data reaches a second threshold, triggering an operation of changing an operation mode of the first physical unit, and in the operation of changing the operation mode of the first physical unit, temporarily setting the first physical unit to be operated in the second operation mode temporarily setting the first physical unit to be operated in the second operation mode [Paragraph 0043].
Lee discloses determining that at least one of a total amount of the first data reaches a third threshold and a total amount of a third data stored in the second operation reaches a fourth threshold; and in response to that the at least one of the total amount of the first data reaches the third threshold and the total amount of the third data stored in the second operation mode reaches the fourth threshold, determining that a target condition is satisfied (P8 – P10 and P15 – P16; Detecting the number of write I/O requests or amount of write data has increased above a threshold and enabling the fast write mode based on the number or amount of write I/O requests. That is, Lee discloses a similar device where host write data is buffered using blocks employing an SLC writing mode, and where TLC blocks may be reconfigured to write in SLC writing mode for buffering purposes in response to detecting that a number of write requests or amount of write data exceeds a threshold level. Hence, Lee discloses, in response to high write traffic, changing a writing mode to SLC from TLC mode. The storage device 230 is initially configured to use TLC mode, and may use an SLC mode to temporarily store data which may later be written using TLC mode as part of a flush process. A portion of the blocks in the TLC mode may be borrowed for use as a fast write buffer written using SLC mode. The fast write mode is activated in response to receiving a large amount of data at a high speed from an external source, such as a host. By supporting the fast write mode, the performance of the storage device in storing the data during a sudden increase in write load is improved. Hence, Lee teaches storage device comprising storage blocks which may be written using a high capacity (TLC) mode and high performance (SLC) mode, switching blocks initially configured in a TLC mode to an SLC mode to accommodate large amounts of write data in a short time span].
Regarding claim 4, Hida discloses the commands include a first command to write [Paragraph 0030] and a second command to mark data as invalid [Paragraph 0024].
Sheperek discloses temporarily changing the mode of operation of a physical unit of storage [Paragraph 0043].
Lee discloses after setting the first physical unit to be operated in the second operation mode, maintaining the first physical unit to be operated in the second operation mode within the time frame [Paragraphs 0055 – 0058; Storage is converted from TLC to SLC temporarily for a time frame that the faster access of SLC is needed. Once the time frame of the need is exceeded the memory in an SLC mode is converted back to the original TLC mode].
Regarding claim 6, Roh teaches wherein in a physical unit programmed based on the first programming mode, a memory cell is configured to store m bits of data, and
in a physical unit programmed based on the second programming mode, a memory cell is configured to store n bits of data, and m is greater than n [Paragraphs 0070 – 0073; Physical blocks of the memory device may be configured to store m-bits of data, e.g. 3, for TLC programming mode, or n bits of data, e.g. 1, for SLC programming mode].
Regarding claim 7, Roh teaches a writing performance of a host writing operation performed through the second programming mode is higher than a writing performance of a host writing operation performed through the first programming mode [Paragraphs 0070 – 0073; Write performance in SLC mode is higher than write performance in TLC mode].
Claims 8, 10 – 11, and 13 – 14 are rejected on similar grounds as claims 1, 3 – 4, and 6 - 7 as they are a device performing the method of claims 1 and 6 - 7. Roh teaches a memory storage device [200, Fig 1] comprising a connection interface unit, coupled to a host system [Fig 1; Paragraph 0036; Address and data bus interfaces for coupling the SSD to a host] a rewritable non-volatile memory module, comprising a plurality of physical units [Fig 1; Paragraph 0038; Flash memory comprising physical blocks] and a memory control circuit unit [210, Fig 1], coupled to the connection interface unit [Fig 1; Paragraph 0036; Address and data bus interfaces for coupling the SSD to a host] and the rewritable non-volatile memory module storage controller [210, Fig 1] coupled to the interface for performing the method of claim 1 [Fig 1].
Claims 15, 17 – 18, and 20 - 21 are rejected on similar grounds as claims 1 and 6 - 7 as they are circuit performing the methods of claims 1, 3 – 4, and 6 - 7. Roh teaches a memory control circuit unit [210, Fig. 1; Paragraphs 0035-0036], configured to control a rewritable non-volatile memory module [220, Fig. 1; Paragraphs 0035-0036], wherein the rewritable non-volatile memory module [220, Fig. 1; Paragraphs 0035-0036] comprises a plurality of physical units [Paragraph 0038; Flash memory comprising physical blocks], and the memory control circuit unit [210, Fig. 1; Paragraphs 0035-0036] comprises a host interface, coupled to a host system [Fig 1; Paragraph 0036; External interfaces comprising address and data bus interfaces for communication between the host and the SSD controller], a memory interface [Fig 1; Paragraph 0036; Internal communication interfaces to connect the storage controller to internal components, e.g. the flash memory], coupled to the rewritable non-volatile memory module [220, Fig. 1; Paragraphs 0035-0036], and a memory management circuit [210, Fig. 1; Paragraphs 0035-0036], coupled to the host interface [Fig 1; Paragraph 0036; External interfaces comprising address and data bus interfaces for communication between the host and the SSD controller] and the memory interface [Fig 1; Paragraph 0036; Internal communication interfaces to connect the storage controller to internal components, e.g. the flash memory], wherein the memory management circuit [210, Fig. 1; Paragraphs 0035-0036] is configured to perform the method of claim 1 [See claim 1 rejection].
Claim(s) 5, 12, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Roh (Pub. No.: 2017/0060443) referred to as Roh in view of Hida et al. (Pub. No.: 2012/0260025) referred to as Hida in view of Sheperek et al. (Pub. No.: 2020/0133754) referred to as Sheperek in view of Lee (EP 3706003) referred to as Lee as applied to claims 4, 11, and 18 above, and further view of Muchherla (Pub. No.: 2018/0285258).
Referring to claim 5, Roh and Hida disclose the data consolidation operation releases a free physical unit by moving a valid data [Roh, Paragraphs 0038 and 0061; Hida, Paragraphs 0024 – 0026 and 0048 – 0049; The combination discloses performing garbage collection to generate free blocks by moving valid data, thus permitting the source block to be erased].
However, Roh in view of Hida in view of Sheperek in view of Lee may not specifically disclose the limitation(s) of prohibiting or deferring execution of a data consolidation operation within the time frame.
Muchherla discloses prohibiting or deferring execution of a data consolidation operation within the time frame [Paragraphs 0014-0018 and 0046; Specifically, Muchherla discloses principles which would have led the skilled artisan to avoid executing garbage collection operations for releasing free blocks at the same time as host sequential writes. When operations of both types are executed at the same time, the sequential write data from the host writes are mixed with the random write data resulting from garbage collection. Mixing these types of data is undesirable because it causes increased write amplification, which reduces the lifespan of the SSD. To avoid this, Muchherla teaches performing garbage collection in the background (“during idle time of the memory”). Accordingly, Muchherla teaches controlling a time when the SSD performs garbage collection operations to be different from a time when sequential host writes are being executed. This control over scheduling of garbage collection operations constitutes prohibiting or deferring garbage collection during a time frame where writes are performed. A time period in which an SLC capacity is increased to accommodate increased host write traffic is not an idle time of the memory. Hence, the skilled artisan would have reasoned based on the principles disclosed by Muchherla that a memory device should refrain from or delay executing garbage collection operations while host write traffic is high until the memory is idle, thereby avoiding the scenario where random writes from the garbage collection process are stored with sequential host write data, thus increasing write amplification and reducing the lifespan of the SSD].
Accordingly, it would have been obvious to the skilled artisan before the effective filing date of the claimed invention to prohibit or delay execution of garbage collection operations during periods of high host write activity, or otherwise to restrict execution of such operations to idle times, as taught by Muchherla to the system of Roh in view of Hida in view of Sheperek in view of Lee in order to avoid mixing sequential host data with random garbage collected data, thereby avoiding reducing the lifespan of the SSD via increased write amplification.
Claims 12 and 19 are rejected on similar grounds as claim 5, as they are the device and circuit performing the method of claim 5.
Response to Arguments
Applicant's arguments filed 07/17/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 10 – 13 that the independent claims and all dependent claims allowed since Lee cannot revert the mode switch which is taught by Sheperek based on aging of the memory. After careful consideration of the applicant's arguments the examiner respectfully disagrees.
Lee converts the mode of the memory based on different criteria than what Sheperek uses to switch the mode of the memory. Lee discloses converting memory from a TLC mode to an SLC mode during a write intensive period to improve data access times and then convert the memory in SLC mode back to SLC when the write intensive period is over. Sheperek is used to teach converting the memory based on an age of the memory to reduce errors. The combination would allow the memory to convert from TLC to SLC and then back to TLC based on access speed needs of the system and then convert and stay in SLC mode based on age to prevent errors.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/Primary Examiner, Art Unit 2138
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