Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arisaka et al. (US PG. Pub. 2015/0179560) in view of Nah et al. (US PG. Pub. 2006/0131732).
Regarding claim 1 – Arisaka teaches a module comprising (fig. 12): a substrate (81 [paragraph 0146] Arisaka states, “core substrate 81”) including a first surface (81A [paragraph 0148] Arisaka states, “upper surface 81A”); a first land electrode (84 [paragraph 0149] Arisaka states, “wiring layer 84”) arranged on the first surface (81A); a first electronic component (90 [paragraph 0157] Arisaka states, “semiconductor chip 90”) mounted on the substrate (81) with the first land electrode (84) being interposed (claimed structure shown in figure 12); and an insulating film (86 [paragraph 0177] Arisaka states, “solder resist layer 86”) partially covering the first land electrode (86), wherein the substrate (81) is provided with a first opening (81X equivalent in size to that of 20X [paragraph 0148 & 0034] Arisaka states, “through holes 81X…The diameter of the through hole 20X and the through electrode 21 may be, for example, approximately 100 to 200 .mu.m.”) passing through the substrate (81) in a thickness direction of the substrate (81) within a projection area of the first land electrode (84), the first electronic component (90) is electrically connected to the first land electrode (84) in an exposed area (86x [paragraph 0155] Arisaka states, “the connection pad P5 and the opening 86X may each be circular with a diameter of approximately 50 to 100 .mu.m as viewed from above”) in the first land electrode (84) exposed without being covered with the insulating film (86; claimed structure shown in figure 12), and the first opening (81X equivalent to 20X with a diameter of 100-200um) is larger than the exposed area (86X with a diameter of 50-100um).
Arisaka fails to teach wherein the first opening is an assembly of a plurality of first opening elements, and the plurality of first opening elements are located within a projection area of a single piece of the first land electrode.
Nah teaches wherein the first opening (fig. 1, openings 50a & 50b) provided in the substrate (14 [paragraph 0017] Nah states, “PCB 14”) is an assembly of a plurality of first opening elements (see plural openings in substrate 14 where vias 50a & 50b are present [paragraph 0019] Nah states, “plurality of second thermal vias 50a-50d”), and the plurality of first opening elements (see plural openings in substrate 14 where vias 50a & 50b are present) are located within a projection area (area shown to overlap the first land electrode 32) of a single piece of the first land electrode (32 [paragraph 0017] Nah states, “first solder pad 32”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module having a first opening within a substrate as taught by Arisaka with the first opening is a plurality of first opening elements located within a projection area of a single piece of the first land electrode as taught by Nah because Nah states, “the thermally conductive nature of vias 50a-d may enable vias 50a, 50b to carry heat from solder pad 32 to pad 58a and layer 59a, and enable vias 50c, 50d to carry heat from solder pad 34 to pad 58c and layer 59c…Thus, thermally conductive element 26, vias 44, 50, pads 58 and layers 59 provide thermally conductive pathways for carrying heat from chip 12 and thereby lowering the temperature of chip 12. A lower operating temperature may extend the operating life of chip 12 and reduce degradation of the solder joints, e.g., cracking, at terminals 20, 22.” [paragraph 0025].
Regarding claim 2 – Arisaka in view of Nah teach the module according to claim 1, wherein the first land electrode (Arisaka; fig. 12, 84) extends to outside of a projection area of the first electronic component (90; claimed structure shown in figure 12), and at least a part of the first opening (81X) is located outside the projection area of the first electronic component (90; claimed structure shown in figure 12).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arisaka et al. in view of Nah et al. as applied to claim 1, and further in view of Kim et al. (US PG. Pub. 2011/0304015)
Regarding claim 3 – Arisaka in view of Nah teach the module according to claim 1, but fails to teach wherein the first electronic component is covered with a sealing resin, a shield film is arranged to cover at least a part of an outer surface of a sealing resin, and a first grounding electrode electrically connected to the shield film is arranged on the first surface, and the substrate is provided with a first grounding opening passing through the substrate in the thickness direction within a projection area of the first grounding electrode.
Kim teaches wherein a first electronic component (fig. 3, 200d [paragraph 0066] Kim states, “semiconductor chip 200d”) is covered with a sealing resin (400c [paragraph 0065] Kim states, “The third region 400c defined by the shielding can 300c on the substrate 100c may be a cavity or may be sealed by the encapsulation material 203”), a shield film (300c) is arranged to cover at least a part of an outer surface of a sealing resin (400c), and a first grounding electrode (see electrode connected to shield film 300c) electrically connected to the shield film (300c) is arranged on the first surface (top surface of substrate 100c), and the substrate (100c) is provided with a first grounding opening (see via connecting shield film 300c to bottom electrode 600) passing through the substrate (100c) in the thickness direction within a projection area of the first grounding electrode (claimed structure shown in figure 3).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the module having the electronic component on the substrate as taught by Arisaka in view of Nah with a shield film covering a sealing resin and electrically connected to a grounding electrode on the first surface of the substrate with a grounding opening passing through the substrate as taught by Kim because Kim states regarding these features, “The semiconductor package can prevent or substantially reduce electromagnetic interference (EMI)” [Abstract].
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 and 9 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Barcley (US PG. Pub. 2003/0029637) discloses a circuit board assembly with heat transfer vias.
Viswanathan et al. (US PG. Pub. 2018/0317312) discloses a packaged microelectronic component mounting.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847
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