Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-6) in the reply filed on 12/24/2025 is acknowledged. Claim 7 has been withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida (US 20190165130 A1) in view of Makabe (US 20230036388 A1) and Sugawara et al. (US 20210257219 A1).
Regarding claim 1, Yoshida discloses a method for manufacturing a semiconductor device, comprising: forming a first insulating layer (21) on a first nitride semiconductor layer (14) having a first principal surface (Fig. 3C);
forming, on the first insulating layer, a mask (22) including a first mask opening (22a) through which a portion of the first insulating layer is exposed (Fig. 3C);
forming a first opening (21a) in the first insulating layer through the first mask opening, to expose a portion of the first nitride semiconductor layer (Fig. 3A);
forming a first electrode (15) on the second nitride semiconductor layer, so as to cover a boundary line between the second nitride semiconductor layer and the first insulating layer, through the first mask opening (Fig. 4B);
However, Yoshida does not disclose a first electrode made of a metallic layer, forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening, through the first mask opening; and removing the mask after the forming the first electrode.
On the other hand, Makabe disclose forming a second nitride semiconductor layer (331s, similar to GaN layer of claimed invention where the layer is significantly larger to show multiple layers are formed on each other, Fig. 22) on the first nitride semiconductor layer inside the first opening, through the first mask opening (210s, Fig. 14), and a first electrode (141) made of a metallic layer (paragraph 57, made of a plurality of metal layers).
Neither Yoshida nor Makabe disclose removing the mask after the forming the first electrode.
However, Sugawara et al. disclose removing the mask after the forming the first electrode (22) (mask is still formed when electrodes 22 and 24 are formed, and the mask is removed in Fig. 5 and 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Makabe and Sugawara such that a first electrode made of a metallic layer, forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening, through the first mask opening; and removing the mask after the forming the first electrode. Doing so would minimize contact resistance and protect underlying semiconductor from fabrication damage.
Regarding claim 2, Yoshida discloses the method for manufacturing the semiconductor device as claimed in claim 1, wherein the mask includes a second mask opening (22b) through which another portion of the first insulating layer is exposed (21b, Fig 3A-3C), the method further comprising:
forming a second opening in the first insulating layer (21b) through the second mask opening (22b), to expose another portion of the first nitride semiconductor layer, simultaneously the forming of the first opening (Fig. 3A-C);
forming a second electrode (32) on the third nitride semiconductor layer (16) through the second mask opening, so as to cover a boundary line between the third nitride semiconductor layer and the first insulating layer, simultaneously as the forming of the first electrode (Fig. 4A-4C).
However, Yoshida does not disclose forming a third nitride semiconductor layer on the first nitride semiconductor layer inside the second opening through the second mask opening, simultaneously as the forming the second nitride semiconductor layer.
On the other hand, Makabe discloses forming a third nitride semiconductor layer (331D, Fig. 22, large nitride layer is similar in shape to the one in the claimed invention, therefore taken to have multiple layers) on the first nitride semiconductor layer inside the second opening (122D) through the second mask opening, simultaneously as the forming the second nitride semiconductor layer (Fig. 22).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Makabe and Sugawara such that forming a third nitride semiconductor layer on the first nitride semiconductor layer inside the second opening through the second mask opening, simultaneously as the forming the second nitride semiconductor layer. Doing so would prevent contamination and optimize material interface.
Regarding claim 8, Yoshida does not disclose forming the first electrode covers an entire upper surface of the second nitride semiconductor layer.
However, Makabe discloses forming the first electrode (132S, Fig. 14) covers an entire upper surface of the second nitride semiconductor layer (131S, Fig. 14). It is shown in Fig. 14 of Makabe that the first electrode nearly covers the entire upper surface of the second nitride semiconductor layer. It would be obvious to one of ordinary skill in the art to expand the first electrode such that it covers the entire second nitride semiconductor layer. In re Japikse, 181, F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Makabe and Sugawara such that forming the first electrode covers an entire upper surface of the second nitride semiconductor layer. Doing so would optimize gate control and electric field distribution.
Regarding claim 9, Yoshida does not disclose forming the first electrode covers an entire upper surface of the second nitride semiconductor layer and a portion of an upper surface of the second nitride semiconductor layer, through the first mask opening.
However, Makabe discloses forming the first electrode (132S, Fig. 14) covers an entire upper surface of the second nitride semiconductor layer (131S, Fig. 14). It is shown in Fig. 14 of Makabe that the first electrode nearly covers the entire upper surface of the second nitride semiconductor layer. It would be obvious to one of ordinary skill in the art to expand the first electrode such that it covers the entire second nitride semiconductor layer. In re Japikse, 181, F.2d 1019, 86 USPQ70 (CCPA 1950).
However, neither Yoshida nor Makabe disclose forming the first electrode covers an entire upper surface of the second nitride semiconductor layer and a portion of an upper surface of the second nitride semiconductor layer, through the first mask opening.
On the other hand, Sugawara discloses forming first electrode (22) through the first mask opening (51X, Fig. 4)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Makabe and Sugawara such that forming the first electrode covers an entire upper surface of the second nitride semiconductor layer and a portion of an upper surface of the second nitride semiconductor layer, through the first mask opening. Doing so acts as a self-aligned field plate that manages electric field and optimizes device performance.
Regarding claim 10, Yoshida does not disclose the forming the first electrode forms the metallic layer including a laminate of a plurality of metal films.
However, Makabe discloses the forming the first electrode forms the metallic layer including a laminate of a plurality of metal films (paragraph 56)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Makabe and Sugawara such that the forming the first electrode forms the metallic layer including a laminate of a plurality of metal films. Doing so is required because no single metal can satisfy all the electrical, thermal, and mechanical demands of creating a reliable semiconductor contact.
Claims 3-6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Makabe (US 20230036388 A1) and Sugawara et al. (US 20210257219 A1) as applied to claim 1 above, in further view of Matsuda (US 20180197978 A1).
Regarding claim 3, Yoshida does not disclose the method for manufacturing the semiconductor device as claimed in claim 1, further comprising, after the forming the first electrode, forming a second insulating layer on the first insulating layer, so as to cover the first electrode; and forming a gate electrode on the second insulating layer.
However, Matsuda discloses the method for manufacturing the semiconductor device as claimed in claim 1, further comprising, after the forming the first electrode (20), forming a second insulating layer (32A) on the first insulating layer (30), so as to cover the first electrode (22); and forming a gate electrode (24A) on the second insulating layer (Fig. 8B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida, Makabe and Sugawara in view of Matsuda to have a second insulating layer on the first insulating layer covering the electrode of a high electron mobility transistor. Doing so would suppress gate leakage current, and passivate the surface states and control the electric field distribution.
Regarding claim 4, none of the prior references disclose the method for manufacturing the semiconductor device as claimed in claim 3, wherein an upper surface of the second nitride semiconductor layer is an N-polar surface.
However, Makabe discloses the channel layer (113) has an N-polar surface (paragraph 48).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Makabe such that the upper surface of the second nitride semiconductor layer is an N-polar surface. Doing so would enable superior electron confinement and enable high density two-dimensional electron gas (2DEG).
Regarding claim 5, Yoshida discloses the method for manufacturing the semiconductor device as claimed in claim 3, further comprising: forming a third opening (21c) in the second insulating layer and the first insulating layer (21), the forming the gate electrode (33), wherein the gate electrode is formed to make contact with the first nitride semiconductor layer (14) through the third opening (Fig. 5B).
Yoshida does not disclose the second insulating layer.
Matsuda discloses a second insulating layer (32A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida, Makabe and Sugawara in view of Matsuda to have a second insulating layer on the first insulating layer of a high electron mobility transistor. Doing so would suppress gate leakage current and enhance breakdown voltage.
Regarding claim 6, none of the prior references disclose the method for manufacturing the semiconductor device as claimed in claim 5, wherein an upper surface of the second nitride semiconductor layer is a Ga-polar surface.
However, Makabe discloses the barrier layer (112) is a Ga-polar surface (paragraph 49).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Makabe such that the upper surface of the second nitride semiconductor layer is an Ga-polar surface. Doing so would enable superior electron confinement and enable high density two-dimensional electron gas (2DEG).
Response to Arguments
Applicant’s arguments, see pages 5-9, filed April 27, 2026, with respect to the rejection(s) of claims 1-2 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Makabe (US 20230036388 A1) and Sugawara et al. (US 20210257219 A1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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