Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Goup I (claims 1-6) in the reply filed on 12/24/2025 is acknowledged. Claim 7 has been withdrawn.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida (US 20190165130 A1).
Regarding claim 1, Yoshida discloses a method for manufacturing a semiconductor device, comprising: forming a first insulating layer (21) on a first nitride semiconductor layer (14) having a first principal surface (Fig. 3C);
forming, on the first insulating layer, a mask (22) including a first mask opening (22a) through which a portion of the first insulating layer is exposed (Fig. 3C);
forming a first opening (21a) in the first insulating layer through the first mask opening, to expose a portion of the first nitride semiconductor layer (Fig. 3A);
forming a second nitride semiconductor layer (15) on the first nitride semiconductor layer inside the first opening, through the first mask opening (Fig. 4B);
forming a first electrode (15) on the second nitride semiconductor layer, so as to cover a boundary line between the second nitride semiconductor layer and the first insulating layer, through the first mask opening (Fig. 4B);
and removing the mask after the forming the first electrode (Fig. 4C, HF acid is used to remove the mask, paragraph 30).
Regarding claim 2, Yoshida discloses the method for manufacturing the semiconductor device as claimed in claim 1, wherein the mask includes a second mask opening (22b) through which another portion of the first insulating layer is exposed (21b, Fig 3A-3C), the method further comprising:
forming a second opening in the first insulating layer (21b) through the second mask opening (22b), to expose another portion of the first nitride semiconductor layer, simultaneously as the forming of the first opening (Fig. 3A-C);
forming a third nitride semiconductor layer (16) on the first nitride semiconductor layer inside the second opening through the second mask opening (Fig. 4B), simultaneously as the forming the second nitride semiconductor layer; and
forming a second electrode (32) on the third nitride semiconductor layer (16) through the second mask opening, so as to cover a boundary line between the third nitride semiconductor layer and the first insulating layer, simultaneously as the forming of the first electrode (Fig. 4A-4C).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3, 5 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Matsuda (US 20180197978 A1).
Regarding claim 3, Yoshida does not disclose the method for manufacturing the semiconductor device as claimed in claim 1, further comprising, after the forming the first electrode, forming a second insulating layer on the first insulating layer, so as to cover the first electrode; and forming a gate electrode on the second insulating layer.
However, Matsuda discloses the method for manufacturing the semiconductor device as claimed in claim 1, further comprising, after the forming the first electrode (20), forming a second insulating layer (32A) on the first insulating layer (30), so as to cover the first electrode (22); and forming a gate electrode (24A) on the second insulating layer (Fig. 8B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Matsuda to have a second insulating layer on the first insulating layer covering the electrode of a high electron mobility transistor. Doing so would suppress gate leakage current, and passivate the surface states and control the electric field distribution.
Regarding claim 5, Yoshida discloses the method for manufacturing the semiconductor device as claimed in claim 3, further comprising: forming a third opening (21c) in the second insulating layer and the first insulating layer (21), the forming the gate electrode (33), wherein the gate electrode is formed to make contact with the first nitride semiconductor layer (14) through the third opening (Fig. 5B).
Yoshida does not disclose the second insulating layer.
Matsuda discloses a second insulating layer (32A)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Yoshida in view of Matsuda to have a second insulating layer on the first insulating layer of a high electron mobility transistor. Doing so would suppress gate leakage current and enhance breakdown voltage.
Claims 4, 6 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida in view of Matsuda (US 20180197978 A1) as applied to claim 3 and 5 above, in further view of Makabe (US 20190027577 A1).
Regarding claim 4, none of the prior references disclose the method for manufacturing the semiconductor device as claimed in claim 3, wherein an upper surface of the second nitride semiconductor layer is an N-polar surface.
However, Makabe discloses the channel layer (13) has an N-polar surface (paragraph 40).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Makabe such that the upper surface of the second nitride semiconductor layer is an N-polar surface. Doing so would enable superior electron confinement and enable high density two-dimensional electron gas (2DEG).
Regarding claim 6, none of the prior references disclose the method for manufacturing the semiconductor device as claimed in claim 5, wherein an upper surface of the second nitride semiconductor layer is a Ga-polar surface.
However, Makabe discloses the barrier layer (12) is a Ga-polar surface.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above with Makabe such that the upper surface of the second nitride semiconductor layer is an Ga-polar surface. Doing so would enable superior electron confinement and enable high density two-dimensional electron gas (2DEG).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817