Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2-6, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2) and Choi et al (US 20120051113 A1).
Regarding claim 1, Lee et al. disclose a semiconductor package comprising: a first memory device (10) arranged on the package substrate (300) and including first (100) and second semiconductor chips (200) stacked in a vertical direction (paragraph 40, Fig. 18); and wherein the first semiconductor chip comprises: a first cell structure (104a, 104b) having a memory cell for storing data (Fig. 1, paragraph 40); a first peripheral circuit structure (108 PR1) that communicates a signal provided from a source located outside the package substrate (Fig. 15); a first bonding pad (110a, Fig. 1); a first input/output pad (216) vertically overlapping the first peripheral circuit structure (108) and electrically connected to the first pad of the package substrate (300) through the first chip connection member (308-1) and wherein the second semiconductor chip comprises: a second cell structure having memory cells for storing data (204a, 204b); and a second bonding pad (210a) connected to the first bonding pad (110a) (paragraph 49, Fig. 1).
Lee et al. do not disclose a package substrate including a first pad, a package substrate including a first pad, a first chip connection member electrically connecting the first semiconductor chip to the package substrate, a first input/output pad vertically overlapping the first peripheral circuit structure and electrically connected to the first pad of the package substrate through the first chip connection member, a part of the first peripheral circuit structure protrudes from a first sidewall of the second semiconductor chip in a first direction so as not to overlap the second semiconductor chip.
However, Chen et al. disclose a package substrate (210) including a first pad (220), a first chip connection member (Wx) electrically connecting the first semiconductor chip (102) to the package substrate (210).
None of the prior references disclose wherein a part of the first peripheral circuit structure protrudes from a first sidewall of the second semiconductor chip in a first direction so as not to overlap the second semiconductor chip.
However, Choi et al. disclose part of the first peripheral circuit structure (214b) protrudes from a first sidewall of the semiconductor chip (210) in a first direction so as not to overlap the second semiconductor chip (220) (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. and Chen et al. with Choi et al. such that the peripheral circuit structure protrudes from a sidewall of the first semiconductor chip in the first direction as to not overlap the second semiconductor chip. Doing so ensures that the peripheral circuits do not interfere with the stacking or functionality of the second chip.
Regarding claim 2, Lee et al. disclose a peripheral circuit (108) of the first peripheral circuit structure is electrically connected to a circuit of the first cell structure (104a) and a circuit of the second cell structure (104b) (paragraph 42, Fig. 1).
Regarding claim 3, Lee et al., Chen et al., and Choi et al. are discussed above. Lee et al. further disclose the first semiconductor chip (100e) is disposed between the package substrate (300) and the second semiconductor chip (200e) (Fig. 20).
However, neither Lee et al. nor Choi et al. disclose the first chip connection member includes a conductive wire extending between the first input/output pad and the first pad of the package substrate.
However, Chen et al. disclose the first chip connection member (Wx) includes a conductive wire extending between the first input/output pad (BP1) and the first pad (220) of the package substrate (210) (Fig. 6B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. and Choi et al. with Chen et al. such that the pad of the semiconductor chip is electrically connected to the pad of the package substrate. Doing so is essential for signal transmission, power distribution, and heat dissipation.
Regarding claim 4, Lee et al. disclose the first bonding pad (110a) is directly coupled to the second bonding pad (210a) (paragraph 49, Fig. 1).
Regarding claim 5, Lee et al. disclose a connection bump (224) disposed between the first bonding pad (110a) and the second bonding pad (210a) (paragraph 98, Fig 8).
Regarding claim 6, Lee et al. disclose the semiconductor package of claim 1, wherein a part of the first peripheral circuit structure (108, Fig. 16) protrudes from a second sidewall of the second semiconductor chip (45-1, Fig. 20) in a second direction so as not to vertically overlap the second semiconductor chip, where the second direction is different from the first direction (Fig. 20).
Regarding claim 11, Lee et al. disclose a molding layer (306) covering the first semiconductor chip (100f) and the second semiconductor chip (200f) on the package substrate (300), wherein a part of the molding layer extends along the first sidewall of the second semiconductor chip (Fig. 19).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2) and Choi et al (US 20120051113 A1) as applied to claim 1 above, in further view of Youn et al (US 8659136 B2).
Regarding claim 7, Lee, Chen, and Choi are discussed above. Lee et al. further disclose the semiconductor package of claim 1, further comprising a second memory device (55-2, Fig. 19) arranged on the first memory device (55-1) and including third (100f) and fourth semiconductor chips (200f) stacked vertically (Fig. 19); and wherein the third semiconductor chip comprises: a third cell structure having a memory cell for storing data (104a, 104b, Fig. 13); a second peripheral circuit structure (108 PR1, structure is the same as stacked chips in Fig. 20) that communicates a signal provided from a source located outside the semiconductor package; a third bonding pad (110a); and wherein the fourth semiconductor chip comprises: a fourth cell structure having a memory cell for storing data (204a, 204b); and a fourth bonding pad (210a) connected to the third bonding pad (110a).
Lee et al. do not disclose a second chip connection member electrically connecting the third semiconductor chip to a second pad of the package substrate,
However, Chen et al. disclose a chip connecting member (Wx) electrically connecting the chip package (SDU’ (Xn)) to a second pad (220, outer left pad, Fig. 6C) of the package substrate (210)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. with Chen et al. such that the third semiconductor chip is electrically connected by a second chip connection to a second pad of the package substrate. Doing so would achieve a smaller form factor, improve performance, and manage heat.
Lee et al. disclose a second input/output pad (216e2) vertically overlapping the second peripheral circuit structure (108, Fig. 20).
However, Lee does not disclose a second input/output pad electrically connected to the second pad of the package substrate through the second chip connection member.
On the other hand, Chen et al. disclose a second input/output pad (BP1) electrically connected to the second pad (220) of the package substrate (210) through the second chip connection member (Wx, Fig. 6C).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. with Chen et al. such that the input/output pad of the second chip vertically overlaps the peripheral circuit structure, and is electrically connected to the pad of the package substrate. Doing so would achieve a smaller form factor, improve performance, and manage heat.
Neither Lee et al., Choi et al, nor Chen et al. disclose wherein a length of the third semiconductor chip in the first direction is greater than a length of the fourth semiconductor chip in the first direction.
However, Youn et al. disclose a length of the first type semiconductor chip (9100A) is longer than a length of a second semiconductor chip (9200A) in the first direction (Fig. 11A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al., Chen et al., and Choi et al. with Youn et al. such that the length of the third semiconductor chip is greater than the length of the fourth semiconductor chip in the first direction. Doing so would facilitate electrical connectivity, maximize manufacturing yield, optimize thermal management, and enable heterogeneous integration.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2) and Choi et al (US 20120051113 A1) as applied to claim 1 above, in further view of Yang (US 20230369306 A1).
Regarding claim 8, Lee, Chen, and Choi are discussed above. Lee et al. further disclose input/output pad (110b, 110c, Fig. 1).
Neither Lee et al., Choi et al., nor Chen et al. disclose the second semiconductor chip is disposed between the package substrate and the first semiconductor chip, and the first chip connection member includes a conductive pillar extending between the first input/output pad and the first pad of the package substrate.
However, Yang discloses the second semiconductor chip (20) is disposed between the package substrate (10) and the first semiconductor chip (30), and the first chip connection member includes a conductive pillar (32) extending between the first input/output pad and the first pad of the package substrate (33) (Fig. 1B).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al., Chen et al., and Choi et al. with Yang such that the conductive pillar extends between the first input/output pad and the first pad of the package substrate. Doing so would enable a high-performance, rigid, and reliable vertical electrical connection.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2), Choi et al (US 20120051113 A1), and Yang (US 20230369306 A1) as applied to claim 8 above, in further view of Kim (US 11810865 B2).
Regarding claim 9, Lee, Chen, Choi, and Yang are discussed above. None of these references disclose an underfill material layer arranged between the first semiconductor chip and the package substrate and between the second semiconductor chip and the package substrate.
However, Kim discloses an underfill resin (124) between the chip structure (CS) and the package substrate (110) (paragraph 44, Fig. 6).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references with Kim such that the underfill material layer is arranged between the semiconductor chip and the package substrate. Doing so would enhance reliability by protecting delicate solder joints from thermo-mechanical stress.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2), Choi et al (US 20120051113 A1), and Yang (US 20230369306 A1) as applied to claim 8 above, in further view of Choi (US 11515290 B2)
Regarding claim 10, Lee, Chen, Choi, and Yang are discussed above. None of these references disclose the semiconductor package of claim 8, further comprising another semiconductor chip connected to the first semiconductor chip and spaced apart from the second semiconductor chip in the first direction with the conductive pillar therebetween, wherein the peripheral circuit of the first peripheral circuit structure is electrically connected to a circuit of a cell structure of the other semiconductor chip.
However, Choi et al. disclose wherein the peripheral circuit of the first peripheral circuit structure (114) is electrically connected (by via 150) to a circuit of a cell structure (124) of the other semiconductor chip (120).
Choi (‘290) discloses semiconductor chip connected to the first semiconductor chip (200, lefthand side, Fig. 2) and spaced apart from the second semiconductor chip (200, righthand side, Fig. 2) in the first direction with the conductive pillar (280) therebetween (Fig. 2)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references with Choi et al. and Choi (‘290) such that the conductive pillars are between two semiconductors and the peripheral circuit is electrically connected to a circuit of a cell structure of the other semiconductor chip. Doing so would enable high-density vertical interconnection and overcome the physical and economic limitations of traditional, single-die (monolithic) chip manufacturing.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2), and Choi et al (US 20120051113 A1) as applied to claim 1 above, in further view of Jung et al. (US 20130093102 A1).
Regarding claim 12, Lee, Chen, and Choi are discussed above. None of these references disclose wherein a thickness of the second semiconductor chip is between about 10 micrometers and about 100 micrometers.
However, Jung et al. disclose a thickness of a semiconductor chip can be formed with a thickness of 30, 40, or 50 micrometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the prior references with Jung et al. such that the thickness of the second semiconductor chip is between 10 micrometers and about 100 micrometers. Doing so would increase performance, reduce power consumption, and decrease overall package size.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al (US 20220130811 A1) in view of Chen et al. (US 11114413 B2), Jung et al (US 20130093102 A1), and Choi et al (US 20120051113 A1)
Regarding claim 13, Lee et al. disclose a semiconductor package comprising: a memory device (100, 200, paragraph 40) disposed on the package substrate (300, Fig. 20), the memory device including a first semiconductor chip (100e) disposed on the package substrate (300) and a second semiconductor chip (200e) disposed on the first semiconductor chip; and wherein the first semiconductor chip comprises: a first cell structure (104a) having a memory cell for storing data (Fig. 1); a first peripheral circuit structure (108 PR1, Fig. 13) that communicates a signal provided from a source located outside the semiconductor package; a first interconnect structure (308-1) including a first input/output pad (216e2) electrically connected to the first pad of the package substrate through the conductive wire and a first bonding pad (Fig. 20); a first input/output pad (216) vertically overlapping the first peripheral circuit structure (108); a second interconnect structure (308-3) including a second bonding pad directly coupled to the first bonding pad (Fig. 20), wherein the second semiconductor chip comprises: a second cell structure (204a) having a memory cell for storing data.
Lee et al. do not disclose a package substrate including a first pad; a conductive wire electrically connecting the first semiconductor chip to the package substrate; wherein a thickness of the second semiconductor chip is smaller than a thickness of the first semiconductor chip; and wherein a part of the first peripheral circuit structure protrudes from a sidewall of the second semiconductor chip in a first direction so as not to vertically overlap the second semiconductor chip, and
However, Chen et al. disclose a package substrate (210) including a first pad (220) (Fig. 6A); a conductive wire (Wx) electrically connecting the first semiconductor chip (102) to the package substrate (210) (Fig. 6A).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. with Chen et al. such that the package substrate has pads and a conductive wire electrically connecting the first semiconductor chip to the package substrate. Doing so improves device performance, reduces footprint size, and manages high-density routing.
Neither Lee nor Choi disclose wherein a thickness of the second semiconductor chip is smaller than a thickness of the first semiconductor chip.
However, Jung et al. disclose a thickness of a semiconductor chip can be formed with a thickness of 30, 40, or 50 micrometers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee and Chen with Jung et al. such that the thickness of the second semiconductor chip is smaller than a thickness of the first semiconductor chip. Doing so would increase performance, reduce power consumption, and decrease overall package size.
Choi et al. (‘113) disclose part of the first peripheral circuit structure (214b) protrudes from a first sidewall of the semiconductor chip (210) in a first direction so as not to overlap the second semiconductor chip (220) (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. and Chen et al. with Choi et al. such that the peripheral circuit structure protrudes from a sidewall of the first semiconductor chip in the first direction as to not overlap the second semiconductor chip. Doing so ensures that the peripheral circuits do not interfere with the stacking or functionality of the second chip.
Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20220130811 A1) in view of Chen et al. (US 11114413 B2), Jung et al (US 20130093102 A1), and Choi et al (US 20120051113 A1) as applied to claim 13 above, in further view of Youn et al. (US 8659136 B2).
Regarding claim 14, Lee, Chen, Jung, and Choi (‘113) are discussed above. None of these references disclose a second sidewall of the second semiconductor chip is vertically aligned with one sidewall of the first semiconductor chip.
However, Youn et al. disclose a second sidewall (left sidewall of semiconductor chip 3200, Fig. 4) is of the second semiconductor chip (3200) is vertically aligned with one sidewall of the first semiconductor chip (3100, Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee, Chen, Jung, and Choi (‘113) with Youn et al. such that the second sidewall of the second semiconductor chip is vertically aligned with one sidewall of the first semiconductor chip. Doing so would optimize interconnect density, signal integrity, and package miniaturization.
Regarding claim 15, Lee, Chen, Jung, and Choi (‘113) are discussed above. None of these references disclose the first semiconductor chip protrudes from a second sidewall of the second semiconductor chip in a second direction that is different from the first lateral direction.
However, Youn et al. disclose the first semiconductor chip (3100) protrudes from a second sidewall of the second semiconductor chip (3200) in a second direction that is different from the first lateral direction (Fig. 4).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee, Chen, Jung, and Choi (‘113) with Youn et al. such that the first semiconductor chip protrudes from a second sidewall of the second semiconductor chip in a second direction that is different from the first lateral direction. Doing so would optimize interconnect density, signal integrity, and package miniaturization.
Conclusion
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817