DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on August 02, 2023 was filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The examiner suggests the following title “CRYSTALLIZED METAL CHALCOGENIDE THIN FILM HAVING A LAYERED STRUCTURE, THIN-FILM TRANSISTOR INCLUDING THE SAME, AND METHOD OF MANUFACTURING THE THIN-FILM TRANSISTOR.”
Claim Objections
Claim 1-23 are objected to because of the following informalities:
claim 1, lines 12-15,
“wherein the semiconductor layer,
comprises a crystallized metal chalcogenide comprising a transition metal and a chalcogen element, and
has a layered structure”
should recite
--wherein the semiconductor layer comprises:
a crystallized metal chalcogenide comprising a transition metal and a chalcogen element; and
has a layered structure.--
Claims 2-23 because of their dependency on claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1, 12, 15, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon).
Regarding claim 1, Kim_146 discloses a display device (fig 3) comprising:
a substrate (101);
a thin-film transistor (Tdr, “driving circuit includes … driving TFT Tdr” [0046] ln 02) on the substrate; and
a light-emitting diode (“light emitting diode E” [0042] ln 04, within emission area EA) electrically connected (using OLED first anode 210) to the thin-film transistor (using drain electrode 109b), wherein the thin-film transistor comprises:
a semiconductor layer (103) in which a source region (103b), a drain region (103c), and a channel region (103a) are defined;
a gate electrode (107) insulated (due to insulation layer 105) from the semiconductor layer (103) and overlapping the semiconductor layer (“gate insulating layer 105 disposed on semiconductor layer 103” [0081] ln 01);
a source electrode (109a) electrically connected to the source region (103b); and
a drain electrode (109b) electrically connected to the drain region (103c),
Kim_146 does not disclose that the semiconductor layer (103) comprises
a crystallized metal chalcogenide comprising a transition metal and a chalcogen element, and
has a layered structure.
Yoon teaches methods related to the manufacturing of chalcogenide thin-film semiconductor materials, and is therefore analogous art. Specifically, Yoon teaches (fig 2)
wherein the semiconductor layer (204,206, examiner interprets that CdTe is a compound semiconductor),
comprises a crystallized (“CdTe film is fully crystallized” [0063] ln 07) metal chalcogenide (fig. 2 layer 206, “206 can include p-cadmium telluride (p-CdTe)” [0035] ln 04-05, examiner interprets that CdTe is a II-VI metal chalcogenide) comprising a transition metal (examiner interprets that Cd is a transition metal) and a chalcogen element (examiner interprets that Te is a chalcogen), and
has a layered structure (206 second cadmium layer with thickness T2, 204 first cadmium layer with thickness T1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a structure containing a thin-film transistor and a light-emitting diode as disclosed by Kim_146, and to include a semiconductor layer consisting of a crystallized metal chalcogenide and having a layered structure as disclosed by Yoon because CdTe has a high electron mobility (over 1000 cm2/V S) which enhances carrier transport in TFT transistors, it can also function in both enhancement and depletion modes providing design flexibility, and has a low cost of manufacturing and can be deposited using conventional techniques such as thermal evaporation allowing for large scale production. In addition, Yoon mentions that “chalcogenide thin-film semiconductors can be used for flexible optoelectronic and photovoltaic devices” [0025] ln 01-02, which are areas where thin-film transistors are widely used.
Regarding claim 12, Kim_146 in view of Yoon discloses a method of manufacturing the display device of claim 1. Kim_146 further discloses the method comprising:
forming the thin-film transistor (fig 3 (Tdr), also “TFT Tdr” [0046] ln 02) on the substrate (101); and
forming the light-emitting diode (fig 3 (E), also “LED E” [0042] ln 04) electrically connected (using first anode 210) to the thin-film transistor (using drain electrode 109b), wherein the forming of the thin-film transistor comprises:
forming the semiconductor layer (103) in which the source region (103b), the drain region (103c), and the channel region (103a) are defined;
forming the gate electrode (107) insulated (using insulation 105) from the semiconductor layer (103) and overlapping the semiconductor layer (“gate insulating layer 105 disposed on semiconductor layer 103” [0081] ln 01);
forming the source electrode (109a) electrically connected to the source region (103b); and
forming the drain electrode (109b) electrically connected to the drain region (103c), …
Yoon further discloses (fig 2) wherein the forming of the semiconductor layer (204, 206) comprises:
depositing a semiconductor precursor comprising a metal chalcogenide (“CdTe” [0063] ln 07), which comprises the transition metal (Cd) and the chalcogen element (Te); and crystallizing the semiconductor precursor (CdTe film is fully crystallized” [0063] ln 07) to have the layered structure (204,206).
Regarding claim 15, Kim_146 in view of Yoon discloses the method of claim 12. Yoon further discloses:
wherein the depositing of the semiconductor precursor is performed through a thermal deposition process (“CdTe films deposited on a 200mm CdS coated Si/SiO2 substrates at a substrate temperature of 200, 300, 450, 540 deg C” [0013, ln 02-04, examiner interprets that CdTe is II-VI compound semiconductor, examiner interprets that CdTe is commonly used as the direct precursor for depositing CdTe thin films, and examiner interprets that raising the substrate temperature is an essential technique in thermal deposition to enhance thin film quality).
Regarding claim 20, Kim_146 in view of Yoon discloses the method of claim 12. Yoon further discloses
wherein the crystallizing of the semiconductor precursor is performed through a heat treatment process (high-temperature (>450 deg C) deposition and post annealing processes radically improves the properties of …. CdTe thin-films through grain recrystallization” [0026] ln 03-05, examiner interprets that CdTe is II-VI compound semiconductor and that CdTe is commonly used as the direct precursor for depositing CdTe thin films).
Claims 2-3, and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon), as applied above, and further in view of Zhang et al. (US 2022/0100042 A1; hereinafter referred to as Zhang).
Regarding claim 2, Kim_146 in view of Yoon discloses the display device of claim 1. Yoon further discloses
…. and the chalcogen element comprises at least one of sulfur (S), selenium (Se), or tellurium (Te) (fig. 2 layer 206, “206 can include p-cadmium telluride (p-CdTe)” [0035] ln 04-05).
Kim_146 in view of Yoon does not disclose
wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re), ....
Zhang teaches a display device including thin film transistors, and is therefore analogous art, specifically Zhang teaches (claim 19)
wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re), …. (“photosensitive device is thin film transistor, a gate of photosensitive device is a photosensitive layer, photosensitive layer comprises a photoresistor, the photoresistor comprises one of … bismuth sulfide”, claim 19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon, and to include a bismuth sulfide (Bi2S3) layer as taught by Zhang because Bismuth sulfide has both tunable semiconducting properties via doping and is a non-toxic alternative to conventional lead or cadmium-based materials leading it to be an environmentally friendly option for thin film transistors.
Regarding claim 3, Kim_146 in view of Yoon further in view of Zhang discloses the display device of claim 2. Zhang further discloses
wherein the semiconductor layer comprises bismuth sulfide (Bi2S3) (“photosensitive device is thin film transistor, a gate of photosensitive device is a photosensitive layer, photosensitive layer comprises a photoresistor, the photoresistor comprises one of … bismuth sulfide”, claim 19).
Regarding claim 13. Kim_146 in view of Yoon disclose the method of claim 12. Yoon further discloses (fig 2, 206)
wherein the metal chalcogenide (CdTe, [0035] ln 04-05) is a compound of a transition metal (Cd) and a chalcogen element (Te),
… and the chalcogen element comprises at least one of sulfur (S), selenium (Se), or tellurium (Te) (Te).
Kim_146 in view of Yoon does not disclose
and wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re),
Zhang teaches a display device including thin film transistors, and is therefore analogous art, specifically Zhang teaches (claim 19)
and wherein the transition metal comprises at least one of bismuth (Bi), tin (Sn), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), hafnium (Hf), titanium (Ti), or rhenium (Re), … (“photosensitive device is thin film transistor, a gate of photosensitive device is a photosensitive layer, photosensitive layer comprises a photoresistor, the photoresistor comprises one of … bismuth sulfide”, claim 19).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon, and to include a bismuth sulfide (Bi2S3) layer as taught by Zhang because Bismuth sulfide has both tunable semiconducting properties via doping and is a non-toxic alternative to conventional lead or cadmium-based materials leading it to be an environmentally friendly option for thin film transistors.
Regarding claim 14. Kim_146 in view of Yoon further in view of Zhang discloses the method of claim 13. Zhang further discloses
wherein the semiconductor layer having the layered structure comprises bismuth sulfide (Bi2S3) (photosensitive device is thin film transistor, a gate of photosensitive device is a photosensitive layer, photosensitive layer comprises a photoresistor, the photoresistor comprises one of … bismuth sulfide”, claim 19).
Claims 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Kim et al. (US 2016/0049536 A1; hereinafter referred to as Kim_536).
Regarding claim 4. Kim_146 in view of Yoon disclose the display device of claim 1. Kim_146 in view of Yoon does not discloses
wherein the layered structure of the semiconductor layer has a structure in which a first sub-layer and a second sub-layer are alternately stacked.
Kim_536 teaches an image sensor including a metal chalcogenide, and is therefore analogous art, specifically Kim_536 teaches (fig. 4)
wherein the layered structure (31,32) of the semiconductor layer has a structure in which a first sub-layer (31) and a second sub-layer (32) are alternately stacked (31, 32, 31, 32, etc.).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon, and to include an alternately stacked structure as taught by Kim_536 because alternately stacking layers produces a superlattice-like structure consisting of discrete energy levels due to its two-dimensional layered nature and thus offers vastly superior sensitivity in optoelectronic devices when compared to bulk materials. Kim_536 alludes to this fact by disclosing “layer 31 and … layer 32 may be repeatedly stacked … to perform sufficient light absorption” [0058] ln 15-17.
Claims 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Talapin (US 2012/0104325 A1; hereinafter referred to as Talapin).
Regarding claim 6. (Yoon teaches crystallized CdTe) Kim_146 in view of Yoon discloses The display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein, in the crystallized metal chalcogenide, a main peak obtained by an X-ray diffraction (XRD) spectrum is in a region where a diffraction angle 2θ is about 15° to about 16°, and a sub-peak obtained by the X-ray diffraction (XRD) spectrum is in a region where the diffraction angle 2θ is about 25° to about 26°.
Talapin teaches a metal chalcogenides (BiSbTe among others) including x-ray diffraction (XRD) analysis, and use in thin film transistor (abstract) and is therefore analogous art, specifically Talapin teaches (fig. 17, see examiner annotated figure below)
wherein, in the crystallized metal chalcogenide (see claim 01), a main peak obtained by an X-ray diffraction (XRD) spectrum is in a region where a diffraction angle 2θ is about 15° to about 16° (Talapin teaches a main peak of Bi(x)Sb(2-x)Te(3) between 2theta of 15-20 degrees, examiner interprets that variation in ranges is also dependent on sample processing conditions during manufacturing and XRD testing), and a sub-peak obtained by the X-ray diffraction (XRD) spectrum is in a region where the diffraction angle 2θ is about 25° to about 26° (Talapin teaches a sub peak of Bi(x)Sb(2-x)Te(3) between 2theta of 25-30 degrees, examiner interprets that variation in ranges is also dependent on sample processing conditions during manufacturing and XRD testing).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a metal chalcogenide such as BiSbTe with corresponding XRD analysis because BiSbTe offers band structure tuning via alloying and therefore allows for optimization of the bandgap, which reduced the detrimental impact of thermally generated minority carriers. In addition, BiSbTe offers flexibility in deposition methods as in can be deposited using sputtering, molecular beam epitaxy, and laser deposition.
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Claim 7, 10, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Chung et al. (US 2016/0035568 A1; hereinafter referred to as Chung).
Regarding claim 7, Kim_146 in view of Yoon discloses the display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm.
Chung teaches a transition metal chalcogenide thin film for use in TFTs, and is therefore analogous art, specifically Chung teaches
wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm (“thickness of transition metal film (for example, a molybdenum film) may range from 1nm to 110nm” [0043] ln 13-15, examiner interprets that claimed range of 10-50nm is encompassed by prior art range of 1-110nm, and examiner interprets that transition metal-based films are widely considered and used as semiconductors).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a 1-110nm transition metal film as disclosed by Chung because an ultra-thin thin transition metal film is used in thin-film transistors (TFTs) to improve mechanical flexibility for flexible electronics applications, and to enable transparency for display applications.
Regarding claim 10, Kim_146 in view of Yoon discloses the display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein the semiconductor layer has a band gap of about 1.4 eV to about 1.6 eV.
Chung teaches a transition metal chalcogenide thin film for use in TFTs, and is therefore analogous art, specifically Chung teaches
wherein the semiconductor layer has a band gap of about 1.4 eV to about 1.6 eV (“bulk Molybdenum disulfide has a nonlinear bandgap level of 1.2 eV and a monolayer Molybdenum disulfide may have a maximum bandgap of 1.8 eV” [0004] ln 10-11, examiner interprets that claim bandgap range of 1.4-1.6 eV is encompasses by prior art established range in bandgap of 1.2-1.8 eV)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a transition metal chalcogenide such as Molybdenum disulfide as taught by Chung because Molybdenum disulfide is used in thin-film transistors (TFTs) primarily for its exceptional 2D semiconductor properties, including high carrier mobility, a bandgap that can be tailored, superior mechanical flexibility, and ability to provide high on/off current ratios, which enable efficient, high-speed, flexible electronic devices such as displays and sensors. Chung alludes to this by disclosing “molybdenum disulfide has excellent luminous efficiency, high carrier mobility and high on/off ratio” [0004] ln 08-10.
Regarding claim 19, Kim_146 in view of Yoon discloses the method of claim 12. Kim_146 in view of Yoon does not disclose
wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm.
Chung teaches a transition metal chalcogenide thin film for use in TFTs, and is therefore analogous art, specifically Chung teaches
wherein the semiconductor layer has a thickness of about 10 nm to about 50 nm (“thickness of transition metal film (for example, a molybdenum film) may range from 1nm to 110nm” [0043] ln 13-15, examiner interprets that claimed range of 10-50nm is encompassed by prior art range of 1-110nm, and examiner interprets that transition metal-based films are widely considered and used as semiconductors).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a 1-110nm transition metal film as disclosed by Chung because an ultra-thin thin transition metal film is used in thin-film transistors (TFTs) to improve mechanical flexibility for flexible electronics applications, and to enable transparency for display applications.
Claim 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Liang et al. (US 2014/0264320 A1; hereinafter referred to as Liang).
Regarding claim 8, Kim_146 in view of Yoon discloses the display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein electron mobility of the thin-film transistor comprising the semiconductor layer has a value of about 10 cm2V-1s-1 to about 14 cm2V-1s-1.
Liang teaches a thin film transistor and a metal-based semiconductor layer, and is therefore analogous art, specifically Liang teaches
wherein electron mobility of the thin-film transistor comprising the semiconductor layer has a value of about 10 cm2V-1s-1 to about 14 cm2V-1s-1 (“Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications … Some of these materials exhibit high mobility (e.g. > 5 cm2V-1s-1)“ [0004] ln 01-14, examiner interprets that claimed limitation of 10 cm2V-1s-1 to about 14 cm2V-1s-1 is covered by > 5 cm2V-1s-1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to tailor the mobility to be greater than 5 cm2V-1s-1 as disclosed by Liang because high mobility in thin-film transistors (TFTs) is critical for enabling faster device response times and lower power consumption by allowing carriers (electrons or holes) to move rapidly and thus support higher on-currents for faster switching in large-area, high-resolution electronic or display (OLED/LCD) applications.
Regarding claim 9, Kim_146 in view of Yoon discloses the display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein an on-to-off current ratio of the thin-film transistor comprising the semiconductor layer has a value of about 104 to about 109.
Liang teaches a thin film transistor and a metal-based semiconductor layer, and is therefore analogous art, specifically Liang teaches
wherein an on-to-off current ratio of the thin-film transistor comprising the semiconductor layer has a value of about 104 to about 109 (Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications … Some of these materials exhibit … high on/off current ratios (e.g. > 106)” [0004] ln 01-15, examiner interprets that claimed limitation of on-to-off current ratio of about 104 to about 109 is covered by > 106).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to tailor the on-to-off current ratio to be greater than 106 as disclosed by Liang because a high on-to-off current ratio in thin-film transistors (TFTs) is crucial to ensure precise switching and low power consumption since a large ratio ensures that the thin-film transistor can charge quickly (high ON current)) and hold the charge without leakage (low OFF current), which are parameters that enable high-fidelity signal processing and pixel switching in displays.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Xu et al. (US 2020/0357635 A1; hereinafter referred to as Xu).
Regarding claim 11, Kim_146 in view of Yoon discloses the display device of claim 1. Kim_146 in view of Yoon does not disclose
wherein the semiconductor layer has a surface roughness of about 0.23 nm to about 0.25 nm.
Xu teaches a chalcogenide semiconductor for use in TFT transistors, and is therefore analogous art, specifically Xu teaches (fig. 8)
wherein the semiconductor layer has a surface roughness of about 0.23 nm to about 0.25 nm (Fig 8 shows an RMS roughness curve decreasing from an RMS roughness value of 2.554 nm at 40 PLD shots to an RMS roughness value of 0.178 nm at 100 PLD shots for the molybdenum sulfide sample, also see “for films having 40, 100 … shots, AFM surface morphologies of MoS2 was observed. An RMS roughness of 2.554, 0.178 … was observed for these MoS2 films” [0046] ln 01-06, examiner interprets that this RMS roughness curve in the range of 0.178-2.554nm encompasses the claimed roughness range of 0.23-0.25 nm, also examiner interprets the molybdenum sulfide MoS2 is a well-known semiconductor in addition to being a well-known metal chalcogenide).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a metal chalcogenide such as MoS2 because “two-dimensional MoS2 has … unique electrical properties that can be tuned by controlling a thickness of the film … for various applications such as thin film transistors” [0003] ln 01-06.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Park et al. (KR 2022/0120274 A; hereinafter referred to as Park).
Regarding claim 21, Kim_146 in view of Yoon discloses the method of claim 20. Kim_146 in view of Yoon does not disclose
wherein the heat treatment process comprises applying heat of about 100 °C to about 150 °C for about 30 minutes to about 1 hour.
Park teaches metal chalcogenide thin films for use in transistors, and is therefore analogous art, specifically Park teaches (claim 11 in attached translation and highlighted on page 2 before original)
wherein the heat treatment process comprises applying heat of about 100 °C to about 150 °C for about 30 minutes to about 1 hour (“The step of heat-treating the transition metal-chalcogen thin film, ... Heat treatment for a temperature range of 100 ° C to 500 ° C and 10 minutes to 3 hours under inert conditions”, claim 11 in attached translation).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to utilize a heat treatment as disclosed by Park because heat treatment of metal chalcogenide is used to enhance film quality, remove solvent residues, and reduce structural defects, which leads to increased charge carrier mobility, increased environmental stability of the film.
Claim 22-23 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 2023/0200146 A1; hereinafter referred to as Kim_146) in view of Yoon et al. (US 2020/0373414 A1; hereinafter referred to as Yoon) further in view of Liang et al. (US 2014/0264320 A1; hereinafter referred to as Liang).
Regarding claim 22, Kim_146 in view of Yoon discloses the method of claim 12. Yoon further discloses crystallizing of the semiconductor precursor (see claim 12). Kim_146 in view of Yoon does not disclose
wherein, through the crystallizing of the semiconductor precursor, electron mobility of the thin-film transistor has a value of about 10 cm2V-1s-1 to about 14 cm2V-1s-1.
Liang teaches a thin film transistor and a metal-based semiconductor layer, and is therefore analogous art, specifically Liang teaches
wherein, through the crystallizing of the semiconductor precursor (Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications. The metal-based semiconductor materials may be .. crystalline” [0004] ln 01-04), electron mobility of the thin-film transistor has a value of about 10 cm2V-1s-1 to about 14 cm2V-1s-1 (“Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications … Some of these materials exhibit high mobility (e.g. > 5 cm2V-1s-1)“ [0004] ln 01-14, examiner interprets that claimed limitation of 10 cm2V-1s-1 to about 14 cm2V-1s-1 is covered by > 5 cm2V-1s-1).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to tailor the mobility to be greater than 5 cm2V-1s-1 as disclosed by Liang because high mobility in thin-film transistors (TFTs) is critical for enabling faster device response times and lower power consumption by allowing carriers (electrons or holes) to move rapidly and thus support higher on-currents for faster switching in large-area, high-resolution electronic or display (OLED/LCD) applications.
Regarding claim 23. Kim_146 in view of Yoon discloses the method of claim 12, wherein. Yoon further discloses crystallizing of the semiconductor precursor (see claim 12). Kim_146 in view of Yoon does not disclose
wherein, through the crystallizing of the semiconductor precursor, an on-to-off current ratio of the thin-film transistor has a value of about 104 to about 109.
Liang teaches a thin film transistor and a metal-based semiconductor layer, and is therefore analogous art, specifically Liang teaches
wherein, through the crystallizing of the semiconductor precursor (Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications. The metal-based semiconductor materials may be .. crystalline” [0004] ln 01-04), an on-to-off current ratio of the thin-film transistor has a value of about 104 to about 109 (Metal-based semiconductor materials (e.g. … metal chalcogenides) are candidates for replacing a-Si in display applications … Some of these materials exhibit … high on/off current ratios (e.g. > 106)” [0004] ln 01-15, examiner interprets that claimed limitation of on-to-off current ratio of about 104 to about 109 is covered by > 106).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ a display device with a thin film transistor including of a metal chalcogenide layer as disclosed by Kim_146 in view of Yoon and to tailor the on-to-off current ratio to be greater than 106 as disclosed by Liang because a high on-to-off current ratio in thin-film transistors (TFTs) is crucial to ensure precise switching and low power consumption since a large ratio ensures that the thin-film transistor can charge quickly (high ON current)) and hold the charge without leakage (low OFF current), which are parameters that enable high-fidelity signal processing and pixel switching in displays.
Allowable Subject Matter
Claims 5 and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 5, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a display device:
wherein the transition metal of the crystallized metal chalcogenide is arranged in the first sub-layer,
and the chalcogen element of the crystallized metal chalcogenide is arranged in the second sub-layer.
Regarding claim 16, the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, a method of manufacturing a display device:
wherein the thermal deposition process comprises:
providing a thermal deposition source and the substrate into a vacuum chamber;
heating the thermal deposition source; and evaporating a material included in the thermal deposition source, in an atomic or molecular state, and
depositing the material on a surface of the substrate to coat the surface of the substrate with a thin film.
Claim 17-18 depends from claim 16, and therefore, are allowable for the same reason as claim 16.
Conclusion
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/C.O.R./
Examiner, Art Unit 2812
03 Feb. 2026
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812