DETAILED ACTION
This office action is in response to the remarks filed on 05/06/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 23 is objected to because of the following informalities: Claim 23 recites “a state… provide a current to a sink device ” this should be “the state… provide the current to the sink device”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 23 recites the limitation "the state of the voltage" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4, 9-11, 18-19, 21and 23 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motoki US 2016/011880.
Regarding Claim 1, Motoki teaches (Figures 2-5) An apparatus (Fig. 2) comprising: a transistor (sw1) coupled between a voltage bus (Vbus) and a power terminal (Vout node), the power terminal coupled to the output of the power supply (102); and a controller (110, 104 and 140) having first and second outputs (input terminals and output terminals of the controller), the first output coupled to the input of the power supply (with 104) , the second output coupled to a control terminal of the transistor (with 110), wherein the controller is configurable to, responsive to a state of the voltage bus (Vbus) indicating that the voltage bus does not provide a current to a sink device (USB load, this happens between φ1- φ2 at startup and between times φ4 and φ6 at the 0V output state), turn off the transistor (See fig. 4, s3 signal). (For Example: Par. 43-56 and 60-68)
Regarding Claim 4, Motoki teaches (Figures 2-5) further comprising a capacitor coupled to the power terminal (c1 or c2).
Regarding Claim 9, Motoki teaches (Figures 2-5) wherein the transistor is an n-channel field effect transistor (at sw1, par. 45).
Regarding Claim 10, Motoki teaches (Figures 2-5) wherein the controller (104, 110 and 140) includes a communication input (com) , and the controller is configurable to negotiate, over the communication input, a contract with the sink device or another device (par. 50, with a connected device); and responsive to negotiating the contract, turn on the transistor and cause the power supply to supply power to the power terminal (see fig. 4, φ3). (For Example: Par. 43-56 and 60-68)
Regarding Claim 11, Motoki teaches (Figures 2-5) a system (Fig. 2) comprising: a power supply (102) having an input and an output (input and output terminals of 102); a transistor (sw1) coupled between a voltage bus (Vbus node) and a power terminal (vout bus), the power terminal coupled to the output of the power supply(102); a connector (108) coupled to the voltage bus: a capacitor (C1) coupled to the power terminal; a controller (104, 140 and 110) having an input coupled to the connector (with 113) and having first and second outputs (with OUT and 104), the first output coupled to the input of the power supply (with 104), the second output coupled to a control terminal of the transistor (sw1 control terminal), wherein the controller is configurable to, responsive to a state of the voltage bus (Vbus) indicating that the voltage bus does not provide a current to a sink device (USB load, this happens between φ1- φ2 at startup and between times φ4 and φ6 at the 0V output state), turn off the transistor (See fig. 4, s3 signal). (For Example: Par. 43-56 and 60-68)
Regarding Claim 18, Motoki teaches (Figures 2-5) wherein the connector (108) is a universal serial bus Type-C connector that is compatible with universal serial bus Type-C power delivery applications (par. 73).
Regarding Claim 19, Motoki teaches (Figures 2-5) wherein the transistor (sw1) is an n-channel field- effect transistor (par. 45).
Regarding Claim 21, Motoki teaches (Figures 2-5) further comprising a power supply coupled to the power terminal and to the controller (see fig. 2, 102 input and output terminals), wherein the controller (104, 140 and 110) is configurable to, responsive to the state of the voltage bus indicating that the voltage bus does not provide the current to the sink device (e.g. φ1- φ2 at startup), cause the power supply to supply power to the power terminal (at the end of φ2 ); and responsive to a voltage at the power terminal (Vout) reaching a threshold voltage (OCP condition), cause the power supply to stop supplying power to the power terminal (par. 53-56).
Regarding Claim 23, Motoki teaches (Figures 2-5) wherein a state of the voltage bus indicating that the voltage bus does not provide a current to a sink device (USB load, this happens between φ1- φ2 at startup) includes the state of the voltage bus indicating that no sink device is coupled to the voltage bus (the determination of the connection with the output device happens at φ3 which as can be seen in fig. 4 is after φ1- φ2). (For Example: Par. 43-56 and 60-68)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Chen US 10108243.
Regarding Claim 2, Motoki teaches (Figures 2-5) further comprising a connector (108) coupled to the voltage bus (Vbus) and coupled to an input of the controller (with 113). (For Example: Par. 43-56 and 60-68)
Motoki does not teach the controller configurable to receive an indication at the input that an external device is not connected to the voltage bus via the connector, and cause the power supply to supply power to the power terminal.
Chen teaches (Figure 3) the controller (102) configurable to receive an indication at the input that an external device is not connected (see Col. 2 lines 60-67 and Col 3 lines 1-12) to the voltage bus (at 108) via the connector (usb connector), and cause the power supply to supply power to the power terminal (see Col. 2 lines 60-67 and Col 3 lines 1-12).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include the controller configurable to receive an indication at the input that an external device is not connected to the voltage bus via the connector, and cause the power supply to supply power to the power terminal, as taught by Chen to reduce system power consumption.
Regarding Claim 5, Motoki teaches (Figures 2-5) wherein the connector (108) is a universal serial bus (USB) Type-C connector (par. 73).
Claim(s) 6 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Chen and further in view of Lim US 2021/0399561.
Regarding Claims 6 and 8, Motoki teaches (Figures 2-5) wherein the connector (108) is a first USB Type- C connector (par. 71), the transistor is a first transistor (sw1), the controller has a third output (another output), and the voltage bus is a first voltage bus (Vbus). (For Example: Par. 43-56 and 60-68)
Motoki as modified does not teach the apparatus further comprising: a second voltage bus: a second USB Type-C connector coupled to the second voltage bus; and a second transistor coupled between the second voltage bus and the power terminal, a control terminal of the second transistor coupled to the third output of the controller; wherein the second connector is compatible with USB Type-C power delivery applications.
Lim teaches (Figures 2) the controller (102) the apparatus further comprising: a second voltage bus (bus for 250): a second USB Type-C connector (at 210, par. 30) coupled to the second voltage bus; and a second transistor (250) coupled between the second voltage bus and the power terminal (at 230 node), a control terminal of the second transistor coupled to the third output of the controller (270); wherein the second connector is compatible with USB Type-C power delivery applications(par. 30 and 91). (For Example: Par. 62-65 and 86-91)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include the apparatus further comprising: a second voltage bus: a second USB Type-C connector coupled to the second voltage bus; and a second transistor coupled between the second voltage bus and the power terminal, a control terminal of the second transistor coupled to the third output of the controller, as taught by Lim to prevent damage due to power from external electronic devices.
Claim(s) 13-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Balakrishnan US 2018/0219399.
Regarding Claim 13, Motoki teaches (Figures 2-5) the sink device (at Usb load).
Motoki does not teach an adaptor coupling the second device to the connector.
Balakrishnan teaches (Figures 1-4) an adaptor (112, 110 and 108) coupling the second device to the connector (106 or 104). (For Example: Par. 23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include an adaptor coupling the second device to the connector, as taught by Balakrishnan to enable the system to be connected to different types of load devices.
Regarding Claim 14, Motoki teaches (Figures 2-5) wherein the connector (108) is a universal serial bus (USB) Type-C connector (par. 73).
Regarding Claim 15, Motoki teaches (Figures 2-5) the system.
Motoki does not teach wherein: the connector is a female connector; the sink device is a USB Type-A device; and the adaptor is a USB-Type A to USB Type-C adaptor.
Balakrishnan teaches (Figures 1-4) wherein: the connector (104) is a female connector; the sink device is a USB Type-A device (see fig. 1); and the adaptor is a USB-Type A to USB Type-C adaptor (see fig. 1). (For Example: Par. 23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include wherein: the connector is a female connector; the sink device is a USB Type-A device; and the adaptor is a USB-Type A to USB Type-C adaptor, as taught by Balakrishnan to enable the system to be connected to different types of load devices.
Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Lim US 2021/0399561.
Regarding Claims 16-17, Motoki teaches (Figures 2-5) wherein the connector (108) is a first USB Type- C connector (par. 71), the transistor is a first transistor (sw1), the controller has a third output (another output), and the voltage bus is a first voltage bus (Vbus). (For Example: Par. 43-56 and 60-68)
Motoki does not teach the system further comprising: a second voltage bus: a second USB Type-C connector coupled to the second voltage bus; and a second transistor coupled between the second voltage bus and the power terminal, a control terminal of the second transistor coupled to the third output of the controller; wherein the second connector is compatible with USB Type-C power delivery applications.
Lim teaches (Figures 2) the system further comprising: a second voltage bus (bus for 250): a second USB Type-C connector (at 210, par. 30) coupled to the second voltage bus; and a second transistor (250) coupled between the second voltage bus and the power terminal (at 230 node), a control terminal of the second transistor coupled to the third output of the controller (270); wherein the second connector is compatible with USB Type-C power delivery applications(par. 30 and 91). (For Example: Par. 62-65 and 86-91)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include the system further comprising: a second voltage bus: a second USB Type-C connector coupled to the second voltage bus; and a second transistor coupled between the second voltage bus and the power terminal, a control terminal of the second transistor coupled to the third output of the controller, as taught by Lim to prevent damage due to power from external electronic devices.
8. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Ripoll US 2015/0239358.
Regarding Claim 20, Motoki teaches (Figures 2-5) wherein the capacitor is a first capacitor (C1), and the system (at fig. 2, connected to 108) further includes a second capacitor (C2) having a terminal coupled to the voltage bus (Vbus.)
Motoki does not teach having a capacitance that is at least ten times smaller that a capacitance of the first capacitor.
Ripoll teaches (Figures 1-4) having a capacitance (7) that is at least ten times smaller that a capacitance of the first capacitor (21). (For Example: Par. 72)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include having a capacitance that is at least ten times smaller that a capacitance of the first capacitor, as taught by Ripoll to enable the system to obtain a good energy performance for the system.
Claim(s) 22 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motoki in view of Dahstestani US 10454360 (Hein Dash).
Regarding Claim 22, Motoki teaches (Figures 2-5) a diode of a transistor(at sw1).
Motoki does not teach wherein the threshold voltage is based on a reverse bias voltage of a diode.
Dash teaches (Figures 1-4) wherein the threshold voltage (Vout) is based on a reverse bias voltage of a diode (244-256). (For Example: Col. 4 lines 41-67 and Col. 5 lines 1-10)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Motoki to include wherein the threshold voltage is based on a reverse bias voltage of a diode, as taught by Dash to provide protection to the system during transient conditions.
Allowable Subject Matter
Claims 7 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Indicating Allowable Subject Matter
The following is an examiner’s statement of reasons for indicating Allowable Subject Matter:
Claim 7; prior art of record fails to disclose either by itself or in combination: “…further comprising a capacitor having a terminal directly connected to the second terminals of the first and second FETs, the capacitor capable of holding enough charge to reverse bias a first parasitic body diode of the first FET and a second parasitic body diode of the second FET.”
Claim 12; prior art of record fails to disclose either by itself or in combination: “… wherein the controller is configurable to cause the power supply to stop supplying power to the power terminal responsive to a first voltage at the power terminal exceeding a threshold, the threshold being based on a second voltage of the second device connected to the connector, and a reverse bias voltage of a diode of the transistor.”
These features taken alone or in combination are neither disclosed nor suggested by the prior art of record.
Response to Arguments
Applicant's arguments filed 05/06/2026 have been fully considered but they are not persuasive.
Applicant argued that “However, Motoki does not disclose that the switch SW1 (the alleged transistor) is turned off responsive to an indication that a sink device is not attached to the bus line 906. For at least these reasons, claim 1 is not anticipated by Motoki. Claim 11 is also not anticipated by Motoki for at least similar reasons as claim 1. Moreover, USPTO's burden of factually supporting a prima facie case of obviousness has not been met. The dependent claims are also not anticipated by Motoki at least due to their dependence from claims 1 or 11”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., attached to the bus line 906) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). The applicant also mentions that the Office has the burden of supporting a prima facie case of obviousness has not been met. However, the examiner is not clear what the applicant meant since the rejection is a 102 rejection not a 103 rejection as clearly mentioned in the Office Action and Applicant reply page 6 of 8.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838
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