DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-16 without traverse in the reply filed on 02/26/2026 is acknowledged. Claims 17-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 4 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites, “…….the width of the gate trench”. There is insufficient antecedent basis for this limitation in the claim. For examination purpose, examiner is considering it “…[[the]] a width of the gate trench”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3 & 6 are rejected under 35 U.S.C. 102 (a)(1)as being anticipated by Siemieniec et al. (US 20210408279 A1)
Regarding claim 1, Siemieniec teaches,
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A semiconductor device (Fig. 6) comprising a transistor (IGFET, para [0108]), the transistor comprising a plurality of transistor cells (TC, para [0112]), each of the transistor cells comprising:
a gate electrode (155, para [0115]) arranged in gate trenches (trench of 150, para [0114]) formed in a first portion of a silicon carbide substrate (portion of 100 including 120 & 137, para [0070]) and extending in a first horizontal direction (X),
wherein the gate trenches pattern the first portion of the silicon carbide substrate into ridges (as marked) so that each of the ridges is arranged between two neighboring gate trenches;
a source region of a first conductivity type (n type 110 for n-channel FET, para [0122]), a channel region of a second conductivity type (p type 120, para [0122]), and a current-spreading region of the first conductivity type (137 which may be same conductivity type as the drift region 131 , para [0128],.i.e. n type for n-channel FET, para [0122]),
wherein the source region, the channel region, and at least a part of the current-spreading region are arranged in the ridges (as seen),
wherein a current path from the source region (110) to the current-spreading region (137) extends in a depth direction of the silicon carbide substrate (current flows from source to drain and hence extends in depth direction of 100);
a body contact portion of the second conductivity type (portion of p+ type 161, FIG. 1D, in contact with p type body 120) arranged in a second portion of the silicon carbide substrate (portion of 100 including 161 & 110),
wherein the second portion is adjacent to the first portion and extends in a second horizontal direction (direction Y) that intersects the first horizontal direction,
wherein the body contact portion is electrically connected to the channel region (p+ 161 electrically connected to p type 120); and
a shielding region of the second conductivity type (including 162 & portion of 161 in contact with 137, FIG. 1G, para [0088]) ,
wherein a first portion of the shielding region (162) is arranged below the gate trenches (as seen), respectively,
and a second portion of the shielding region (portion of 161 in contact with 137, see as marked above) is arranged adjacent to a sidewall of the gate trenches, respectively (as seen).
Regarding claim 2, Siemieniec teaches the semiconductor device of claim 1 and further teaches, wherein the shielding region (second portion of shielding region 161 as marked above) is electrically connected with the body contact portion (both second portion of shielding region and body contact portion as defined are part of 161 and hence electrically connected).
Regarding claim 3, Siemieniec teaches the semiconductor device of claim 1 and further teaches, wherein the source region is also arranged in the second portion (as defined second portion including 161 & 110, so 110 arranged in the second portion).
Regarding claim 6, Siemieniec teaches the semiconductor device of claim 1 and further teaches , wherein the gate electrode continuously extends along a plurality of first and second portions of the silicon carbide substrate (as seen gate electrode 155 extends along first portion 137 & 120 and along second portion 161 & 110).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 5 , 8 & 11 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. (US 20210408279 A1)
Regarding claim 4, Siemieniec teaches the semiconductor device of claim 1 but does not explicitly teach, wherein a width of the first portion of the shielding region is larger than 0.75 times the width of the gate trench, the widths being measured in a second horizontal direction (Y) intersecting the first horizontal direction (X).
But Siemieniec additionally teach,
x1 may be equal to x2 (para [0124]), x2 may be equal to half of w1 (para [0125]) which renders x1+x2 may be equal to w1, which is larger than 0.75 times of w1.
a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985), see MPEP 2144.05.
Regarding claim 5, Siemieniec teaches the semiconductor device of claim 1 but does not explicitly teach, wherein a width of the second portion of the shielding region is smaller than 300 nm, the width being measured in a second horizontal direction (Y) intersecting the first horizontal direction (X).
But Siemieniec additionally teaches,
w1 may be in a range from 500 nm to 2 μm, para [0114],
x2 may be equal to half of w1 (para [0125]) renders x2 may be in a range of 250 nm to 1 um (half of range of w1 above)
x2 may be at most 80%, at most 65% or at most 60% of the distance dl (para [0125]) renders dl (which may be a width of the second portion 161) may be in a range of 300 nm or more.
a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985), see MPEP 2144.05.
Regarding claim 8, Siemieniec teaches,
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A semiconductor device (Fig. 6) comprising a transistor (IGFET, para [0108]), the transistor comprising a plurality of transistor cells (TC, para [0112]), each of the transistor cells comprising:
a gate electrode (155, para [0115]) arranged in gate trenches (trench of 150) formed in a first portion of a silicon carbide substrate (portion of 100 including 120 & 137, para [0070])and extending in a first horizontal direction (X),
wherein the gate trenches pattern the first portion of the silicon carbide substrate into ridges (as marked) so that each of the ridges is arranged between two neighbouring gate trenches;
a source region of a first conductivity type (n type 110 for n-channel FET, para [0122]), a channel region of a second conductivity type (p type 120, para [0122]), and a current-spreading region of the first conductivity type (137 which may be same conductivity type as the drift region 131 , para [0128],.i.e. n type for n-channel FET, para [0122]),
wherein the source region, the channel region, and at least a part of the current-spreading region are arranged in the ridges (as seen),
wherein a current path from the source region (110) to the current-spreading region (137) extend in a depth direction of the silicon carbide substrate (current flows from source to drain and hence extends in depth direction of 100);
a body contact portion of the second conductivity type (portion of p+ type 161, FIG. 1D, in contact with p type body 120) arranged in a second portion of the silicon carbide substrate (portion of 100 including 161 & 110),
wherein the second portion is adjacent to the first portion and extends in a second horizontal direction (Y) intersecting the first horizontal direction,
wherein the body contact portion is electrically connected to the channel region (body contact portion 161 electrically connected to 120);
a shielding region of the second conductivity type (including 162 & portion of 161 in contact with 137, FIG. 1G, para [0088]) arranged below the gate trenches (as seen),
………..and a source contact (portion of 161 in contact with source region 110) arranged in the second portion of the silicon carbide substrate (161 is in the second portion as defined) adjacent to the ridge and in contact with the source region (as seen),
wherein a width of the source contact (width of the source contact i.e. width of 161 in contact with 110, see marked as w2 above) is larger than a width of the ridge (width of ridge under load electrode 310 in a transistor cell TC, see marked as w1 above), the widths being measured in a horizontal direction perpendicular to the first horizontal direction (w2>w1)
But Siemieniec does not explicitly teach,
wherein a width of the shielding region is more than 0.75 times the width of the gate trench, the widths being measured in a direction perpendicular to the first direction;
But Siemieniec additionally teach,
x1 may be equal to x2 (para [0124]), x2 may be equal to half of w1 (para [0125]) which renders x1+x2 may be equal to w1, which is larger than 0.75 times of w1.
a prima facie case of obviousness exists where the claimed ranges or amounts do not overlap with the prior art but are merely close. Titanium Metals Corp. of America v. Banner, 778 F.2d 775, 783, 227 USPQ 773, 779 (Fed. Cir. 1985), see MPEP 2144.05.
Regarding claim 11, Siemieniec teaches the semiconductor device of claim 8 and further teaches , wherein a portion of the gate electrode is arranged over the ridges (see FIG. 6 above, 155 extends little over the ridge).
Claim 7 & 12 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. and further in view of Joo (KR-20210009006-A)
Regarding claim 7, Siemieniec teaches, the semiconductor device of claim 1 but does not explicitly teach, further comprising a super junction structure of the second conductivity type extending to a larger depth than a bottom side of the current- spreading region.
But Joo teaches,
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a superjunction region 800 (comprising p-type superjunction region 810 and n-type superjunction region 820, FIG. 1) and that is locally located under the p shield region 320 to suppress the expansion of a depletion region and reduce on-resistance (see Fig. 1 description)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Siemieniec such that a super junction structure 800 (810 & 820) is formed under the shield region 162 such that a super junction structure of the second conductivity type (p type 810) extending to a larger depth than a bottom side of the current- spreading region (137), according to teaching of Joo above, in order to suppress the expansion of a depletion region and reduce on-resistance, as taught by Joo above.
Regarding claim 12, Siemieniec teaches the semiconductor device of claim 8 but does not explicitly teach, further comprising a superjunction structure of the second conductivity type extending to a larger depth than a bottom side of the current- spreading region.
But Joo teaches,
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a superjunction region 800 (comprising p-type superjunction region 810 and n-type superjunction region 820, FIG. 1) and that is locally located under the p shield region 320 to suppress the expansion of a depletion region and reduce on-resistance (see Fig. 1 description)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Siemieniec such that a super junction structure 800 (810 & 820) is formed under the shield region 162 such that a super junction structure of the second conductivity type (p type 810) extending to a larger depth than a bottom side of the current- spreading region (137), according to teaching of Joo above, in order to suppress the expansion of a depletion region and reduce on-resistance, as taught by Joo above.
Claim 9 & 10 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. and further in view of Meiser et al. (US 2014/0209905 A1).
Regarding claim 9, Siemieniec teach the semiconductor device of claim 8 but does not explicitly teach, wherein the gate trenches are segmented so that an intermediate portion is arranged between two neighbouring trenches along the first direction, the intermediate portion being arranged in the second portion of the silicon carbide substrate.
But Meiser teaches,
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In a top view, gate trenches 300p and 300 p+1 separated by an intermediate portion (mesa 310) and an isolation trench 205 laterally insulating adjacent transistor (para [0033], Fig. 3A)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Siemieniec such that trenches of gate structure 150 are arranged in a segmented fashion in top view such that an intermediate portion (the ridge portion/310) is arranged in the second portion of the 100 (as defined the ridge includes both first portion and second portion of 100, hence arranged in the second portion) separated by an isolation trench 205, in order to insulate adjacent transistor.
Regarding claim 10, Siemieniec & Meiser teach the semiconductor device of claim 9 and further teaches, wherein the intermediate portion comprises a doped portion of the second conductivity type (the ridge portion includes p+ type 161) that is electrically connected to the channel region (120).
Claim 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Siemieniec et al. and further in view Mirchandani et al. (US 9673318 B1).
Regarding claim 13, Siemieniec teaches,
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A semiconductor device (Fig. 6 as annotated above) comprising a transistor (IGFET, para [0108]), the transistor comprising a plurality of transistor cells (TC, para [0112]), each of the transistor cells comprising:
a gate electrode (155, para [0115]) arranged in gate trenches (trench of 150) formed in a silicon carbide substrate (100),
……wherein the gate trenches enclose a first mesa (150 partially enclose the mesa as marked above), respectively, so that the gate electrode is adjacent to each side of the first mesa (as seen);
a source region of a first conductivity type (n type 110 for n-channel FET, para [0122]), a channel region of a second conductivity type (p type 120, para [0122]), and a current-spreading region of the first conductivity type (137, which may be same conductivity type as the drift region 131 , para [0128],.i.e. n type for n-channel FET, para [0122]),
wherein the source region, the channel region, and at least a part of the current-spreading region are arranged in the first mesa (as seen),
wherein a current path from the source region (110) to the current- spreading region (137) extends in a depth direction of the silicon carbide substrate (current flows from source to drain and hence extends in depth direction of 100);
and a shielding region (p+ type 162, para [0088], FIG. 1G) of the second conductivity type arranged below the gate trenches.
But Siemieniec does not explicitly teach,
wherein the gate trenches extend along a hexagon like or a trapezoid like path and form a grid
Meanwhile, Mirchandani teaches,
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Gate trench 110 and source trench 122 extend along a hexagon path to form a grid (Fig. 1 as annotated above, Col. 2, ll. 46-47)
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify Siemieniec such that the gate trench 150 extend along a hexagon path to form a grid, according to teaching of Mirchandani above, in order to improve avalanche ruggedness and figures of merit, such as on-state resistance and breakdown voltage, as taught by Mirchandani (Col. 1, ll. 45-48)
Regarding claim 14, Siemieniec & Mirchandani teach the semiconductor device of claim 13 and further teaches , wherein the gate trenches further enclose a second mesa (see “second mesa” as marked above in Mirchandani Fig. 1) , and wherein a doped contact portion of the second conductivity type for electrically contacting the shielding region is arranged in the second mesa (portion of p+ doped 161 in contact with 162/128 in second mesa).
Regarding claim 15, Siemieniec & Mirchandani teach the semiconductor device of claim 13 and further teaches , wherein each of the transistor cells further comprises a body contact portion of the second conductivity type (portion of p+ type 161, FIG. 1D, in contact with p type body 120, see as marked) , the body contact portion being electrically connected to the channel region (161 electrically connected to 120), and wherein the body contact portion is arranged in a central portion of the first mesa and the source region is arranged in an edge portion of the first mesa adjacent to the gate trench (as seen in FIG. 6 above).
Regarding claim 16, Siemieniec & Mirchandani teach the semiconductor device of claim 15 and further teaches , wherein the source region (110) and a doped contact portion of the second conductivity type (portion of p+ doped 161 in contact with 162) for electrically contacting the shielding region (162) are arranged in the first mesa (161 in first mesa as seen).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHATIB A RAHMAN whose telephone number is (571)270-0494. The examiner can normally be reached on MON-FRI 8:00 am- 5:00 pm (Arizona).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor Steven Gauthier, can be reached on (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813