DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 30th, 2025 has been entered.
Claim Status
Claims 1, 3, 6, 10-14, and 16 have been amended. Claims 2 and 17 have been cancelled. Claims 1, 3-16 and 18-20 remain pending and are ready for examination.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
In light of the specification and the claimed invention, the examiner is interpreting the first “means to store data” as the non-volatile memory in which the hot LBAs are comprised, and the “second means to store data” as a volatile memory in which the write commands for the hot LBAs are stored/tracked.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 4-7 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tai et al. (US Publication No. 2018/0101314 -- "Tai") in view of Daly (US Publication No. 2015/0081978 -- "Daly") in further view of Koker et al. (US Publication No. 2018/0286010 -- "Koker") in further view of Benisty et al. (US Publication No. 2022/0342550 – “Benisty”).
Regarding claim 1, Tai teaches A data storage device, comprising: a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: classify a plurality of write commands as hot logical block addresses (LBAs); increase a hot LBA counter; (Tai paragraph [0005], An embodiment of the invention provides a non-volatile memory apparatus including a non-volatile memory and a controller. The controller is coupled to the non-volatile memory. The controller is adapted to perform an address classification method to determine whether a logical address of a write command coming from a host is a hot data address. The controller accesses the non-volatile memory according to the write command of the host. The address classification method includes: providing a data look-up table, where the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value; searching the data look-up table based on the logical address of the write command in order to obtain a corresponding counter value and a corresponding timer value; and determining whether the logical address of the write command is the hot data address based on the corresponding counter value and the corresponding timer value. The controller coupled to the memory may classify a write command as corresponding to a hot address, and correspondingly increase the counter, also see Tai paragraph [0021], FIG. 2 is a flowchart illustrating an address classification method according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in step S210, the data classification circuit 114 provides a data look-up table, where the data look-up table may cache one set or a plurality sets of data entry information to identify the hot data, and the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value. In some embodiments, the logical address information can be a logical block address (LBA) or other logical address) restart a timer; (Tai paragraph [0025], Besides, in the step S230, the CPU 111 may further update the corresponding counter value Vc and the corresponding timer value Vt according to the logical address of the write command of the host 10. When the logical address information of one corresponding data entry in the data look-up table matches the logical address of the write command of the host 10, the data classification circuit 114 may add the corresponding counter value Vc of the corresponding data entry by one to track the data write frequency, and set the corresponding timer value Vt of the corresponding data entry to a first logic state (for example, logic 1) to represent a recent access. A timer corresponding to the LBA access may be reset to a first logic state) store completion information; (Tai paragraph [0021], FIG. 2 is a flowchart illustrating an address classification method according to an embodiment of the invention. Referring to FIG. 1 and FIG. 2, in step S210, the data classification circuit 114 provides a data look-up table, where the data look-up table may cache one set or a plurality sets of data entry information to identify the hot data, and the data look-up table includes a plurality of data entries, each of the data entries includes a logical address information, a counter value and a timer value. In some embodiments, the logical address information can be a logical block address (LBA) or other logical address) and flush the history buffer (Tai paragraph [0003], The write amplification also depends on write workloads. In an actual write workload, some data is updated more frequently. The frequently updated data is generally referred to as hot data. Updating of other data is probably less frequent. The less frequently updated data is generally referred to as cold data. To write the cold data and the hot data into a same memory in mixture may generally result in higher write amplification. Therefore, before the data of the host is written into the flash memory, there is a need for the flash memory storage device to identify whether the data of the host is hot data. The flash memory may identify and flush hot LBA commands based on the determination of hot data, which utilizes the hot LBA counter as detailed in claim 1) if one or more of the following has occurred: the hot LBA counter has reached a limit; (Tai paragraph [0026], In the embodiment of FIG. 3, the step S240 includes sub steps S241, S242, S243, S244 and S245. If the determination result of the step S230 represents that the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10, the CPU 111 may execute the step S241. In the step S241, the CPU 111 may check the corresponding counter value Vc and the corresponding timer value Vt found from the data look-up table. When the corresponding counter value Vc exceeds a predetermined range and the corresponding timer value Vt is in the first logic state, the CPU 111 determines the logical address of the write command of the host 10 to be the hot data address (step S242). According to the design requirement, the predetermined range can be a single boundary range or a double boundary range. For example, in some embodiments, in the step S241, it is checked whether the corresponding counter value Vc is greater than a threshold Th1 (if the corresponding counter value Vc is greater than the threshold Th1, it represents that the corresponding counter value Vc exceeds the predetermined range), where the threshold Th1 can be determined according to an actual design requirement. The hot LBA counter may be compared to a predetermined threshold value and determined to exceed the limit) or firmware (FW) requests a data flush (Tai paragraph [0018-0019], According to a design requirement, the communication interface includes a small computer system interface (SCSI), a serial attached SCSI (SAS), an enhanced small disk interface (ESDI), a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCI-express) interface, an integrated drive electronics (IDE) interface, a universal serial bus (USB), a thunderbolt interface or other interface. The interface structure between the host 10 and the NVM apparatus 100 is not limited by the present embodiment. When the host 10 sends the write command, the data to be written can be temporarily stored in the memory buffer 113, and the CPU 111 may convert/decode the write command (including the logical address) of the host 10 into a corresponding internal control signal (including a physical address of the NVM 120), and provide the internal control signal to the memory control circuit 112 and/or the memory buffer 113)
Tai does not teach aggregate the plurality of hot LBAs in a history buffer; a timeout of the timer has been reached; or a workload counter is less than a predetermined threshold; retrieving data for a most recent write command added to the history buffer and associated with a hot LBA without retrieving data for other write commands in the history buffer associated with the same hot LBA; write the retrieved data to the non-volatile memory device; and post a completion for the most recent write command and the other write commands in the history buffer associated with the hot LBA.
However, Daly teaches a timeout of the timer has been reached; or a workload counter is less than a predetermined threshold (Daly paragraph [0056], In some embodiments, a global cache manager; e.g., global cache manager 214, can use a timer to periodically request information about memory allocated to application 212. The information about memory used by application 212 can be one of the above-mentioned example notifications related to memory allocation. For example, global cache manager 214 can set a timer for a predetermined period of time (500 ms, 1 second, 2 seconds). Then, upon expiration of the timer, global cache manager 214 can be informed of the timer expiration and responsively request information how much memory is used by a specified application; e.g., application 212. In these embodiments, a timer expiration event that leads to a request for information how much memory is used can be a triggering event to global cache manager 212. The cache may be connected to a timer which has a predetermined value for timeout, as well as a memory allocation threshold value).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai with those of Daly. Daly teaches using a predetermined value for a timeout of a timer for a cache, which can improve memory allocation and operation selection (Daly paragraph [0038], Turning to the figures, FIG. 1 is a flow chart of method 100, in accordance with an example embodiment. Method 100 begins at block 110, where a mobile device can receive an indication of a triggering event related to memory allocated for an application, such as discussed below in the context of FIGS. 2A-4C. The application can be configured to be executed on the mobile device. In some embodiments, the triggering event can be an event selected from the group consisting of: an insertion event requesting to insert a requested amount of memory into the cache, a memory-allocation notification event, and a timer expiration event).
Tai in view of Daly does not teach aggregate the plurality of hot LBAs in a history buffer; retrieving data for a most recent write command added to the history buffer and associated with a hot LBA without retrieving data for other write commands in the history buffer associated with the same hot LBA; write the retrieved data to the non-volatile memory device; and post a completion for the most recent write command and the other write commands in the history buffer associated with the hot LBA.
However, Koker teaches aggregate the plurality of hot LBAs in a history buffer (Koker paragraph [0147], According to one embodiment, replacement control logic 712 monitors trackers 710 and determines a replacement policy for cache 720 based on information received from trackers 710. In this embodiment, control logic 712 determines the trackers 710 that are being frequently used (e.g., hot trackers) and those that are currently being infrequently or unused (e.g., cold trackers). Accordingly, control logic 712 recognizes the cache address 720 ranges associated with a hot tracker and applies a replacement policy based on the regions having the most accesses. For example, control logic 712 may implement a LRU or LRA replacement policy using data from trackers 710 to make sure data in hot address ranges (e.g., corresponding to hot trackers) are not evicted from cache 720. Alternatively, control logic 712 may evict data in address ranges corresponding to hot trackers if implementing a most recently used (MRU) replacement policy. In other embodiments, control logic 712 may apply the replacement policy based on the regions having the least accesses (e.g., cold regions). A hot tracker may be used to monitor and track a plurality of logical block addresses and address ranges) retrieving data for a most recent write command added to the history buffer (see cache tracker below) and associated with a hot LBA without retrieving data for other write commands in the history buffer associated with the same hot LBA (Koker paragraph [0147], According to one embodiment, replacement control logic 712 monitors trackers 710 and determines a replacement policy for cache 720 based on information received from trackers 710. In this embodiment, control logic 712 determines the trackers 710 that are being frequently used (e.g., hot trackers) and those that are currently being infrequently or unused (e.g., cold trackers). Accordingly, control logic 712 recognizes the cache address 720 ranges associated with a hot tracker and applies a replacement policy based on the regions having the most accesses. For example, control logic 712 may implement a LRU or LRA replacement policy using data from trackers 710 to make sure data in hot address ranges (e.g., corresponding to hot trackers) are not evicted from cache 720. Alternatively, control logic 712 may evict data in address ranges corresponding to hot trackers if implementing a most recently used (MRU) replacement policy. In other embodiments, control logic 712 may apply the replacement policy based on the regions having the least accesses (e.g., cold regions). A hot tracker may be used to monitor and track a plurality of logical block addresses and address ranges, which can involve retrieval of only specific selected address ranges).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai and Daly with those of Koker. Koker teaches aggregating hot LBAs in a buffer component, which can prevent cache management from replacing hot LBAs through a replacement policy, ensuring improved performance (Koker paragraph [0147], For example, control logic 712 may implement a LRU or LRA replacement policy using data from trackers 710 to make sure data in hot address ranges (e.g., corresponding to hot trackers) are not evicted from cache 720).
Tai in view of Daly in further view of Koker does not teach write the retrieved data to the non-volatile memory device; and post a completion for the most recent write command and the other write commands in the history buffer associated with the hot LBA.
However, Benisty teaches write the retrieved data to the non-volatile memory device; and post a completion for the most recent write command and the other write commands in the history buffer associated with the hot LBA (Benisty paragraph [0048], However, if LBA “X” is not equal to LBA “Y” at block 606, then at block 610, the controller determines if LBA “X” is equal to LBA “B.” If LBA “X” is not equal to LBA “B,” then the write command is executed. However, if LBA “X” does equal LBA “B,” the pending simple copy command is canceled at block 612. At block 614, the write command is executed. In one embodiment, the copy commands are executed since the read data is already cached, such that the pending copy command queue (e.g., the one or more simple copy command slots 318 and the copy command queue 316) are flushed to the NVM 328. The data from the retrieved LBA may be written to NVM, and the completion can be indicated for the write command as well as other pending commands corresponding to overlapping LBAs, see Benisty paragraph [0006], In one embodiment, a data storage device is disclosed that includes a copy command manager comprising a copy command slot, and a controller comprising an overlap table, the controller configured to execute a method for a simple copy. The method includes receiving a copy command from a host, receiving copy data from a NAND, and allocating the copy command slot to the copy command. The method further includes updating the overlap table, and posting a completion of the copy command to the host).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai, Daly and Koker with those of Benisty. Benisty teaches flushing retrieved LBAs corresponding to a write command to non-volatile memory, as well as commands in a buffer targeted towards overlapping LBAs, which can optimize the memory performance and remove delays associated with command execution (i.e., see Benisty paragraph [0005], The present disclosure generally relates to methods and systems for executing a simple copy command in a manner that mitigates additional latency in the device. According to certain embodiments, a copy command manager that includes one or more copy command slots is provided. When a simple copy command is received from a host, a copy command slot is allocated to the command and the simple copy command is copied into the copy command slot. Upon copying the simple copy command to the copy command slot, an overlap table of the data storage device controller is updated to indicate the copy has been completed, and the completion is posted to the host. After posting, the simple copy command is carried out in the background through completion).
Regarding claim 4, Tai in view of Daly in further view of Koker in further view of Benisty teaches The data storage device of claim 1, wherein the hot LBA counter limit is a predetermined value (Tai paragraph [0026], In the embodiment of FIG. 3, the step S240 includes sub steps S241, S242, S243, S244 and S245. If the determination result of the step S230 represents that the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10, the CPU 111 may execute the step S241. In the step S241, the CPU 111 may check the corresponding counter value Vc and the corresponding timer value Vt found from the data look-up table. When the corresponding counter value Vc exceeds a predetermined range and the corresponding timer value Vt is in the first logic state, the CPU 111 determines the logical address of the write command of the host 10 to be the hot data address (step S242). According to the design requirement, the predetermined range can be a single boundary range or a double boundary range. For example, in some embodiments, in the step S241, it is checked whether the corresponding counter value Vc is greater than a threshold Th1 (if the corresponding counter value Vc is greater than the threshold Th1, it represents that the corresponding counter value Vc exceeds the predetermined range), where the threshold Th1 can be determined according to an actual design requirement).
Regarding claim 5, Tai in view of Daly in further view of Koker in further view of Benisty teaches The data storage device of claim 1, wherein the timeout of the timer is a predetermined value (Daly paragraph [0056], In some embodiments, a global cache manager; e.g., global cache manager 214, can use a timer to periodically request information about memory allocated to application 212. The information about memory used by application 212 can be one of the above-mentioned example notifications related to memory allocation. For example, global cache manager 214 can set a timer for a predetermined period of time (500 ms, 1 second, 2 seconds). Then, upon expiration of the timer, global cache manager 214 can be informed of the timer expiration and responsively request information how much memory is used by a specified application; e.g., application 212. In these embodiments, a timer expiration event that leads to a request for information how much memory is used can be a triggering event to global cache manager 212. The cache may be connected to a timer which has a predetermined value for timeout).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai with those of Daly and Koker and Benisty. Daly teaches using a predetermined value for a timeout of a timer for a cache, which can improve memory allocation and operation selection (Daly paragraph [0038], Turning to the figures, FIG. 1 is a flow chart of method 100, in accordance with an example embodiment. Method 100 begins at block 110, where a mobile device can receive an indication of a triggering event related to memory allocated for an application, such as discussed below in the context of FIGS. 2A-4C. The application can be configured to be executed on the mobile device. In some embodiments, the triggering event can be an event selected from the group consisting of: an insertion event requesting to insert a requested amount of memory into the cache, a memory-allocation notification event, and a timer expiration event).
Regarding claim 6, Tai in view of Daly in further view of Koker in further view of Benisty teaches The data storage device of claim 1, wherein the controller is configured to classify a new write command upon determining that at least one has not occurred (Tai paragraph [0033], When the determination result of the step S420 represents that the host command counter value host_write_count is smaller than the threshold N, the data classification circuit 114 may wait the host 10 to send a next write command (step S430). After the host 10 sends the next write command (the step S430), the data classification circuit 114 returns to the step S410 to add the host command counter value host_write_count by one. When the write command counter has not exceeded a threshold value, new write commands may be continued to be performed).
Regarding claim 7, Tai in view of Daly in further view of Koker in further view of Benisty teaches The data storage device of claim 1, wherein the controller is configured to receive a plurality of write commands for the hot LBA (Tai paragraph [0024], In the step S230, the CPU 111 may search the data look-up table of the data classification circuit 114 according to the logical address information (for example, the identification code) of the step S310, so as to determine whether the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10. If the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10, the CPU 111 may obtain the corresponding data entry in the step S230, so as to obtain a corresponding counter value Vc and a corresponding timer value Vt from the corresponding data entry. The controller (see Tai fig. 1; #110) may receive a plurality of write commands that may be targeted towards a hot LBA, as previously determined, such as in Tai paragraph [0026], When the corresponding counter value Vc exceeds a predetermined range and the corresponding timer value Vt is in the first logic state, the CPU 111 determines the logical address of the write command of the host 10 to be the hot data address (step S242)).
Regarding claim 9, Tai in view of Daly in further view of Koker in further view of Benisty teaches The data storage device of claim 1, wherein the controller is configured to process a plurality of write commands for a plurality of hot LBAs (Tai paragraph [0024], In the step S230, the CPU 111 may search the data look-up table of the data classification circuit 114 according to the logical address information (for example, the identification code) of the step S310, so as to determine whether the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10. If the data look-up table includes the corresponding data entry having the logical address information matching the logical address of the write command of the host 10, the CPU 111 may obtain the corresponding data entry in the step S230, so as to obtain a corresponding counter value Vc and a corresponding timer value Vt from the corresponding data entry. The controller (see Tai fig. 1; #110) may receive a plurality of write commands that may be targeted towards a hot LBA, as previously determined, such as in Tai paragraph [0026], When the corresponding counter value Vc exceeds a predetermined range and the corresponding timer value Vt is in the first logic state, the CPU 111 determines the logical address of the write command of the host 10 to be the hot data address (step S242)).
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tai in view of Daly in further view of Koker in further view of Benisty as applied to claim 1 above, and further in view of Linkovsky et al. (US Publication No. 2018/0314421 -- "Linkovsky").
Regarding claim 3, Tai in view of Daly in further view of Koker in further view of Benisty and further in view of Linkovsky teaches The data storage device of claim 1, wherein flushing the history buffer further comprises: waiting for command completion of the most recent write command (Linkovsky paragraph [0047], FIG. 3 illustrates a sequence of steps for processing a command via the NVMe standard. As shown, the host device 300 includes host memory 302, and the memory device includes a controller, such as an NVMe controller 310. In one implementation, the host memory 302 includes a submission queue 304 and a completion queue 306. Further, in one implementation, the submission queues and completion queues may have a 1:1 correlation. Command completion messages may be sent in a 1:1 correlation indicating a most recent write command has a command completion message sent) prior to posting the completion for all the write commands; (Linkovsky paragraph [0024], In another implementation, the memory device uses the detected streams (such as the detected write and/or read streams) in order to determine addresses (or address ranges) that are often used in host device commands. These often used addresses (or address ranges) may be termed “hot addresses” or “hot address ranges”. In practice, the host device may perform multiple accesses to specific LBA address or to specific small range of the LBA addresses. In order to more efficiently process commands (such as write commands or read commands), the memory device may use a frequently-used address algorithm in order to determine the specific address (such as the specific LBA address) or a specific range of addresses (such as the specific range of LBA addresses) frequently used. The frequently-used address algorithm may use the previously detected streams (such as the detected write streams and/or the detected read streams) in the determination. In particular, if the incoming command falls within a hot range of one of the previously detected streams, then the algorithm determines if the incoming command is a write command or a read command. If the incoming command is a write command, the memory device may save the data to an internal buffer (such as a volatile internal buffer), deferring saving the data into non-volatile memory. The saving to non-volatile memory may be deferred in expectation that the host device will soon rewrite the data. If the incoming command is a read command, the memory device reads the data from the internal buffer without performing a read access from the non-volatile memory. The first write command may be indicated as completed without executing the write to non-volatile memory, while completing and indicating completion of a second write command to the same LBA range) and clearing the hot LBA counter (Linkovsky paragraphs [0101-0102], The internal variable i may be defined to indicate the number of the current entry. At the beginning of the operation, i=0. At 710, the SDM 523 increments variable i and begins to perform checks of conditions and calculations on the first entry i. At 712, the SDM 532 checks whether locality was already detected before or not. If yes, at 714, the flow chart moves to 728. If not, the flow chart moves to 722. The counter for the hot LBA tracker may be reset to 0 pending a new set of write commands (i.e., after flushing buffer)).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai and Daly and Koker and Benisty with those of Linkovsky. Linkovsky teaches Linkovsky teaches the aggregation of write commands to hot LBA ranges which can be executed in a more efficient manner by sending a completion for a first command prior to execution, only retrieving the data for a second write command, which can reduce the transfer latency for host write commands in both directions (Linkovsky paragraph [0025], Using this information, the memory device may more intelligently process host device commands without host device support. In particular, using this information generated by the frequently-used address logic, the memory device may save the data stored at the designated address in the internal buffer after the write access and read the data stored in the internal buffer during the read access without reading the data from non-volatile memory. In this way, the memory device may save transfer latency in both directions and may decrease the total number of accesses to the non-volatile memory device).
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tai in view of Daly in further view of Koker in further view of Benisty as applied to claim 7 above, and further in view of Rajwade et al. (US Publication No. 2023/0154539 -- "Rajwade").
Regarding claim 8, Tai in view of Daly in further view of Koker in further view of Benisty and further in view of Rajwade teaches The data storage device of claim 7, wherein the controller is configured to skip at least one write command of the plurality of write commands (Rajwade paragraph [0122], Example 21 includes a system comprising at least one memory chip comprising a group of memory cells coupled to a wordline; and a storage device controller coupled to the at least one memory chip, the storage device controller to detect a sequential write operation; skip programming of one or more pages of the group of memory cells responsive to the detection of the sequential write operation; and request programming of the one or more pages of the group of memory cells responsive to one or more random write commands. When a plurality of write commands is transmitted to the controller, a particular one of the write commands may be skipped).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Tai, Daly, Koker and Benisty with those of Rajwade. Rajwade teaches skipping one of a plurality of write commands by a controller, which can allow the controller additional flexibility regarding the execution of the programming commands, such as in the case of a sequential write operation or overlapping write operation (Rajwade paragraph [0122], Example 21 includes a system comprising at least one memory chip comprising a group of memory cells coupled to a wordline; and a storage device controller coupled to the at least one memory chip, the storage device controller to detect a sequential write operation; skip programming of one or more pages of the group of memory cells responsive to the detection of the sequential write operation; and request programming of the one or more pages of the group of memory cells responsive to one or more random write commands).
Claim(s) 10-13 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Linkovsky et al. (US Publication No. 2018/0314421 -- "Linkovsky") in view of Koker et al. (US Publication No. 2018/0286010 -- "Koker") in further view of Tai et al. (US Publication No. 2018/0101314 -- "Tai").
Regarding claim 10, Linkovsky teaches A data storage device, comprising: a non-volatile memory device; and a controller coupled to the non-volatile memory device, wherein the controller is configured to: (Linkovsky paragraph [0027], FIG. 1A is a block diagram illustrating a non-volatile memory device 100. The non-volatile memory device 100 may include a controller 102 and non-volatile memory that may be made up of one or more non-volatile memory dies 104. As used herein, the term die refers to the set of non-volatile memory cells, and associated circuitry for managing the physical operation of those non-volatile memory cells, that are formed on a single semiconductor substrate. The controller 102 may interface with a host device or a host system and transmit command sequences for read, program, and erase operations to the non-volatile memory die(s) 104) receive a first write command to write data to a first logical block address (LBA); receive a second write command to write data to the first LBA, wherein the second write command is received (Linkovsky paragraph [0024], In another implementation, the memory device uses the detected streams (such as the detected write and/or read streams) in order to determine addresses (or address ranges) that are often used in host device commands. These often used addresses (or address ranges) may be termed “hot addresses” or “hot address ranges”. In practice, the host device may perform multiple accesses to specific LBA address or to specific small range of the LBA addresses. In order to more efficiently process commands (such as write commands or read commands), the memory device may use a frequently-used address algorithm in order to determine the specific address (such as the specific LBA address) or a specific range of addresses (such as the specific range of LBA addresses) frequently used. Write commands may specifically target the same hot LBA ranges) retrieving data associated with the second write command; writing the retrieved data associated with the second write command to the non-volatile memory device, (see Linkovsky paragraphs [0019-0020], In a second specific implementation, the memory device, analyzing incoming write commands, detects a write stream With regard to the analysis, one or more aspects of the incoming command may be analyzed in order to determine whether the aspect(s) are local or proximate to the one or more aspects of the command(s) previously assigned to the identified stream. In one implementation, the memory device analyzes an address (or an address range) of the incoming command to determine whether the address (or address range) of the incoming command is local or proximate to an address (or address range) in the stream command(s). The plurality of write command data can be retrieved via the incoming stream commands) wherein the retrieved data is associated with the second write command; and posting a completion message to the host device for the second write command after the retrieving (Linkovsky paragraph [0024], In another implementation, the memory device uses the detected streams (such as the detected write and/or read streams) in order to determine addresses (or address ranges) that are often used in host device commands. These often used addresses (or address ranges) may be termed “hot addresses” or “hot address ranges”. In practice, the host device may perform multiple accesses to specific LBA address or to specific small range of the LBA addresses. In order to more efficiently process commands (such as write commands or read commands), the memory device may use a frequently-used address algorithm in order to determine the specific address (such as the specific LBA address) or a specific range of addresses (such as the specific range of LBA addresses) frequently used. The frequently-used address algorithm may use the previously detected streams (such as the detected write streams and/or the detected read streams) in the determination. In particular, if the incoming command falls within a hot range of one of the previously detected streams, then the algorithm determines if the incoming command is a write command or a read command. If the incoming command is a write command, the memory device may save the data to an internal buffer (such as a volatile internal buffer), deferring saving the data into non-volatile memory. The saving to non-volatile memory may be deferred in expectation that the host device will soon rewrite the data. If the incoming command is a read command, the memory device reads the data from the internal buffer without performing a read access from the non-volatile memory. The first write command may be indicated as completed without executing the write to non-volatile memory, while completing and indicating completion of a second write command to the same LBA range).
Linkovsky does not teach flush the buffer, wherein the flushing comprises: prior to executing the first write command and the first and second write commands are aggregated in a buffer.
However, Koker teaches prior to executing the first write command and the first and second write commands are aggregated in a buffer (Koker paragraph [0079], In one embodiment, the accelerator integration circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching the virtual/effective to physical/real address translations. In one implementation, a cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in cache 438 and graphics memories 433-434, N is kept coherent with the core caches 462A-462D, 456 and system memory 411. A plurality of commands can be aggregated before submission in a cache/buffer, which can include write commands, see Koker paragraph [0049], The L2 cache 221 is a read/write cache that is configured to perform load and store operations received from the memory crossbar 216 and ROP 226).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Linkovsky with those of Koker. Koker teaches aggregating a plurality of write commands in a buffer, which can allow for improved processing for command operation (Koker paragraph [0049], The L2 cache 221 is a read/write cache that is configured to perform load and store operations received from the memory crossbar 216 and ROP 226. Read misses and urgent write-back requests are output by L2 cache 221 to frame buffer interface 225 for processing. Dirty updates can also be sent to the frame buffer via the frame buffer interface 225 for opportunistic processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in parallel processor memory, such as the memory units 224A-224N of FIG. 2 (e.g., within parallel processor memory 222)).
Linkovsky in view of Koker does not teach flush the buffer, wherein the flushing comprises.
However, Tai teaches flush the buffer, wherein the flushing comprises: (Tai paragraph [0003], The write amplification also depends on write workloads. In an actual write workload, some data is updated more frequently. The frequently updated data is generally referred to as hot data. Updating of other data is probably less frequent. The less frequently updated data is generally referred to as cold data. To write the cold data and the hot data into a same memory in mixture may generally result in higher write amplification. Therefore, before the data of the host is written into the flash memory, there is a need for the flash memory storage device to identify whether the data of the host is hot data. Tai teaches the concept of flushing a buffer in the context of a memory device executing commands targeted to determined LBAs).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Linkovsky and Koker with those of Tai. teaches the concept of flushing a buffer in the context of a memory device executing commands targeted to determined LBAs, which can improve allocation of memory space for determined hot/cold data (i.e., see Tai paragraph [0003], The write amplification also depends on write workloads. In an actual write workload, some data is updated more frequently. The frequently updated data is generally referred to as hot data. Updating of other data is probably less frequent. The less frequently updated data is generally referred to as cold data. To write the cold data and the hot data into a same memory in mixture may generally result in higher write amplification. Therefore, before the data of the host is written into the flash memory, there is a need for the flash memory storage device to identify whether the data of the host is hot data).
Regarding claim 11, Linkovsky in view of Koker in further view of Tai teaches The data storage device of claim 10, wherein the flushing occurs when a write flow is otherwise idle (Linkovsky paragraph [0057], Each entry in the PRP list may be associated with a certain section in the host device memory, and may be a predetermined size, such as 4 Kb. Thus, in a 1 Mb transfer, there may be 250 references in the PRP list, each 4 Kb in size. In practice, the memory device may retrieve data out of sequence. This may be due to the data subject to retrieval being on several flash dies, with the dies being available for data retrieval at different times. For example, the memory device may retrieve the data corresponding to 100-200 Kb of the 1 Mb transfer before retrieving the data corresponding to 0-100 Kb of the 1 Mb transfer. Nevertheless, because the memory device has the PRP list (and therefore knows the memory locations the host device expects the data corresponding to 100-200 Kb to be stored), the memory device may transfer the data corresponding to 100-200 Kb of the 1 Mb transfer without having first retrieved the data corresponding to 0-100 Kb of the 1 Mb transfer. Retrieval of the write commands that are queued may be based on the current write flow).
Regarding claim 12, Linkovsky in view of Koker in further view of Tai teaches The data storage device of claim 10, wherein the flushing occurs when a remaining queue depth is below a predetermined threshold (Linkovsky paragraph [0048], In practice, at the initialization phase, the host device 300 creates one or more submission queues and one or more corresponding completion queues. In particular, the host device 300 may notify the memory device of the submission queue(s) and completion queue(s) by sending information, such as the base address for each queue to the memory device. In that regard, each submission queue has a corresponding completion queue. When the submission queue and the completion queue are resident in the host device, the host device sends information to the memory device in order for the memory device to determine the locations of the submission queue and the completion queue in the host device. In a specific implementation, the host device sends a command indicating the creation of the submission queue and the completion queue. The command may include a PRP1 pointer, which is a pointer to a list on the host device of the locations of the specific submission queue or the specific completion queue. The submission and completion queue may utilize a queue command depth that may be used to indicate write commands, see Linkovsky paragraph [0049] for queue command).
Regarding claim 13, Linkovsky in view of Koker in further view of Tai teaches The data storage device of claim 10, wherein the flushing occurs prior to beginning a reset flow (Linkovsky paragraph [0050], In step 2, the host device 300 writes to a submission queue tail doorbell register 312 in the memory device. This