DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 6, 9 and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Morris et al. 20120033978 herein Morris.
Per claim 1, Morris discloses: at least one processor; at least one optical channel; and at least one photonic substrate separate (interpreted as memory DIMM’s) from the at least one processor, (fig. 5;) the at least one photonic substrate comprising a plurality of memory units and at least one photonic network for providing the at least one processor access to the plurality of memory units, (fig. 5, ¶0028; The system 500 comprises a first expansion DIMM 502 loaded into a DIMM slot of a primary board 504. The expansion DIMM 502 includes an electronic interface 506 and an optical interface 508. The electronic interface 506 is in electronic communication with a processor 510 via a first DDRx interface 512 and is in electronic communication with the optical interface 508) wherein: the at least one photonic network (fig. 8, comp 804) is in communication with the at least one processor through the at least one optical channel; (¶0029; DIMM 514 and a memory expansion board 516. The expansion DIMM 514 is loaded into a DIMM slot of the memory expansion board 516 and includes an optical interface 518 and an electronic interface 520, which is in electronic communication with two DIMMs 522 and 524 via a second DDRx interface 526 and in electronic communication with the optical interface 518. FIG. 5 also shows that the expansion DIMMs 502 and 514 are in optical communication via waveguides 528 and 530 that optically couple interfaces 508 and 518) and the at least one photonic network is programmable to configure which of the plurality of memory units in the at least one photonic substrate the at least one processor can access through the at least one optical channel (¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512. The electronic interface 506 performs parallel-to-serial flow control by converting the parallel electronic signals into serial electronic signals and includes a memory buffer that stores the information encoded in the electronic signals to compensate for variations in the rate at which data is output from the processor 510. The serial electronic signals are sent to the optical interface 508 and converted into optical signals encoding the same information, which are sent over the waveguide 530 to the optical interface 518 which converts the optical signals back into serial electronic signals that are sent to the second electronic interface 520. The electronic interface 520 performs serial-to-parallel flow control by converting the serial electronic signals into parallel electronic signals and includes a memory buffer to store the information encoded in the electronic signals to compensate for variations in the rate at which data is sent from the expansion DIMM 502. The parallel electronic signals that are sent over the DDRx interface 526 for storage in DIMMs 522 and 524).
Per claim 2, Morris discloses: wherein, the at least one processor comprises a first processor and a second processor; and the first processor and the second processor are configured to process a dataset using the plurality of memory units (fig. 2, ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 3, Morris discloses: the at least one photonic network is programmed to enable access to a first memory unit of the plurality of memory units by the first processor and to enable access to a second memory unit of the plurality of memory units by the second processor; and processing the dataset comprises: executing, by the first processor, an operation using data stored in the first memory unit to obtain a first output; and storing the first output in the first memory unit (fig. 2, ¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512… Data stored in the DIMMs 522 and 524 is sent to the processor 510 by sending parallel electronic signal over the DDRx interface 526 to the expansion DIMM 514; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 6, Morris discloses: wherein: the at least one photonic network is programmed to enable access to a subset of the plurality of memory units by the at least one processor through the at least one optical channel (fig. 2, ¶0030-31; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 9, Morris discloses: wherein, the at least one processor comprises a first processor and a second processor; the plurality of memory units comprises a first memory unit and a second memory unit; and the at least one photonic network is programmed to enable access to the first memory unit by the first processor and access to the second memory unit by the second processor ((fig. 2, ¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512… Data stored in the DIMMs 522 and 524 is sent to the processor 510 by sending parallel electronic signal over the DDRx interface 526 to the expansion DIMM 514; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 12, Morris discloses: wherein: the at least one processor comprises a plurality of processors; the at least one optical channel comprises a plurality of optical channels; and each of the plurality of processors is in communication with the at least one photonic network through a respective one of the plurality of optical channels ((fig. 2, ¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512… Data stored in the DIMMs 522 and 524 is sent to the processor 510 by sending parallel electronic signal over the DDRx interface 526 to the expansion DIMM 514; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 13, Morris discloses: wherein: the at least one photonic network comprises a plurality of photonic networks; the at least one photonic substrate comprises a plurality of photonic modules each including: a respective one of the plurality of photonic networks; a subset of the plurality of memory units; and a memory controller. wherein each of the plurality of processors is connected to memory controllers of the plurality of photonic modules through a respective one of the plurality of optical channels ((fig. 2, ¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512… Data stored in the DIMMs 522 and 524 is sent to the processor 510 by sending parallel electronic signal over the DDRx interface 526 to the expansion DIMM 514; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206).
Per claim 14, Morris discloses: wherein the at least one photonic network is programmed into a configuration to allocate memory units among the plurality of processors based on memory requirements for execution of a plurality of software applications, wherein the configuration: enables access to a first set of the plurality of memory units by a first one of the plurality of processors configured to execute a first software application; and enable access to a second set of the plurality of memory units by a second one of the plurality of processors configured to execute a second software application ((fig. 2, ¶0030-31; When the processor 510 stores data in the DIMMs 522 and 524, the processor 510 sends parallel electronic signals comprising the data, address, and control information to the expansion DIMM 502 over the DDRx interface 512… Data stored in the DIMMs 522 and 524 is sent to the processor 510 by sending parallel electronic signal over the DDRx interface 526 to the expansion DIMM 514; ¶0023; The first interface 202 receives electronic signals encoding data, address, and control information produced by the processors 206 and converts the electronic signals into optical signals 214 that are sent to the second interface 208. The second interface 208 receives the optical signals 214 and converts the optical signals 214 back into electronic signals that are sent to and stored in memory 210. In order to retrieve data stored in memory 210, the data is encoded in electronic signals that are sent to the second interface 208, which converts the electronic signals into optical signals 216 that are sent to the first interface 202, which, in turn, converts the optical signals 216 into electronic signals that can be processed by the processors 206; the examiner notes that the processors are performing similar tasks and the different processors are merely showing an iteration of the function but a plurality of processor sand DIMM”S ).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 7-8, 10-11 and 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Morris et al. 20120033978 herein Morris in view of Graves et al. 6198558 herein Graves.
Per claim 7, Morris discloses a plurality of processors accessing a DIMM network but does not specifically disclose: wherein, at a first time, the at least one photonic network is programmed to enable access to a first one of the plurality of memory units by the at least one processor through the at least one optical channel; and at a second time subsequent to the first time, the at least one photonic network is programmed to: disable access to the first memory unit by the at least one processor through the at least one optical channel; and enable access to a second one of the plurality of memory units by the at least one processor through the at least one optical channel.
However, Graves discloses: wherein, at a first time, the at least one photonic network is programmed to enable access to a first one of the plurality of memory units by the at least one processor through the at least one optical channel; and at a second time subsequent to the first time, the at least one photonic network is programmed to: disable access to the first memory unit by the at least one processor through the at least one optical channel; and enable access to a second one of the plurality of memory units by the at least one processor through the at least one optical channel (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU through the at least one first optical transceiver and destined for the core network; the examiner notes that the enable and disabling is not specifically defined in the specification and is merely a function of the switch).
It would have been obvious to one having ordinary skill in the art at the effective filing date of the invention to combine the teachings of Morris and Graves optical network unit to enable bidirectional communication between a host and network. Graves improves the efficiency and reliability of the ON. (col. 14 lines 56-66; relocation of digital signal processing tasks from the ONU to the HDT results in a cheaper, simpler, more efficient and more reliable ONU for deployment deep into the network. On the HDT side, considerable gains in DSP efficiency are also realized. For example, although individual processors are dedicated to a particular task, say conversion of mu-law PCM to linearly encoded samples, a single DSP can be used to perform the task at hand on a number of different data streams. These streams may be destined for completely different ports on the network, such as LIUs on different ONUs in different PONs).
Per claim 8, Graves discloses: wherein, the at least one photonic network comprises at least one optical switch configurable to connect/disconnect the at least one processor to/from each of the plurality of memory units; and the at least one photonic network is programmable by configuring the at least one optical switch (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU through the at least one first optical transceiver and destined for the core network).
Per claim 10, Graves discloses: wherein, the at least one processor comprises a plurality of processors, the plurality of processors organized into multiple sets of processors; and the at least one photonic network is programmed to enable each of the sets of processors to access a different subset of the plurality of memory units through the at least one optical channel (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU through the at least one first optical transceiver and destined for the core network).
Per claim 11, Graves discloses: wherein, each of the sets of processors and respective subset of the plurality of memory units accessible by the set of processors forms a respective virtual processor assigned to a respective virtual machine (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU, and at least one second signal processing function to be executed by a second subset of the plurality of DSPs on data arriving from the LIU through the at least one first optical transceiver and destined for the core network).
Per claim 15, Graves discloses: further comprising an optical switch, wherein:the at least one photonic substrate comprises a plurality of photonic substrates, the plurality of photonic substrates each comprising a set of memory units and a respective photonic network, wherein photonic networks of the plurality of substrates are each programmable to configure which of a respective set of memory units can be accessed by the at least one processor; and the optical switch is configurable to provide the at least one processor with access to multiple memory units distributed across multiple ones of the plurality of photonic substrate (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU).
Per claim 16, Graves discloses: wherein: the at least one photonic substrate comprises at least one memory controller; the at least one photonic network comprises an optical circuit interconnecting the at least one memory controller with the plurality of memory units; and the at least one photonic network comprises a plurality of electrical/optical (E/O) transceivers each connecting a respective one of the plurality of memory units to the optical circuit (col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU).
Per claim 17, Graves discloses: wherein: the at least one photonic substrate comprises: at least one memory controller; at least one fiber attach, the at least one fiber attach connected to the at least one optical channel; and at least one E/O transceiver; and the at least one photonic network comprises: an optical circuit connecting the at least one memory controller to the at least one fiber attach, wherein the at least one E/O transceiver is configured to convert signals transmitted between the at least one memory controller and the at least one fiber attach; and a plurality of electrical connections between the at least one memory controller and the plurality of memory units, wherein data signals are transmitted between the at least one memory controller and the plurality of memory units through the plurality of electrical connections (fig. 1B, col. 4 lines 23-42; a host digital terminal (HDT) for enabling bidirectional communication between a core network and at least one optical network unit (ONU) having a plurality of line interface units (LIUs), the HDT comprising a digital switch matrix, a plurality of programmable digital signal processors (DSPs) connected to the digital switch matrix for executing the signal processing functions; at least on first optical transceiver connected between the optical fiber and the switch matrix; at least one second optical transceiver for connection to the core network and connected to the switch matrix; and means to control the digital switch matrix so as to select, for each LIU, at least one first signal processing function to be executed by a first subset of the plurality of DSPs on data arriving from the core network through the at least one second optical transceiver and destined for the LIU).
Allowable Subject Matter
Claims 4-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 18-20 are allowed.
Remark
Examiner respectfully requests, in response to this Office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist Examiner in prosecuting the application.
Conclusion
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BABOUCARR . FAAL
Primary Examiner
Art Unit 2138
/BABOUCARR FAAL/Primary Examiner, Art Unit 2138