DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign mentioned in the description: “SWn” (Paragraph 70, lines 13 and 17, amend “SWn” to “SWn-1”). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informality: On Paragraph 28, line 1, replace “the the offset RTI voltage” with “the offset RTI voltage”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 14 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites the limitation "the inverting input end" in line 3. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “an inverting input end of the amplifier of the current sensing amplifier circuit” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Fortuny (Patent Publication Number US 2022/0057469 A1), hereafter referred to as Fortuny, in view of Koller et al. (Patent Publication Number DE 102005007632 A1), hereafter referred to as Koller.
Regarding claim 1, Fortuny discloses:
A current sensing amplifier circuit (Fortuny, Fig. 3), which is configured to operably sense a current to be sensed (“to-be-sensed current”) flowing through a sensing resistor (Fig. 3, consider current Iin through sense resistor RSNS), wherein the sensing resistor has two ends correspondingly coupled to a first input end (Fig. 3, see connection between RSNS and R1) and a second input end of the current sensing amplifier circuit (Fig. 3, see connection between RSNS and R3); the current sensing amplifier circuit comprising: an amplifier (Fig. 3, A1), which is configured to operably generate an output voltage correlated with the to-be-sensed current according to a first input voltage at the first input end and a second input voltage at the second input end in a normal operation mode (Fig. 3, consider output voltage Vs_out based on input voltages Vhp and Vhn, as dependent on to-be-sensed current Iin); a first resistor (Fig. 3, R2) coupled between a reference voltage (Fig. 3, see connection between R2 and Vref) and a non-inverting input end of the amplifier (Fig. 3, see connection between R2 and Vhp), wherein a resistance of the first resistor is a sum of a first resistance plus a first error resistance (Paragraph 59, lines 19-20); a second resistor (Fig. 3, R4) coupled between the output voltage (Fig. 3, see connection between R4 and Vs_out) and an inverting input end of the amplifier (Fig. 3, see connection between R4 and Vhn), wherein a resistance of the second resistor is a difference of the first resistance minus the first error resistance (Paragraph 59, lines 19-20); a third resistor (Fig. 3, R1) coupled between the first input end (Fig. 3, see connection between R1 and RSNS) and the non-inverting input end of the amplifier (Fig. 3, see connection between R1 and Vhp), wherein a resistance of the third resistor is a difference of a second resistance minus a second error resistance (Paragraph 59, line 18); a fourth resistor (Fig. 3, R3) coupled between the second input end (Fig. 3, see connection between R3 and RSNS) and the inverting input end of the amplifier (Fig. 3, see connection between R3 and Vhn), wherein a resistance of the fourth resistor is a sum of the second resistance plus the second error resistance (Paragraph 59, line 18); and a current source circuit (Fig. 3, 201A), which is configured to operably generate a trimming current in a trimming mode according to the first input voltage and the reference voltage, according to the second input voltage and the reference voltage, or according to an input common mode voltage and the reference voltage (Fig. 3, see connection between 201A, Vhp, and Vref), and the current source circuit is configured to operably provide the trimming current to trim an offset referred to input (RTI) voltage generated due to the first error resistance and the second error resistance in the normal operation mode (Paragraph 31, lines 1-9, see also Paragraph 6, lines 3-9); wherein the current source circuit is coupled to: a first node between the first resistor and the non-inverting input end, a second node between the second resistor and the output voltage, a third node between the third resistor and the non-inverting input end, or a fourth node between the fourth resistor and the inverting input end (Fig. 3, see connection between 201A, output of 202, and R4); but fails to disclose wherein in the trimming mode, the first input end is electrically connected to the second input end, so that the first input voltage has a same voltage level as the second input voltage.
However, Koller teaches wherein in the trimming mode, the first input end is electrically connected to the second input end, so that the first input voltage has a same voltage level as the second input voltage (Koller, Fig. 1, see switch 11, see also Page 5, Paragraph 2, lines 2-3).
Fortuny and Koller are both considered to be analogous to the claimed invention because they are in the same field of reducing amplifier offsets. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Fortuny to incorporate the teachings of Koller to include the switch of Koller in the circuit of Fortuny, which would have the effect of providing a calibration mode for the circuit of Fortuny (Koller, Page 5, Paragraph 2, lines 2-3).
Regarding claim 8, Fortuny further discloses:
wherein the trimming current is proportional to a difference between the first input voltage and the reference voltage, a difference between the second input voltage and the reference voltage, or a difference between the input common mode voltage and the reference voltage (Fortuny, Paragraph 29, lines 8-12).
Regarding claim 9, Fortuny further discloses:
wherein the first error resistance is smaller than 1/2 of the first resistance (Fortuny, Paragraph 59, lines 19-20) and the second error resistance is smaller than 1/2 of the second resistance (Paragraph 59, line 18).
Claims 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Fortuny in view of Koller as applied to claim 1 above, and further in view of Puşcaşu et al. “A High Voltage Current Sense Amplifier With Extended Input Common Mode Range Based On a Low Voltage Operational Amplifier Cell”, as cited by applicant, hereafter referred to as Puşcaşu.
Regarding claim 5, Fortuny and Koller fail to disclose:
wherein the reference voltage is configured to operably adjust the input common mode voltage, so that the current sensing amplifier circuit has a bidirectional current sensing function.
However, Puşcaşu teaches wherein the reference voltage is configured to operably adjust the input common mode voltage, so that the current sensing amplifier circuit has a bidirectional current sensing function (Puşcaşu, Page 1, Section II., lines 6-8).
Fortuny, Koller, and Puşcaşu are all considered to be analogous to the claimed invention because they are in the same field of reducing amplifier offsets. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Fortuny to incorporate the teachings of Puşcaşu to include the variable reference voltage of Puşcaşu in the circuit of Fortuny, which would have the effect of improving matching figures while reducing circuit area (Puşcaşu, Page 4, Section IV., lines 1-6).
Regarding claim 6, Fortuny and Koller fail to disclose:
further comprising: a chopper circuit coupled between the inverting input end and the non-inverting input end, wherein the chopper circuit is configured to operably suppress a variation of the offset RTI voltage caused by different input common mode voltages.
However, Puşcaşu teaches further comprising: a chopper circuit (Puşcaşu, Fig. 1, Elements Dpf, Dpr, PTG, and NTG) coupled between the inverting input end and the non-inverting input end (Fig. 1, see connection between IN+ and IN- via Dpf/Dpr/PTG/NTG), wherein the chopper circuit is configured to operably suppress a variation of the offset RTI voltage caused by different input common mode voltages (Page 1, Section II., lines 9-16).
Fortuny, Koller, and Puşcaşu are all considered to be analogous to the claimed invention because they are in the same field of reducing amplifier offsets. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Fortuny to incorporate the teachings of Puşcaşu to include the chopper circuit of Puşcaşu in the circuit of Fortuny, which would have the effect of protecting the circuit of Fortuny against high differential input voltages (Page 1, Section II., lines 9-12).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fortuny in view of Koller as applied to claim 1 above, and further in view of Jasa et al. (Patent Publication Number US 2015/0015333 A1), hereafter referred to as Jasa.
Regarding claim 10, Fortuny fails to disclose:
wherein the current source circuit is configured to operably generate the trimming current in the trimming mode according to the first input voltage and the reference voltage by a binary approximation approach, a single-slope approximation approach or a successive approximation approach.
However, Jasa teaches wherein the current source circuit is configured to operably generate the trimming current in the trimming mode according to the first input voltage and the reference voltage by a binary approximation approach, a single-slope approximation approach or a successive approximation approach (Jasa, Paragraph 11, lines 18-21).
Fortuny, Koller, and Jasa are all considered to be analogous to the claimed invention because they are in the same field of reducing amplifier offsets. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Fortuny to incorporate the teachings of Jasa to use a successive approximation approach in the circuit of Fortuny, which would have the effect of optimizing the trimming current (Jasa, Paragraph 11, lines 18-21).
Allowable Subject Matter
Claims 2-4 and 7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 11-13 and 15-19 are allowed over the prior art of record.
Claim 14 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art, when taken alone, or in combination, cannot be construed as reasonably teaching or suggesting all of the elements of the claimed invention as arranged, disposed, or provided in the manner as claimed by the applicant.
The closest prior art is Fortuny (Patent Publication Number US 2022/0057469 A1), hereafter referred to as Fortuny. Fortuny discloses a current sense amplifier including a trimming current generation circuit to cancel an offset voltage in the current sense amplifier, but fails to disclose the trimming current generation circuit including first and second voltage-to-current conversion circuits, and therefore, Fortuny is not suitable for the application as claimed in claims 2-4 and 11-19. Furthermore, Fortuny also fails to disclose “wherein the offset RTI voltage is correlated with a compensation item of the trimming current, and wherein the compensation item is irrelevant to a gain error of the amplifier”, and therefore, Fortuny is not suitable for the application as claimed in claim 7.
As allowable subject matter has been indicated, applicant's reply must either comply with all formal requirements or specifically traverse each requirement not complied with. See 37 CFR 1.111(b) and MPEP § 707.07(a).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nakatani (Patent Number US 11,429,131 B2) discloses (Fig. 4B) a trimming current circuit including a current mirror.
O’Shaughnessy (Patent Number US 6,166,670 A) discloses (Fig. 5) resistors with error resistances of 0.5% of the intended resistance value.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843