Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 8-9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by YoonJaeHo KR 10-2012-0030724, hereinafter, ‘724
In regards to claim 1, ‘724 teaches a semiconductor substrate comprising: an insulating substrate (abstract);
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a plurality of gate lines and a plurality of source lines formed above the insulating (fig. 8 GI pg. 9 1st para.) substrate (claim 1; )(fig. 4 source lines from 12)
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a first electronic circuit formed above the insulating substrate and connected to the plurality of gate lines (claim 1((fig. 4 13 gate driving circuit above 10) (pg. 7);
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a first lead line (fig. 8 VSTL) formed above the insulating substrate and provided with a first signal (fig 8.VST) (page 8);
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a second lead line formed above the insulating substrate and electrically connected to the first electronic circuit (line to ST1 page 8);
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and a first inductor provided above the insulating substrate and electrically connected between the first lead line and the second lead line.(page 8) (fig. 8 (L between VSTL and ST1)
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In regards to claim 2, ‘724 teaches The semiconductor substrate of claim 1, further comprising: a third lead line formed above the insulating substrate and provided with a second signal; a fourth lead line formed above the insulating substrate and electrically connected to the first electronic circuit; and a second inductor provided above the insulating substrate and electrically connected between the third lead line and the fourth lead line (fig. 4 20 for both the left and right side and corresponding lead lines).
In regards to claim 8, ‘724 teaches semiconductor substrate of claim 1, wherein the first inductor is a coil.(fig. 8 coil L)
In regards to claim 9, ‘724 teaches semiconductor substrate of claim 8, wherein the coil is formed above the insulating substrate (page 8 figs. 8-10 above GLS/GI).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3-7 and 11-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘724 in view of Nitobe et al (2018/0024678) hereinafter, Nitobe.
In regards to claim 11, ‘724 teaches an electronic device comprising (abstract):
a semiconductor substrate including an insulating substrate, a plurality of gate lines and a plurality of source lines (fig. 4 lines from 12)) formed above the insulating substrate, a first electronic circuit formed above the insulating substrate (fig. 8 GI pg. 9 1st para.) substrate (claim 1; ) and connected to the plurality of gate lines, a first lead line formed above the insulating substrate and provided with a first signal and a second lead line formed above the insulating substrate and electrically connected to the first electronic circuit (fig. 4 clk1-n for left and right side)
‘724 fails to expressly teach a wiring substrate.
However, Nitobe teaches a wiring substrate (fig. 1 (28) wiring for 34 for example).
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It would have been obvious to one of ordinary skill in the art to modify the teachings of ‘724 to further include a wiring substrate as taught by Nitobe in order to save space with a wiring substrate that is flexible.
Therefore, ‘724 in view of Nitobe teaches a wiring substrate including a third lead line electrically connected to the first lead line and a fourth lead line electrically connected to the second lead line, and coupled to the semiconductor substrate; and a first inductor provided on the wiring substrate and electrically connected between the third lead line and the fourth lead line. (line to ST1 page 8) (claim 1((fig. 4 13 gate driving circuit above 10) (pg. 7),(fig. 8 VSTL) (fig 8.VST) (page 8) fig. 4 for left or right side 20 ‘724 in view of (fig. 1 (28) wiring and 34 for example) Nitobe.
;
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In regards to claim 3, ‘724 fails to teach the semiconductor substrate of claim 1, further comprising: a second electronic circuit formed above the insulating substrate and connected to the plurality of source lines a third lead line formed above the insulating substrate and provided with a second signal ; a fourth lead line formed above the insulating substrate and electrically connected to the second electronic circuit; and a second inductor provided above the insulating substrate and electrically connected between the third lead line and the fourth lead line.
However, Nitobe teaches a source amplifier and corresponding leads. (fig. 12 (118, 104s)) Nitobe.
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It would have been obvious to one of ordinary skill in the art to modify the teachings of Nitobe to further include a source amplifier and corresponding leads in order to provide data to the pixels in a conventual means of driving displays, as taught by Nitobe, and to further include a second inductor as taught by ‘724 (fig. 4 20 on both sides) connected to the source driver in order to prevent flicker noise as suggested in the last paragraph of ‘724.
Therefore, the semiconductor substrate of claim 1, further comprising: a second electronic circuit formed above the insulating substrate and connected to the plurality of source lines a third lead line formed above the insulating substrate and provided with a second signal (fig. 12 (118, 104s)leads) Nitobe; a fourth lead line formed above the insulating substrate and electrically connected to the second electronic circuit; and a second inductor provided above the insulating substrate and electrically connected between the third lead line and the fourth lead line ‘724 (fig. 4 20 on both sides).
In regards to claim 4, ‘724 teaches semiconductor substrate of claim 3, further comprising: a display area in which the plurality of gate lines and the plurality of source lines are provided; a non-display area outside the display area; and a plurality of pixel electrodes formed above the insulating substrate and located in the display area, (fig. 4 10 in-between gate drivers) ‘724 wherein the first electronic circuit is a gate line driving circuit located in the non-display area and electrically connected to the plurality of pixel electrodes to drive the plurality of pixel electrodes, and the second electronic circuit is a demultiplexer located in the non-display area and connected to the plurality of source lines. (fig. 12 (pixels in-between gate drivers and 104 mux outside of pixels) Nitobe.
In regards to claim 5, ‘724 teaches semiconductor substrate of claim 4, further comprising: a common electrode formed above the insulating substrate, located in the display area, and having a plurality of electrodes; and a third electronic circuit formed above the insulating substrate and located in the non-display area(fig. 2 (48)[0052]) Nitobe, wherein the third electronic circuit is electrically connected to the plurality of electrodes and is a circuit for driving the plurality of electrodes. (fig. 4 data drivers 12) ‘724 and (fig. 12 (16) Nitobe).
In regards to claim 6, ‘724 teaches semiconductor substrate of claim 5, wherein the first inductor is located in the non-display area. .( fig. 4 for left or right side 20 ‘724 in view of (fig. 1 (28) wiring for 34 for example) Nitobe.
In regards to claim 7, ‘724 teaches semiconductor substrate of claim 4, wherein the first inductor is located in the non-display area. .( fig. 4 for left or right side 20 ‘724 in view of (fig. 1 (28) wiring for 34 for example) Nitobe.
In regards to claim 12, ‘724 teaches electronic device of claim 11, further comprising: a second inductor, wherein the semiconductor substrate further includes a fifth lead line formed above the insulating substrate and provided with a second signal, and a sixth lead line formed above the insulating substrate and electrically connected to the first electronic circuit, (line to ST1 page 8) (claim 1((fig. 4 13 gate driving circuit above 10) (pg. 7),(fig. 8 VSTL) (fig 8.VST) (page 8) for left and right side ‘724 the wiring substrate further includes a seventh lead line electrically connected to the fifth lead line and an eighth lead line electrically connected to the sixth lead line, and the second inductor is provided on the wiring substrate and is electrically connected between the seventh lead line and the eighth lead line (fig. 4 for left or right side 20 ‘724 in view of (fig. 1 (28) wiring for 34 for example) Nitobe.
In regards to claim 13, ‘724 teaches electronic device of claim 11, further comprising: a second inductor, wherein the semiconductor substrate further includes a second electronic circuit formed above the insulating substrate and connected to the plurality of source lines, a fifth lead line formed above the insulating substrate and provided with a second signal, and a sixth lead line formed above the insulating substrate and electrically connected to the second electronic circuit (fig. 4 left and right gate drivers 13s) ‘724, the wiring substrate further includes a seventh lead line electrically connected to the fifth lead line and an eighth lead line electrically connected to the sixth lead line, and the second inductor is provided on the wiring substrate and is electrically connected between the seventh lead line and the eighth lead line. (fig. 4 for left or right side 13 ‘724 in view of (fig. 1 (28) wiring for 34 for example) Nitobe.
In regards to claim 14, ‘724 teaches electronic device of claim 13, wherein the semiconductor substrate further includes a display area in which the plurality of gate lines and the plurality of source lines are provided, a non-display area outside the display area, and a plurality of pixel electrodes formed above the insulating substrate and located in the display area (fig. 4 10 in-between gate drivers) ‘724, the first electronic circuit is a gate line driving circuit located in the non-display area and electrically connected to the plurality of pixel electrodes to drive the plurality of pixel electrodes, and the second electronic circuit is a demultiplexer located in the non-display area and connected to the plurality of source lines.(fig. 12 (pixels in-between gate drivers and 104 mux outside of pixels) Nitobe.
In regards to claim 15, ‘724 teaches electronic device of claim 14, wherein the semiconductor substrate further includes a common electrode including a plurality of electrodes formed above the insulating substrate and located in the display area (fig. 2 (48)[0052]) Nitobe, and a third electronic circuit formed above the insulating substrate and located in the non-display area, and the third electronic circuit is electrically connected to the plurality of electrodes and is a circuit for driving the plurality of electrodes (fig. 4 data drivers 12) ‘724 and (fig. 12 (16) Nitobe).
In regards to claim 16, ‘724 teaches electronic device of claim 11, wherein the first inductor is a coil. (fig. 8 coil L) ‘724
In regards to claim 17, ‘724 teaches electronic device of claim 16, wherein the coil is formed inside the wiring substrate.( fig. 4 for left or right side 20 ‘724 in view of (fig. 1 (28) wiring for 34 for example) Nitobe.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘724 in view of Hatano et al (2015/0212623) hereinafter, Hatano.
In regards to claim 10, ‘724 fails to teach the semiconductor substrate of claim 1, wherein the first inductor is a ferrite bead.
However, Hatano teaches wherein the first inductor is a ferrite bead [112].
It would have been obvious to one of ordinary skill in the art to modify the teachings of ‘724 to further include wherein the first inductor is a ferrite bead through simple substitution of one known inductor for another and the results would have been predictable at removing noise. [112]
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over ‘724 and Nitobe in view of Hatano et al (2015/0212623) hereinafter, Hatano.
In regards to claim 18, ‘724 and Nitobe fail to teach the electronic device of claim 11, wherein the first inductor is a ferrite bead.
However, Hatano teaches wherein the first inductor is a ferrite bead [112].
It would have been obvious to one of ordinary skill in the art to modify the teachings of ‘724 and Nitobe to further include wherein the first inductor is a ferrite bead through simple substitution of one known inductor for another and the results would have been predictable at removing noise. [112]
Conclusion
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/GRANT SITTA/Primary Examiner, Art Unit 2622