Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 8/7/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Elmala (US 20070229165 A1).
Regarding Independent Claim 1, Elmala teaches,
A power amplifier circuit (Fig. 2, 200) comprising:
a first carrier amplifier (Fig. 2, 220) comprising a carrier differential amplifier circuit (Fig. 2, 222 and 224) that comprises a first transistor (Fig. 2, 222) and a second transistor (Fig. 2, 224), the first carrier amplifier (Fig. 2, 220) being in or on a semiconductor substrate [See paragraph [0024], “Embodiments represented by FIG. 2 may be completely integrated on silicon as lumped elements structures are used to approximate, in a narrow-band sense, the behavior of the quadrature hybrid, impedance transformation circuit, and output matching circuit.”]; and
a first peak amplifier (Fig. 2, 230) that is in or on the semiconductor substrate,
wherein an emitter or a source of the first transistor is electrically connected to an emitter or a source of the second transistor (Fig. 2, 222 and 224 are connected through an emitter/source), wherein the emitter or the source of the first transistor is electrically connected to a ground electrode by a first bump (Fig. 2, 222 is coupled to ground), and wherein the emitter or the source of the second transistor is electrically connected to the ground electrode by a second bump, the second bump being different from the first bump (Fig. 2, 224 is connected to a different ground through 251).
Regarding claim 2,
The power amplifier circuit according to Claim 1,
wherein the first peak amplifier (Fig. 2, 230) comprises a peak differential amplifier circuit (Fig. 2, 232 and 234) comprising a third transistor (Fig. 2, 232) and a fourth transistor (Fig. 2, 234), and wherein an emitter or a source of the third transistor is electrically connected to an emitter or a source of the fourth transistor (Fig. 2, 232 and 234 are connected through an emitter/source).
Regarding claim 3,
The power amplifier circuit according to Claim 2,
wherein the emitter or the source of the third transistor is electrically connected to the ground electrode by a third bump (Fig. 2, 232 is coupled to ground), and wherein the emitter or the source of the fourth transistor is electrically connected to the ground electrode by a fourth bump, the fourth bump being different from the third bump (Fig. 2, 234 is connected to a different ground through 261).
Regarding claim 4,
The power amplifier circuit according to Claim 2, wherein the emitter or the source of the first transistor or the emitter or the source of the second transistor is electrically connected to the emitter or the source of the third transistor by a conductor (Fig. 2, 250).
Regarding claim 5,
The power amplifier circuit according to Claim 1, wherein the first bump comprises a plurality of bumps electrically connected in parallel with each other (Fig. 2, 220 and 230 are connected in parallel, meaning that the grounds are parallel to each other. See paragraph [0016], “FIG. 2 shows a parallel power amplifier circuit with slab inductors in accordance with various embodiments of the present invention. Parallel power amplifier circuit 200 is shown as one side of a differential system. Parallel power amplifier circuit 200 includes driver amplifier 210, carrier amplifier 220, and peak amplifier 230. Parallel power amplifier 200 also includes slab inductors 240, 242, 216, 226, 236, 250, and 260.”]).
Regarding claim 6,
The power amplifier circuit according to Claim 1, wherein the second bump comprises a plurality of bumps electrically connected in parallel with each other (Fig. 2, 220 and 230 are connected in parallel, meaning that the grounds are parallel to each other. See paragraph [0016], “FIG. 2 shows a parallel power amplifier circuit with slab inductors in accordance with various embodiments of the present invention. Parallel power amplifier circuit 200 is shown as one side of a differential system. Parallel power amplifier circuit 200 includes driver amplifier 210, carrier amplifier 220, and peak amplifier 230. Parallel power amplifier 200 also includes slab inductors 240, 242, 216, 226, 236, 250, and 260.”]).
Regarding claim 7,
The power amplifier circuit according to Claim 3, wherein the third bump comprises a plurality of bumps electrically connected in parallel with each other (Fig. 2, 220 and 230 are connected in parallel, meaning that the grounds are parallel to each other. See paragraph [0016], “FIG. 2 shows a parallel power amplifier circuit with slab inductors in accordance with various embodiments of the present invention. Parallel power amplifier circuit 200 is shown as one side of a differential system. Parallel power amplifier circuit 200 includes driver amplifier 210, carrier amplifier 220, and peak amplifier 230. Parallel power amplifier 200 also includes slab inductors 240, 242, 216, 226, 236, 250, and 260.”]).
Regarding claim 8,
The power amplifier circuit according to Claim 3, wherein the fourth bump comprises a plurality of bumps electrically connected in parallel with each other (Fig. 2, 220 and 230 are connected in parallel, meaning that the grounds are parallel to each other. See paragraph [0016], “FIG. 2 shows a parallel power amplifier circuit with slab inductors in accordance with various embodiments of the present invention. Parallel power amplifier circuit 200 is shown as one side of a differential system. Parallel power amplifier circuit 200 includes driver amplifier 210, carrier amplifier 220, and peak amplifier 230. Parallel power amplifier 200 also includes slab inductors 240, 242, 216, 226, 236, 250, and 260.”]).
Regarding claim 9,
The power amplifier circuit according to Claim 4, wherein the conductor is an inductor or a resistor (Fig. 2, 250 is an inductor).
Regarding claim 10,
The power amplifier circuit according to Claim 1, further comprising:
a second carrier amplifier (Fig. 2, 212) that is connected in series with the first carrier amplifier (Fig. 2, 220) at an input side of the first carrier amplifier; and
a second peak amplifier (Fig. 2, 214) that is connected in series with the first peak amplifier (Fig. 2, 230) at an input side of the first peak amplifier.
Regarding claim 11,
The power amplifier circuit according to Claim 10, wherein a collector or a drain of the first carrier amplifier (Fig. 2, 220) and a collector or a drain of the first peak amplifier (Fig. 2, 230) are electrically connected to a combiner (Fig. 2, 260).
Regarding claim 12,
The power amplifier circuit according to Claim 10, wherein the second peak amplifier (Fig. 2, 214) is in or on the semiconductor substrate [See paragraph [0024], “Embodiments represented by FIG. 2 may be completely integrated on silicon as lumped elements structures are used to approximate, in a narrow-band sense, the behavior of the quadrature hybrid, impedance transformation circuit, and output matching circuit.”].
Regarding independent claim 13,
A power amplifier circuit (Fig. 2, 200) comprising:
a third carrier (Fig. 2, 220) amplifier;
a fourth carrier amplifier (Fig. 2, 212) that is connected in series with the third carrier amplifier (Fig. 2, 220) at an input side of the third carrier amplifier (Fig. 2, input of 220);
a third peak amplifier (Fig. 2, 230) comprising a peak differential amplifier circuit (Fig. 2, 232 and 234) that comprises a sixth transistor (Fig. 2, 232) and a seventh transistor (Fig. 2, 234); and
a fourth peak amplifier (Fig. 2, 214) that is connected in series with the third peak amplifier (Fig. 2, 230) at an input side of the third peak amplifier (Fig. 2, input of 230), wherein an emitter or a source of the sixth transistor (Fig. 2, 232) is electrically connected to a ground electrode by a fifth bump (Fig. 2, 232 is connected to a ground), and wherein an emitter or a source of the seventh transistor (Fig. 2, 234) is electrically connected to the ground electrode by a sixth bump, the sixth bump being different from the fifth bump (Fig. 2, 234 is connected to ground through 261).
Regarding independent claim 14,
A power amplifier circuit (Fig. 2, 200) comprising:
a first carrier amplifier (Fig. 2, 220) comprising a differential amplifier circuit (Fig. 2, 222 and 224) that comprises a first transistor (Fig. 2, 222) and a second transistor (Fig. 2, 224), the first carrier amplifier (Fig. 2, 220) being in or on a semiconductor substrate [See paragraph [0024], “Embodiments represented by FIG. 2 may be completely integrated on silicon as lumped elements structures are used to approximate, in a narrow-band sense, the behavior of the quadrature hybrid, impedance transformation circuit, and output matching circuit.”]; and
a first peak amplifier (Fig. 2, 230) that is in or on the semiconductor substrate [See paragraph [0024], “Embodiments represented by FIG. 2 may be completely integrated on silicon as lumped elements structures are used to approximate, in a narrow-band sense, the behavior of the quadrature hybrid, impedance transformation circuit, and output matching circuit.”],
wherein an emitter or a source of the first transistor is electrically connected to an emitter or a source of the second transistor (Fig. 2, 222 and 224 are connected through an emitter/source), wherein the emitter or the source of the first transistor is electrically connected to a ground electrode by a first via (Fig. 2, 222 is coupled to ground), and wherein the emitter or the source of the second transistor is electrically connected to the ground electrode by a second via, the second via being different from the first via (Fig. 2, 224 is connected to a different ground through 251).
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843