DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1 and 13.
Pending: 1-15.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: BONDED SEMICONDUCTOR MEMORY DEVICE WITH TRENCH CAPACITOR STACK.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-5, 7-11 and 13-15 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Nishikawa et al., US Patent 9589981 B2.
Re: Independent Claim 1, Nishikawa discloses a first semiconductor structure (46, 32, 601 and stacks 400, fig. 13B) comprising a gate structure (46, 32 and 601, fig. 13B) and a stack (400, fig. 13B), the gate structure (46, 32 and 601, fig. 13B) including channel structures (601, fig. 13B) and the stack (400, fig. 13B) including a capacitor (400, fig. 13A-13E); and
a second semiconductor structure (10 and 61, fig. 13B ) that is bonded to the first semiconductor structure (46, 32, 601 and stacks 400, fig. 13B), the second semiconductor structure (10 and 61, fig. 13B ) including a peripheral circuit (circuit within substrate 10, fig. 13B; column 8, lines 21-30),
wherein the capacitor (400, fig. 13A-13E) comprises conductive layers (146, fig. 13B) and dielectric layers (32, fig. 13B) that are alternately stacked along an internal surface of a trench that is formed within the stack (400, fig. 13B).
Re: Claim 2, Nishikawa disclose(s) all the limitations of claim 1 on which this claim depends. Nishikawa further discloses: a contact plug (76, fig. 13B) that extends through the stack (400, fig. 13B), the contact plug (76, fig. 13B) being connected to the peripheral circuit (circuit within substrate 10, fig. 13B; column 8, lines 21-30).
Re: Claim 3, Nishikawa disclose(s) all the limitations of claim 2 on which this claim depends. Nishikawa further discloses: wherein the contact plug (76, fig. 13B) has a height that is substantially identical (as shown in figure 13B the height of the contact plug 76 is considerably same as the capacitor stacks) with a height of the capacitor (400, fig. 13A-13E).
Re: Claim 4, Nishikawa disclose(s) all the limitations of claim 2 on which this claim depends. Nishikawa further discloses: wherein the contact plug (76, fig. 13B) has a smaller width (width of plug 76 has a smaller width than conductive layer 146 of the capacitor) than the capacitor (400, fig. 13A-13E).
Re: Claim 5, Nishikawa disclose(s) all the limitations of claim 2 on which this claim depends. Nishikawa further discloses: a first contact via (96, fig. 13B) that is connected to the contact plug (76, fig. 13B); and second contact vias (8CO1 and 8CO2, fig. 13B) that are connected to the conductive layers (146, fig. 13B), respectively.
Re: Claim 7, Nishikawa disclose(s) all the limitations of claim 5 on which this claim depends. Nishikawa further discloses: a first wire (96, fig. 13A) that is connected to the first contact via (96, fig. 13B); and a second wire (823, fig. 13A) that is connected to at least one of the second contact vias (8CO1 and 8CO2, fig. 13B).
Re: Claim 8, Nishikawa disclose(s) all the limitations of claim 5 on which this claim depends. Nishikawa further discloses: wherein the first wire (96, fig. 13A) and the second wire (823, fig. 13A) have heights that are substantially identical with each other.
Re: Claim 9, Nishikawa disclose(s) all the limitations of claim 2 on which this claim depends. Nishikawa further discloses: wherein the contact plug (76, fig. 13B) and the conductive layers (146, fig. 13B) comprise molybdenum (column 11, lines 62-66).
Re: Claim 10, Nishikawa disclose(s) all the limitations of claim 1 on which this claim depends. Nishikawa further discloses: a source structure (96, 76 and 61, fig. 13A-13B) that is disposed on the gate structure (46, 32 and 601, fig. 13B), the source structure (96, 76 and 61, fig. 13A-13B) being connected to the channel structures (601, fig. 13B).
Re: Claim 11, Nishikawa disclose(s) all the limitations of claim 1 on which this claim depends. Nishikawa further discloses: wherein a thickness of each of the conductive layers (146, fig. 13B) and the dielectric layers (32, fig. 13B) is 300 to 600 Å (20 nm to 50 nm; column 10, lines 1-5).
Re: Independent Claim 13, Nishikawa discloses a stack comprising sacrificial layers (46, fig. 8A-8C) and insulating layers (32, fig. 8A-8C) that are alternately stacked;
a contact plug (76, fig. 13B) that extends through the stack (400, fig. 13B);
a first capacitor (400, fig. 13A-13E) that is disposed within the stack (400, fig. 13B), the first capacitor (400, fig. 13A-13E) including first conductive layers (146U1 and 146O1, fig. 13B) and first dielectric layers (32, fig. 13B) that are alternately stacked;
a second capacitor (400, fig. 13A-13E) that is disposed within the stack (400, fig. 13B), the second capacitor (400, fig. 13A-13E) including second conductive layers (146U2 and 146O2, fig. 13B) and second dielectric layers (32, fig. 13B) that are alternately stacked; and
an interconnection structure (822, 821, 831, fig. 13A) that connects the first capacitor (146U1 and 146O1, fig. 13A-13E) and the second capacitor (146U2 and 146O2, fig. 13A-13E) in parallel.
Re: Claim 14, Nishikawa disclose(s) all the limitations of claim 13 on which this claim depends. Nishikawa further discloses: wherein the first conductive layers (146U1 and 146O1, fig. 13E) comprise an even first conductive layer (146O1, fig. 13E) and an odd first conductive layer (146U1, fig. 13E) and
wherein the second conductive layers (146U2 and 146O2, fig. 13E) comprise an even second conductive layer (146U2, fig. 13E) and an odd second conductive layer (146O2, fig. 13E).
Re: Claim 15, Nishikawa disclose(s) all the limitations of claim 14 on which this claim depends. Nishikawa further discloses: a first wire (833, fig. 13E) that is connected to the odd first conductive layer (146U1, fig. 13E) and the even second conductive layer (146U2, fig. 13E); and a second wire (823, fig. 13E) that is connected to the even first conductive layer (146O1, fig. 13E) and the odd second conductive layer (146O2, fig. 13E).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 6 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Nishikawa et al., US Patent 9589981 B2 in view of Yang et al., US PG pub. 20230138205 A1.
Re: Claim 6, Nishikawa discloses all the limitations of claim 5 on which this claim depends. Nishikawa is silent regarding: wherein the first contact via (96, fig. 13B) and the second contact vias (8CO1 and 8CO2, fig. 13B) are disposed under the stack (400, fig. 13B) and have heights that are substantially identical with each other.
Yang discloses memory device stack structure can form upside down as show the peripheral circuit 102 can form on the stop surface of the memory device 104.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to form a peripheral circuit above the memory structure since this can increase memory density (¶0043).
Re: Claim 12, Nishikawa discloses all the limitations of claim 5 on which this claim depends. Nishikawa is silent regarding: wherein the peripheral circuit (circuit within substrate 10, fig. 13B; column 8, lines 21-30) comprises an input and output circuit, and
wherein the input and output circuit faces the capacitor (400, fig. 13A-13E).
Yang discloses in figure 1B an I/O circuit can form on the memory cell array and peripheral circuit (¶0050).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an input/output circuit on to the memory array and peripheral circuit since the I/O circuit can makes it easier to manage different peripherals and enables to transfer data directly to or from memory.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Chang et al., US PG pub. 20190341386 A1”) Discloses a a substrate, plural gates, plural cell plugs, a capacitor structure and a stacked structure. The gates are disposed in the substrate, and the cell plugs are disposed on the substrate, to electrically connect the substrate at two sides of each gate. The capacitor structure includes plural capacitors, and each capacitor is electrically connected each cell plug. The stacked structure covers the capacitor structure, and the stacked structure includes a semiconductor layer, a conductive layer on the semiconductor layer and an insulating layer stacked on the conductive layer. Two gaps are defined respectively between a side portion of the insulating layer and a lateral portion of the conductive layer at two sides of the capacitor structure, and the two gaps have different lengths.
* (“Chung US PG pub. 20170221919 A1”) discloses a substrate including a cell region and a peripheral region adjacent to the cell region, a cell stack structure located in the cell region, the cell stack structure including vertical memory strings, a circuit located in the peripheral region, the circuit driving the vertical memory strings, and an interlayer insulating layer formed on the substrate to cover the cell stack structure and the circuit, and including air gaps located between the cell region and the peripheral region.
* (“Ahn et al., US PG pub. 20130049086 A1”) discloses a semiconductor substrate having a cell region and a peripheral circuit region defined therein, semiconductor memory elements formed over the semiconductor substrate in the cell region, an interlayer insulating layer formed over the semiconductor substrate in the peripheral circuit region, first conductive layers substantially vertically passing through the interlayer insulating layer, and arranged in a matrix, and second conductive layers coupling the first conductive layers in rows or columns, each pair of the second conductive layers and the first conductive layers coupled to the each pair of the second conductive layers, respectively, forming electrodes of a capacitor.
Conclusion
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898