DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1 and 13.
Pending: 1-19.
Newly added: 16-19.
Response to Arguments
Applicant' s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In light of Applicant's amendment, the objection of specification title has been withdrawn.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-12 and 16-19 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the stack" in lines 4, 8, and 12. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-8, 10, 12-17 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Kim US PG Pub. 20210028184 A1.
Re: Independent Claim 1, Kim discloses a first semiconductor structure (AR1, fig. 3) comprising channel structures (CH, fig. 3) that are disposed within a gate structure and a capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) that is disposed within the stack (GST and DST, fig. 3); and a second semiconductor structure (AR2, fig. 3) that is bonded to the first semiconductor structure (AR1, fig. 3), the second semiconductor structure (AR2, fig. 3) including a peripheral circuit, wherein the stack (GST and DST, fig. 3) comprises alternately stacked sacrificial layers (SAn, fig. 3) and insulating layers (ILD, fig. 3) and wherein the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) comprises conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3) and dielectric layers (DLa/DLb, ML and adjacent ML, fig. 3) that are alternately stacked along an internal surface of a trench (H, fig. 3) penetrating the sacrificial layers (SAn, fig. 3) and insulating layers (ILD, fig. 3) of the stack (GST and DST, fig. 3).
Re: Claim 2, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: a contact plug (¶0091&¶0080) that extends through the stack (GST and DST, fig. 3), the contact plug (¶0091&¶0080) being connected to the peripheral circuit.
Re: Claim 3, Kim disclose(s) all the limitations of claim 2 on which this claim depends. Kim further discloses wherein the contact plug (¶0091&¶0080) has a height that is substantially identical with a height of the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3).
Re: Claim 4, Kim disclose(s) all the limitations of claim 2 on which this claim depends. Kim further discloses wherein the contact plug (¶0091&¶0080) has a smaller width than the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3).
Re: Claim 5, Kim disclose(s) all the limitations of claim 2 on which this claim depends. Kim further discloses a first contact via (BCT2, fig. 3) that is connected to the contact plug (¶0091&¶0080); and second contact vias (CCT1, fig. 3) that are connected to the conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3), respectively.
Re: Claim 6, Kim disclose(s) all the limitations of claim 5 on which this claim depends. Kim further discloses wherein the first contact via (BCT2, fig. 3) and the second contact vias (CCT1, fig. 3) are disposed under the stack (GST and DST, fig. 3) and have heights that are substantially identical with each other.
Re: Claim 7, Kim disclose(s) all the limitations of claim 5 on which this claim depends. Kim further discloses a first wire (BL1/BL2, fig. 1-3) that is connected to the first contact via (BCT2, fig. 3); and a second wire (L1/L2, fig. 1-3) that is connected to at least one of the second contact vias (CCT1, fig. 3).
Re: Claim 8, Kim disclose(s) all the limitations of claim 7 on which this claim depends. Kim further discloses wherein the first wire (BL1/BL2, fig. 1-3) and the second wire (L1/L2, fig. 1-3) have heights that are substantially identical with each other.
Re: Claim 10, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: a source structure (CTS, fig. 3; ¶0033) that is disposed on the gate structure, the source structure being connected to the channel structures (CH, fig. 3).
Re: Claim 12, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the peripheral circuit comprises an input and output circuit, and wherein the input and output circuit faces the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3).
Re: Claim 16, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim further discloses: wherein the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) has a tapered form.
Re: Claim 17, Kim disclose(s) all the limitations of claim 16 on which this claim depends. Kim further discloses: a width of an upper surface of the capacitor (ELa/ELb, CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) is greater than a width (since the pillar has a taper shape the top surface would have a wider width than the lower surface pillar) of a lower surface of the capacitor (CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3).
Re: Independent Claim 13, Kim discloses a stack (GST and DST, fig. 3) comprising sacrificial layers (SAn, fig. 3) and insulating layers (ILD, fig. 3) that are alternately stacked; a contact plug (¶0091&¶0080) that extends through the stack (GST and DST, fig. 3);
a first capacitor (ELa/ELb, pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) penetrating the stack (GST and DST, fig. 3), the first capacitor (ELa/ELb, pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) including first conductive layers (ELa/ELb, fig. 3, pair of CE and adjacent CE pillar, fig. 2-3) and first dielectric layers (DLa/DLb, ML and adjacent ML, fig. 3) that are alternately stacked;
a second capacitor (ELa/ELb, another pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) penetrating the stack (GST and DST, fig. 3), the second capacitor (ELa/ELb, another pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) including second conductive layers (ELa/ELb, fig. 3, another pair of CE and adjacent CE pillar, fig. 2-3) and second dielectric layers (DLa/DLb, ML and adjacent ML, fig. 3) that are alternately stacked; and an interconnection structure that connects the first capacitor (ELa/ELb, pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) and the second capacitor (ELa/ELb, another pair of CE and adjacent CE pillar with DLa/DLb, ML and adjacent ML, fig. 1-3) in parallel.
Re: Claim 14, Kim disclose(s) all the limitations of claim 13 on which this claim depends. Kim further discloses: wherein the first conductive layers (ELa/ELb, fig. 3, pair of CE and adjacent CE pillar, fig. 2-3) comprise an even first conductive layer (second row of CE as show in figure 2) and an odd first conductive layer (first row of CE as show in figure 2), and wherein the second conductive layers (ELa/ELb, fig. 3, another pair of CE and adjacent CE pillar, fig. 2-3) comprise an even second conductive layer (fourth row of CE as show in figure 2) and an odd second conductive layer (third row of CE as show in figure 2).
Re: Claim 15, Kim disclose(s) all the limitations of claim 14 on which this claim depends. Kim further discloses: wherein the interconnection structure comprises: a first wire (BL1/BL2, fig. 1-3) that is connected to the odd first conductive layer (first row of CE as show in figure 2) and the even second conductive layer (fourth row of CE as show in figure 2); and a second wire (L1/L2, fig. 1-3) that is connected to the even first conductive layer (second row of CE as show in figure 2) and the odd second conductive layer (third row of CE as show in figure 2).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11 and 19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim US PG Pub. 20210028184 A1.
Re: Claim 11, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim is silent regarding: wherein a thickness of each of the conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3) and the dielectric layers (DLa/DLb, ML and adjacent ML, fig. 3) is 300 to 600 A.
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify the conductive layers and the dielectric layers is 300 to 600 A, since such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a thinner thickness to achieve the predictable result of miniaturization the memory device thereby improve the high-density integration.
Re: Claim 19, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim is silent regarding: wherein each of the conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3) has a thickness that is substantially identical to a thickness of each of the dielectric layers (DLa/DLb, ML and adjacent ML, fig. 3).
However, thickness range it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention because, absent evidence of disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F.2d 454, 105 USPQ 223, 235 (CCPA 1955). Furthermore, the specification contains no disclosure of either the critical nature of the claimed dimensions of any unexpected results arising therefrom. Where patentability is aid to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. See In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2sd 1934, 1936 (Fed. Cir. 1990). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention was made to modify each of the conductive layers has a thickness that is substantially identical to a thickness of each of the dielectric layers since such modification would have only involved a mere change in working range which involves only routine skill in the art one would have been motivated to make such modification to make those layer to have a uniform thickness for each semiconductor layer strictly improves device leveling and electrical consistency.
Claim(s) 9 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kim US PG Pub. 20210028184 A1; Nishikawa et al., US Patent 9589981 B2.
Re: Claim 9, Kim disclose(s) all the limitations of claim 2 on which this claim depends. Kim is silent regarding: wherein the contact plug (¶0091&¶0080) and the conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3) comprise molybdenum.
Nishikawa teaches contact plug made of material molybdenum (column 11, lines 62-66).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include material molybdenum for the contact plug or conductive layers since molybdenum has very thin film thicknesses it can keeps lower resistance than other material like tungsten.
Re: Claim 18, Kim disclose(s) all the limitations of claim 1 on which this claim depends. Kim is silent regarding: wherein the conductive layers (ELa/ELb, CE and adjacent CE pillar, fig. 3) comprise molybdenum.
Nishikawa teaches conductive layers made of material molybdenum (column 11, lines 62-66).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include material molybdenum for the contact plug or conductive layers since molybdenum has very thin film thicknesses it can keeps lower resistance than other material like tungsten.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Park et al., US PG pub. 20130154055 A1”) Discloses a capacitor of a semiconductor device includes a capacitor structure configured to include electrode layers and dielectric layers alternately stacked, edge regions each stepwise patterned, and a central region disposed between the edge regions, sacrificial layers disposed within the respective electrode layers in the edge regions of the capacitor structure, and support plugs formed in the central region of the capacitor structure and configured to penetrate the electrode layers and the dielectric layers.
* (“Lu US PG pub. 20220037460 A1”) discloses a fabrication method for a double-sided capacitor. The fabrication method for the double-sided capacitor includes the following steps: providing a substrate; forming a stack structure on the substrate; forming a capacitor hole in a direction perpendicular to the substrate to penetrate the stack structure, wherein the stack structure includes sacrificial layers and supporting layers alternately stacked; forming an auxiliary layer to cover the sidewall of the capacitor hole; forming a first electrode layer to cover the surface of the auxiliary layer; removing a part of the supporting layer on the top of the stack structure; removing the sacrificial layers and the auxiliary layer simultaneously along the opening; and forming a dielectric layer covering the surface of the first electrode layer and a second electrode layer covering the surface of the dielectric layer, wherein the gap is at least filled with the dielectric layer.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/
Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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