DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on April 12th, 2026 has been entered.
Claim Status
Claims 1 and 11 have been amended. Claims 2 and 12 remain cancelled. Claims 1, 3-11 and 13-20 remain pending and are ready for examination.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, 7, 10-11, 13, 16 and 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng et al. (US Publication No. 2021/0334018 -- "Geng") in view of Grube et al. (US Publication No. 2015/0378822 – “Grube”) in further view of Costa et al. (US Publication No. 2020/0310683 -- "Costa").
Regarding claim 1, Geng teaches An integrated circuit for memory access, comprising a first memory module, a second memory module, and an access signal determining module, wherein the access signal determining module is respectively connected to the first memory module and the second memory module, and the access signal determining module comprises: (Geng paragraph [0009], According to a first aspect, a communication method is provided, where the method is applied to a computer system, the computer system includes a first subsystem and a second subsystem, a safety level of the first subsystem is higher than a safety level of the second subsystem, a central processing unit (CPU) core of the first subsystem, a CPU core of the second subsystem, and a memory access checker are integrated on a same chip. The computer system includes an interrupt controller, and the interrupt controller is shared by the first subsystem and the second subsystem. Interrupt routing configuration information stored in the interrupt controller is configured by the CPU core of the first subsystem, and the interrupt routing configuration information is used to indicate a CPU core that responds to each interrupt. The first subsystem further includes a memory access checker. The communication method further includes that the memory access checker receives a memory access request from a memory access initiator, the memory access checker determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and when a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, the memory access checker allows the memory access initiator to access the memory. A memory access signal can be sent to a plurality of different memories, based on safety levels, as seen in Geng paragraph [0015], In this application, the memory access checker is configured in a subsystem with a high safety level, and the memory of the computer system is divided based on a safety level, so as to achieve good isolation between different subsystems of the computer system, thereby preventing an exception of a subsystem from affecting normal operation of another subsystem as far as possible) an interface circuit, configured to transmit a first memory access signal of a processor accessing the first memory module to the first memory module; (Geng paragraph [0009], The communication method further includes that the memory access checker receives a memory access request from a memory access initiator, the memory access checker determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and when a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, the memory access checker allows the memory access initiator to access the memory. The access request may be sent to a first memory subsystem) and an address filtering circuit; the address filtering circuit, connected to the interface circuit, and configured to determine a target safety level corresponding to an access address of the first memory access signal; (Geng paragraph [0009], The communication method further includes that the memory access checker receives a memory access request from a memory access initiator, the memory access checker determines, based on preconfigured memory safety level division information, whether a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, and when a safety level of a memory to be accessed by the memory access initiator matches a safety level of the memory access initiator, the memory access checker allows the memory access initiator to access the memory. The memory access requests can be filtered through a memory access initiator (i.e., address filter) that checks an address for a given target safety level, also see Geng paragraph [0010], The memory access request carries a memory address to be accessed by the memory access initiator and safety level information of the memory access initiator, and the memory safety level division information is used to indicate safety levels of memories in different address segments of the computer system) and an access signal processing circuit, connected to the address filtering circuit, and configured to offset the access address of the first memory access signal in response to that the target safety level is a preset level, obtain a second memory access signal based on the offset address, and transmit the second memory access signal to the second memory module (Geng paragraphs [0086-0087], With reference to the second aspect, in some implementations of the second aspect, the configuring safety levels of the first subsystem and the second subsystem based on the safety level configuration file includes writing safety level information of an IO device into a safety level configuration and detection module corresponding to the IO device. The safety level configuration and detection module corresponding to the IO device is configured to detect the access request received by the IO device, to determine whether a safety level of a device that initiates the access request matches a safety level of the IO device. The partition manager writes the safety level information of the IO device into the IO device, so that the safety level of the IO device can be configured, and a safety level configuration and detection module of the configured IO device can check the safety level of the device that initiates the access request, thereby achieving isolation between devices of different safety levels. The memory access signal can check the security level of a first memory, and if the safety level does not meet a predetermined level, can check a second memory module for its respective security level, also see Geng paragraph [0316], Safety configuration and check for an IO device used to configure the corresponding IO device as different safety levels. After the safety level configuration is completed, address access sent by the IO device carries a safety level signal).
Geng does not teach a read channel module, a data comparison module, offset the access address of the first memory access signal in response to that the target safety level is a preset level, determine an offset address in the second memory module corresponding to the access address of the first memory access signal, obtain a second memory access signal based on the offset address; wherein addresses in the first memory module correspond to addresses in the second memory module, the preset level is a high safety level, and the first memory module and the second memory module each has a low safety level; and the read channel module, configured to read first data from the first memory module and read second data from the second memory module; and the data comparison module, configured to compare the first data with the second data, and determine a data error signal based on a comparison result.
However, Grube teaches offset the access address of the first memory access signal based on an offset correspondence between address ranges of the first memory module and the second memory module in response to that the target safety level is a preset level, obtain a second memory access signal based on the offset address (Grube paragraphs [0341-0342], The method continues at step 522 where the processing module generates an offset sub-DSN address range based on the identified sub-DSN address range and in offset function of the storage unit. For example, the processing module identifies the access function and utilizes the offset function on the identified sub-DSN address range to produce the offset sub-DSN address range. For instance, the processing module adds a pillar index of the storage unit to the sub-DSN address range to produce the offset sub-DSN address range. The method continues at step 524 of the processing module identifies a memory device associated with the offset sub-DSN address range. For example, the processing module interprets a sub-DSN address range to memory device identifier table using the offset sub-DSN address range to produce an identifier of the memory device. The method continues at step 526 where the processing module facilitates the access request using the identified memory device. For example, the processing module causes execution of the access request and generation of an access response. The offset for different memory signal access commands can be generated based on determined address ranges for the given memory areas).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng with those of Grube. Grube teaches using determined address ranges for offsetting memory access commands, which can allow for performing memory commands between different memory areas, allowing for optimizations such as memory device attribute typing (i.e., see Grube paragraph [0337], Having generated the offset sub-DSN address range, the DST execution unit identifies a memory device associated with the offset sub-DSN address range. For example, DST execution unit 2 identifies memory device 2 when the offset sub-DSN address range is a second sub-DSN address range. As such, each DST execution unit of the set of DST execution units selects memory devices with different attributes which may provide a system performance improvement from diversity of memory device attributes types (e.g., avoiding potential correlated failures)).
Geng in view of Grube does not teach a read channel module, a data comparison module, determine an offset address in the second memory module corresponding to the access address of the first memory access signal; wherein addresses in the first memory module correspond to addresses in the second memory module, the preset level is a high safety level, and the first memory module and the second memory module each has a low safety level; and the read channel module, configured to read first data from the first memory module and read second data from the second memory module; and the data comparison module, configured to compare the first data with the second data, and determine a data error signal based on a comparison result.
However, Costa teaches a read channel module, a data comparison module (Costa paragraph [0030], By way of overview, the lockstep mode system 200A has a memory dispatcher 220 for reading data from memory 240 in lockstep mode. The lockstep mode is for data requiring a high integrity level (e.g., ASIL-D). The memory dispatcher 220 duplicates the read address to read the original and duplicate data from two respective memories 240A, 240B without processing unit intervention. A memory dispatcher may serve as a read channel module, and a data comparator may perform a comparison operation, see Costa paragraph [0018], The memory dispatcher 120 comprises an address decoder 122, a processor 124, and a comparator 126) determine an offset address in the second memory module corresponding to the access address of the first memory access signal; (Costa paragraph [0012], By way of overview, the lockstep mode system 100A has a memory dispatcher 120 for writing data to a memory 140 in lockstep mode. The lockstep mode is for data requiring a high integrity level (e.g., ASIL-D). The memory dispatcher 120 duplicates the data and corresponding write address to write the original and duplicate data in two respective memories 140A, 140B without processing unit intervention. The access signal towards the first (i.e, primary) memory may be duplicated and send a corresponding access signal to the second (i.e., redundant) memory) wherein addresses in the first memory module correspond to addresses in the second memory module, the preset level is a high safety level, and the first memory module and the second memory module each has a low safety level; (Costa paragraph [0012], By way of overview, the lockstep mode system 100A has a memory dispatcher 120 for writing data to a memory 140 in lockstep mode. The lockstep mode is for data requiring a high integrity level (e.g., ASIL-D). The memory dispatcher 120 duplicates the data and corresponding write address to write the original and duplicate data in two respective memories 140A, 140B without processing unit intervention. The access signal towards the addresses may be offset to the second memory module specifically when the high preset level is used (in this case ASIL-D, the highest security level). In the event that the security level is low, the offset is not performed (in this case, ASIL-B, as seen in Costa paragraph [0010], The present disclosure is directed to a memory dispatcher for accessing a memory. The memory dispatcher has two modes—lockstep mode and full performance (non-lockstep) mode. The mode is set based on a required integrity level of a memory region to which a memory access address corresponds. The lockstep mode is for data requiring a high integrity level (e.g., ASIL-D) and provides double data storage without a processing unit accessing a memory twice. The full performance (non-lockstep) mode is for data requiring a lower integrity level (e.g., ASIL-B) and does not replicate data) the read channel module, configured to read first data from the first memory module and read second data from the second memory module; (Costa paragraph [0032], If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP. Data can be read from the first and second memories) and the data comparison module, configured to compare the first data with the second data, and determine a data error signal based on a comparison result (Costa paragraphs [0050-0051], Step 430 is comparing, by a comparator 126/226 coupled to the lockstep processor 124L/224L: the primary and redundant copies of the write data XY_A, XY_B, and the primary and redundant memory write addresses XPTO_A, XPTO_B (Sub-Step 432); or the primary and redundant copies of the read data XY_A, XY_B, and the primary and redundant memory read addresses XPTO_A, XPTO_B (Sub-Step 434). The memory dispatcher of this disclosure provides high diagnostic coverage with data replication when external memory is used for storing data at an ASIL-D integrity level. The memory dispatcher also results in increased overall computation performance because an ASIL-D computation unit may be offloaded to the memory dispatcher. An automatic comparison saves time by providing the computation unit its requested data as soon as the primary data is available, and then the computation unit can be used for subsequent tasks until and unless the comparator outputs an error signal. The first and second data can be compared to determine an error data signal).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng and Grube with those of Costa. Costa teaches specifically performing read operations from the first and second memory modules, and then performing a data comparison for determining a data error signal, which can provide increased computational performance by offloading the processing to the memory dispatcher, as well as allowing for memory module access between differing security levels (Costa paragraph [0051], The memory dispatcher of this disclosure provides high diagnostic coverage with data replication when external memory is used for storing data at an ASIL-D integrity level. The memory dispatcher also results in increased overall computation performance because an ASIL-D computation unit may be offloaded to the memory dispatcher. An automatic comparison saves time by providing the computation unit its requested data as soon as the primary data is available, and then the computation unit can be used for subsequent tasks until and unless the comparator outputs an error signal).
Claims 11 and 20 are the corresponding method and computer readable medium claims to device claim 1. They are rejected with the same references and rationale.
Regarding claim 3, Geng in view of Grube in further view of Costa teaches The integrated circuit according to claim 1, wherein the read channel module comprises: a first bus interface circuit, connected to the first memory module, and configured to receive the first data read from the first memory module, and transmit the first data to the processor and the data comparison module; (Costa paragraph [0032], If the decoded read address XPTO corresponds with a lockstep region of the memory 240, the lockstep processor 224L is configured to generate, based on the decoded read address XPTO, primary and redundant memory read addresses XPTO_A, XPTO_B. The primary data path processor 220LP is configured to generate the primary memory read address XPTO_A. The redundant data path processor 220LR is configured to generate the redundant memory read address XPTO_B in lockstep with the primary data path processor 220LP. Data can be read from the first memory and sent to a comparator, see Costa paragraph [0050], Step 430 is comparing, by a comparator 126/226 coupled to the lockstep processor 124L/224L: the primary and redundant copies of the write data XY_A, XY_B, and the primary and redundant memory write addresses XPTO_A, XPTO_B (Sub-Step 432); or the primary and redundant copies of the read data XY_A, XY_B, and the primary and redundant memory read addresses XPTO_A, XPTO_B (Sub-Step 434)) and a second bus interface circuit, connected to the second memory module, and configured to receive the second data read from the second memory module, and transmit the second data to the data comparison module (Costa paragraphs [0050-0051], Step 430 is comparing, by a comparator 126/226 coupled to the lockstep processor 124L/224L: the primary and redundant copies of the write data XY_A, XY_B, and the primary and redundant memory write addresses XPTO_A, XPTO_B (Sub-Step 432); or the primary and redundant copies of the read data XY_A, XY_B, and the primary and redundant memory read addresses XPTO_A, XPTO_B (Sub-Step 434). The memory dispatcher of this disclosure provides high diagnostic coverage with data replication when external memory is used for storing data at an ASIL-D integrity level. The memory dispatcher also results in increased overall computation performance because an ASIL-D computation unit may be offloaded to the memory dispatcher. An automatic comparison saves time by providing the computation unit its requested data as soon as the primary data is available, and then the computation unit can be used for subsequent tasks until and unless the comparator outputs an error signal. The first and second data can be compared to determine an error data signal).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng and Grube with those of Costa. Costa teaches specifically performing read operations from the first and second memory modules, and then performing a data comparison for determining a data error signal, which can provide increased computational performance by offloading the processing to the memory dispatcher (Costa paragraph [0051], The memory dispatcher of this disclosure provides high diagnostic coverage with data replication when external memory is used for storing data at an ASIL-D integrity level. The memory dispatcher also results in increased overall computation performance because an ASIL-D computation unit may be offloaded to the memory dispatcher. An automatic comparison saves time by providing the computation unit its requested data as soon as the primary data is available, and then the computation unit can be used for subsequent tasks until and unless the comparator outputs an error signal).
Claim 13 is the corresponding method claim to device claim 3. It is rejected with the same references and rationale.
Regarding claim 7, Geng in view of Grube in further view of Costa teaches The integrated circuit according to claim 1, wherein the access signal determining module further comprises: a first address register, configured to store an upper bound value of an address range corresponding to the preset level; and a second address register, configured to store a lower bound value of the address range corresponding to the preset level; (Geng paragraph [0010], The memory access request carries a memory address to be accessed by the memory access initiator and safety level information of the memory access initiator, and the memory safety level division information is used to indicate safety levels of memories in different address segments of the computer system. Each region of memory may contain the address ranges for which a given safety level is required, which can be stored in the memory, see Geng paragraphs [0099-0100], With reference to the third aspect, in some implementations of the third aspect, the receiving safety level configuration information of the first subsystem and the second subsystem, to configure safety levels of the first subsystem and the second subsystem includes receiving memory safety level division information, where the memory safety level division information is used to indicate safety levels of memories in different address segments of the computer system. The memory safety level division information is received, so as to configure the safety levels of the memories in different address segments of the computer system. Also see Geng paragraphs [0329-0330], The ARM64 platform is used as an example. The foregoing memory configuration file may be carried in a device tree source (device tree source, DTS) file. The foregoing memory configuration file may be divided into memory address ranges to be used by subsystems of different safety levels. For example, the foregoing memory configuration file may include the following configuration information: The foregoing configuration information indicates that the memories in the range of 0-0x40000000 are allocated to subsystems of the ASIL-D safety level, and the memories in the range of 0x40000000-0x80000000 are allocated to subsystems of the ASIL-B safety level) and the address filtering circuit comprises: a first comparison unit, respectively connected to the interface circuit and the first address register, and configured to compare the access address of the first memory access signal received by the interface circuit with the upper bound value in the first address register, to obtain a first comparison result; a second comparison unit, respectively connected to the interface circuit and the second address register, and configured to compare the access address of the first memory access signal received by the interface circuit with the lower bound value in the second address register, to obtain a second comparison result; (Geng paragraphs [0014-0015], Optionally, the foregoing method further includes when the safety level of the memory to be accessed by the memory access initiator does not match the safety level of the memory access initiator, disallowing the memory access initiator to access the memory. In this application, the memory access checker is configured in a subsystem with a high safety level, and the memory of the computer system is divided based on a safety level, so as to achieve good isolation between different subsystems of the computer system, thereby preventing an exception of a subsystem from affecting normal operation of another subsystem as far as possible. The memory access request can be compared with an upper and lower bound, which can correspond to a plurality of predetermined security levels, such as those in Geng paragraph [0004], If the safety risks of the systems are greater, the corresponding safety requirement levels are higher. To assess the safety levels of automobiles, the International Organization for Standardization (ISO) 26262 “Road Vehicles—Functional Safety” introduced the concept of Automotive Safety Integrity Level (ASIL) and defined four different ASILs ASIL A, ASIL B, ASIL C, and ASIL D. ASIL D is the highest safety integrity, and ASIL A is the lowest safety integrity. Also see Geng paragraph [0209]) and a determining unit, respectively connected to the first comparison unit, the second comparison unit, and the access signal processing circuit, and configured to output a safety level matching state to the access signal processing circuit based on the first comparison result and the second comparison result, wherein the safety level matching state comprises two states: the target safety level matches or does not match the preset level (Geng paragraph [0257], Write safety level information of an IO device into a safety level configuration and detection module corresponding to the IO device, where the safety level configuration and detection module corresponding to the IO device is configured to detect an access request received by the IO device, to determine whether a safety level of a device that initiates the access request matches a safety level of the IO device. The safety level is determined to meet or not meet the preset level).
Claim 16 is the corresponding method claim to device claim 7. It is rejected with the same references and rationale.
Regarding claim 10, Geng in view of Grube in further view of Costa teaches The integrated circuit according to claim 1, wherein the access signal determining module further comprises: a channel selection circuit, respectively connected to the interface circuit and the access signal processing circuit, and configured to transmit the first memory access signal and the second memory access signal through channel selection (Geng paragraph [0006], One solution is to deploy safety domain systems of different safety levels on different hardware devices by stacking a large quantity of electronic control units (ECUs) to achieve the purpose of resource isolation. Different safety domain systems communicate with each other through the Controller Area Network (CAN)/universal asynchronous receiver-transmitter (UART) low-speed bus. In this solution, it is equivalent that different safety domain systems are individually executed by different devices. Although resource isolation is achieved, a large amount of hardware stacking is required, and the communication between different safety domain systems has relatively high latency. The interface circuit and access signal processing may utilize a plurality of different channels/buses for the memory access signals).
Claim 19 is the corresponding method claim to device claim 10. It is rejected with the same references and rationale.
Claim(s) 4 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Grube in further view of Costa as applied to claim 3 above, and further in view of Oda et al. (US Publication No. 2009/0319994 – “Oda”).
Regarding claim 4, Geng in view of Grube in further view of Costa and further in view of Oda teaches The integrated circuit according to claim 3, wherein the read channel module further comprises: a first read cache unit, respectively connected to the processor, the first bus interface circuit, and the data comparison module, and configured to cache the first data received by the first bus interface circuit, and output the first data to the processor and the data comparison module; and a second read cache unit, respectively connected to the second bus interface circuit and the data comparison module, and configured to cache the second data received by the second bus interface circuit, (Oda paragraph [0012], a first processor equipped with a first cache memory having a first memory cell unit, a second processor equipped with a second cache memory having a second memory cell unit, and a bus to connect the first and second processors and the main memory, the first memory cell unit being capable of storing first tag addresses and first data in association with first index addresses, respectively, the first index addresses being configured based on address information. A first and second read cache may be used to receive and output read data via a bus interface) and output the second data to the data comparison module (Said data read from the caches may be output to a data comparison reader, see Oda paragraph [0012], a read data comparing unit configured respectively to compare the respective ones of the first and second data read from the first and second readers).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng and Grube and Costa with those of Oda. Oda teaches using a plurality of read cache units to connect the data comparison unit and transmit the read data through the interface circuit, which can provide additional speed for reading data as well as data reliability via comparison operations (Oda paragraph [0068], For example, processing of reading data corresponding to consecutive addresses in the main memory 500 from the main memory 500 and storing the data in the cache memory 300 is performed in advance. The processing enables the stored data to be read from the cache memory 300 with the miss signal as the interrupt signal. As a result, a hit rate of the cache memory 300 can be improved. The hit rate of the cache memory is a number of times of reading from the cache memory 300 divided by a number of times of reading from all memories. By improving the hit rate of the cache memory 300 in this manner, the system performance of the debugging system 10 can be improved).
Claim 14 is the corresponding method claim to device claim 4. It is rejected with the same references and rationale.
Claim(s) 5 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Grube in further view of Costa in further view of Oda as applied to claim 4 above, and further in view of Benisty (US Publication No. 2023/0113376 -- "Benisty").
Regarding claim 5, Geng in view of Grube in further view of Costa and further in view of Oda and further in view of Benisty teaches The integrated circuit according to claim 4, wherein the data comparison module comprises an exclusive-OR circuit unit, and the exclusive-OR circuit unit comprises a first input end, a second input end, and an output end; the first input end is connected to the first read cache unit, and is configured to input the first data; the second input end is connected to the second read cache unit, and is configured to input the second data; and the output end is connected to an error processing module, and is configured to output the data error signal to the error processing module (Benisty paragraph [0036], For a compare command, the host device places a compare command in the submission queue, and the data storage device then proceeds to perform the compare operation. FIG. 3 is a schematic illustration 300 of a compare command data flow according to one embodiment. The controller 304 retrieves the data to be compared from the host device 302 and places the data in the write buffer 308. The controller 304 also retrieves the read data from the memory device 306 and places the read data in the read buffer 310. The data from the write buffer 308 and the read buffer 310 is fed to the comparer 312 that compares the data, such as by performing an XOR comparison. The results of the compare command are delivered back to the host device 302. A comparator may be used to receive two different inputs from a buffer, and provide an XOR comparison, then output the result).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng, Grube, Costa and Oda with those of Benisty. Benisty teaches using an XOR comparison received from a buffer, which can provide more efficient error detection and subsequent correction (Benisty paragraph [0038], It has surprisingly been found that performance of a compare command execution can be increased in order to be aligned with enterprise SSD requirements. Host data transfer and memory device data transfer can be synchronized. More specifically, when a chunk of data is available from the memory device, the corresponding relevant chunk of data is fetched from the host device. The chunk of data that is retrieved may be out of order from the host data order, but it is contemplated that the relevant data from the host may be retrieved in order. Regardless, while the host data is retrieved, the chunk of data retrieved from the memory device is decoded in parallel. In so doing, the decoding of the chunk of data will complete at substantially the same time as the relevant data is retrieved. As the data is retrieved in chunks, fewer buffer storage space (or even fewer buffers) is necessary. Even though fewer buffers or buffer space are needed, performance does not suffer because the data is processed in chunks rather than waiting for all of the data to arrive prior to performing the compare operation. Furthermore, if the compare command fails for any chunk of data, then the entire compare command fails. Thus, the compare command failure can be determined much faster than if all the data is first retrieved).
Claim 15 is the corresponding method claim to device claim 5. It is rejected with the same references and rationale.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Grube in further view of Costa as applied to claim 3 above, and further in view of Jeong (US Publication No. 2024/0004411 -- "Jeong").
Regarding claim 6, Geng in view of Grube in further view of Costa and further in view of Jeong teaches The integrated circuit according to claim 3, wherein the read channel module further comprises an OR logic circuit; the first bus interface circuit is further connected to the OR logic circuit, and is further configured to receive a backpressure signal of a bus, and output a first preparation signal to the OR logic circuit; the second bus interface circuit is further connected to the OR logic circuit, and is further configured to receive the backpressure signal of the bus, and output a second preparation signal to the OR logic circuit; and the OR logic circuit is configured to output a third preparation signal to the processor in response to the first preparation signal and/or the second preparation signal, wherein the third preparation signal is used to notify the processor not to initiate a read-write operation (Jeong paragraph [0046], The OR gate may output the active mode enable signal VDC_EN of the high state when a signal input from the first AND gate 1112 is in the high state, the inverted ready/busy signal according to ready/busy line RB #of the high state indicating that the memory device is in operation is input, or the test mode signal TESTMODE indicating that the memory device is in a test mode is input. The OR gate may output the active mode enable signal VDC_EN of the low state when the signal input from the first AND gate 1112 is in the low state, the inverted ready/busy signal according to ready/busy line RB #of the low state indicating that the memory device is in the ready state is input, or the memory device does not enter the test mode. An "OR" logic gate may receive a plurality of preparation signals/inputs, and output a ready/busy signal based on said result to implement an operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng and Grube and Costa with those of Jeong. Jeong teaches using an OR logic circuit for indicating a ready/busy state, which is a well-known technique in the art to add specificity to the function of the device to ensure that execution for an operation may only occur when a set of bits are at a predetermined level (Jeong paragraph [0034], The memory device 1000 may output an outside state signal of a ready state or a busy state to the external device through the ready/busy line RB #. The outside state signal of the ready state may be a state in which the command, the address, or the data may be input from the external device. The outside state signal of the ready state may be a logic high. The outside state signal of the busy state may be a state in which the command, the address, or the data might not be input from the external device. The outside state signal of the busy state may be a logic low. That is, when the memory device 1000 is in the ready state, the memory device 1000 may output a signal of an inverted low state through the ready/busy line RB #. Similarly, when the memory device 1000 is in the busy state, the memory device 1000 may output a signal of an inverted high state through the ready/busy line RB #. In an embodiment, the external device, for example, may be a memory controller that controls the memory device 1000. In an embodiment, the external device, for example, may be a host. In an embodiment, the external device, for example may be any device external to the memory device 1000).
Claim(s) 8-9 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Grube in further view of Costa as applied to claim 1 above, and further in view of Fielding et al. (US Publication No. 2022/0318138 -- "Fielding").
Regarding claim 8, Geng in view of Grube in further view of Costa in further view of Fielding teaches The integrated circuit according to claim 7, wherein the access signal processing circuit comprises: a finite-state machine, connected to the determining unit, and configured to add the access address of the first memory access signal to preset offset information to obtain the offset address (Fielding paragraph [0122], In embodiments in which respective distinct regions of memory locations are allocated to respective sets of adjacent blocks of data elements, the distinct region of memory locations may be accessed in any desired and suitable way. In embodiments, the distinct region of memory locations may be accessed using a memory address or memory offset for the distinct region of memory locations in question. As discussed above, the relevant memory address or memory offset may be indicated in a header for the encoded block of data. The memory access request address may be offset in order to access a different memory region based on said offset) when the safety level matching state is that the target safety level matches the preset level, obtain the second memory access signal based on the offset address, and transmit the second memory access signal to the second memory module (Geng paragraphs [0086-0087], With reference to the second aspect, in some implementations of the second aspect, the configuring safety levels of the first subsystem and the second subsystem based on the safety level configuration file includes writing safety level information of an IO device into a safety level configuration and detection module corresponding to the IO device. The safety level configuration and detection module corresponding to the IO device is configured to detect the access request received by the IO device, to determine whether a safety level of a device that initiates the access request matches a safety level of the IO device. The partition manager writes the safety level information of the IO device into the IO device, so that the safety level of the IO device can be configured, and a safety level configuration and detection module of the configured IO device can check the safety level of the device that initiates the access request, thereby achieving isolation between devices of different safety levels. The memory access signal can check the security level of a first memory, and if the safety level does not meet a predetermined level, can check a second memory module for its respective security level, also see Geng paragraph [0316], Safety configuration and check for an IO device used to configure the corresponding IO device as different safety levels. After the safety level configuration is completed, address access sent by the IO device carries a safety level signal).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng, Grube and Costa with those of Fielding. Fielding teaches offsetting the address for a first memory access request to be used for obtaining a second memory access request, which is a well-known feature of memory that can improve the performance of access requests by using a more efficient offset indicator (Fielding paragraph [0076], Truncating the memory address values in this way means that there will be fewer bits available for storing the memory address (e.g. offset) value itself, which reduces the memory address range that can be indicated using the memory address value. However, this is compensated for by the much larger increase in memory address range afforded by the technology described herein).
Claim 17 is the corresponding method claim to device claim 8. It is rejected with the same references and rationale.
Regarding claim 9, Geng in view of Grube in further view of Costa in further view of Fielding teaches The integrated circuit according to claim 8, wherein the access signal processing circuit further comprises: a first register, connected to the finite-state machine, and configured to store the preset offset information (Fielding paragraph [0036], To address this, according to the technology described herein, a modifier value is included into the header together with the memory address value which modifier value represents a ‘modifier’ that is to be applied to the memory address (e.g. offset) value when determining the memory location. As will be explained further below, the modifier can thus be applied to the memory address value appropriately to modify, e.g., and in an embodiment, increase, the value that is represented by the memory address value itself, to thereby extend the memory address range that can be indicated by the header. The offset information may be a preset modifier value which is stored and can be applied to the initial memory address access request).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng, Grube and Costa with those of Fielding. Fielding teaches offsetting the address for a first memory access request to be used for obtaining a second memory access request, which is a well-known feature of memory that can improve the performance of access requests by using a more efficient offset indicator (Fielding paragraph [0076], Truncating the memory address values in this way means that there will be fewer bits available for storing the memory address (e.g. offset) value itself, which reduces the memory address range that can be indicated using the memory address value. However, this is compensated for by the much larger increase in memory address range afforded by the technology described herein).
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Geng in view of Grube in further view of Costa as applied to claim 11 above, and further in view of Jeong (US Publication No. 2024/0004411 -- "Jeong").
Regarding claim 18, Geng in view of Grube in further view of Costa and further in view of Jeong teaches The processing method for memory access according to claim 11, wherein the processing method further comprises: receiving a backpressure signal of a bus, and outputting a third preparation signal to the processor in response to the backpressure signal, wherein the third preparation signal is used to notify the processor not to initiate a read-write operation (Jeong paragraph [0046], The OR gate may output the active mode enable signal VDC_EN of the high state when a signal input from the first AND gate 1112 is in the high state, the inverted ready/busy signal according to ready/busy line RB #of the high state indicating that the memory device is in operation is input, or the test mode signal TESTMODE indicating that the memory device is in a test mode is input. The OR gate may output the active mode enable signal VDC_EN of the low state when the signal input from the first AND gate 1112 is in the low state, the inverted ready/busy signal according to ready/busy line RB #of the low state indicating that the memory device is in the ready state is input, or the memory device does not enter the test mode. An "OR" logic gate may receive a plurality of preparation signals/inputs, and output a ready/busy signal based on said result to implement an operation).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to combine the teachings of Geng and Grube and Costa with those of Jeong. Jeong teaches using an OR logic circuit for indicating a ready/busy state, which is a well-known technique in the art to add specificity to the function of the device to ensure that execution for an operation may only occur when a set of bits are at a predetermined level (Jeong paragraph [0034], The memory device 1000 may output an outside state signal of a ready state or a busy state to the external device through the ready/busy line RB #. The outside state signal of the ready state may be a state in which the command, the address, or the data may be input from the external device. The outside state signal of the ready state may be a logic high. The outside state signal of the busy state may be a state in which the command, the address, or the data might not be input from the external device. The outside state signal of the busy state may be a logic low. That is, when the memory device 1000 is in the ready state, the memory device 1000 may output a signal of an inverted low state through the ready/busy line RB #. Similarly, when the memory device 1000 is in the busy state, the memory device 1000 may output a signal of an inverted high state through the ready/busy line RB #. In an embodiment, the external device, for example, may be a memory controller that controls the memory device 1000. In an embodiment, the external device, for example, may be a host. In an embodiment, the external device, for example may be any device external to the memory device 1000).
Response to Arguments
Applicant's arguments filed March 6th, 2026 with respect to the 35 U.S.C. 103 Rejection have been fully considered but they are not persuasive.
Applicant argues:
“Costa discloses that the processor 124 in the memory dispatcher 120 includes a lockstep processor 124L and a non-lockstep processor 124NL. After the address decoder 122 decodes the write address XPTO, if the decoded write address corresponds with a lockstep region of the memory 140, the lockstep processor 124L writes data to the memory 140A and the memory 140B; if the decoded write address corresponds with a non-lockstep region of the memory 140, the non- lockstep processor 124NL writes data to the memory 140A and the memory 140B. That is to say, the solution of Costa selects different processors for writing data based on the write address, and the technical effect achieved is implementing two scheduling modes lockstep and non- lockstep. It can be seen that Costa does not disclose distinguishing technical feature 1, and the technical effect of the technical features already disclosed in Costa is different from the technical effect of distinguishing technical feature 1.
Since Costa does not disclose distinguishing technical feature 1, and the technical effect produced by Costa is different from that produced by distinguishing technical feature 1, Costa does not constitute a technical teaching for combination with Geng and Grube.”
The examiner respectfully disagrees. In light of the applicant’s amendments to independent claims 1 and 11, the examiner has applied new cited portions of the Costa reference to disclose the claimed subject matter. Specifically, Costa has been added to disclose the concept of utilizing two differing security levels (in this case, ASIL-D and ASIL-B) to access two separate memory modules (primary and redundant). In this case, when the security level is high, the access address is offset, and the data is duplicated and sent to the corresponding address location of the redundant memory. Regarding the combination of references, Costa teaches the concept of utilizing differing memories for differing security levels, which allows additional flexibility for the memory, specifically the memory access initiator which can access multiple memory levels described in the primary reference Geng and can provide additional security/reliability (i.e., see Costa paragraph [0034], The comparator 226 is configured to compare the primary and redundant copies of the read data XY_A, XY_B. The comparator 226 is also configured to compare the primary and redundant memory read addresses XPTO_A, XPTO_B. If the primary (XPTO_A) and redundant (XPTO_B) memory read addresses differ from what they should be, or the primary (XY_A) and redundant (XY_B) copies of the read data differ, the comparator 116 is configured to generate an error signal. This means that the MCU cannot be trusted and should be shut down or enter a safe state within a certain period of time. The comparator 226 may be further configured to synchronize the received primary read data XY_A with the corresponding received redundant read data XY_B). In light of the above rationale, the applicant’s arguments are not determined to be persuasive, and the 35 USC 103 Rejection is maintained.
Conclusion
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/J.C.K./Examiner, Art Unit 2133
/BRIAN R PEUGH/Primary Examiner, Art Unit 2133
