DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over unpatentable over Lee et al. (hereinafter “Lee”), US Pub. No. 2023/0019182, in view of Xi, US Pub. No. 2021/0335303.
Regarding claim 1, Lee teaches a display device (figs. 2, 7A-7D), comprising: a lower substrate including an active area and a non-active area, and being stretchable (figs. 2, 7A-7D, stretchable micro-LED, display includes a pixel array region (active area) and surrounding regions for interconnection (non-active area)); a pattern layer disposed on the active area of the lower substrate, and including a plurality of first plate patterns and a plurality of first line patterns (figs. 4A-4C, 7A-7D, element 31 correspond to plates, element 15 correspond to line patterns); a plurality of pixels disposed on each of the plurality of first plate patterns (figs. 7A-7D, micro-LEDs disposed on element 31); and a plurality of connection lines disposed on the plurality of first line patterns, and configured to connect the plurality of pixels (figs. 4A-4C, 7A-7D, interconnects 15).
Lee fails to explicitly teach a gate driver including a plurality of stages to supply a gate signal to the plurality of pixels through the plurality of connection lines, wherein the gate driver is disposed on the active area of the lower substrate.
However, in the same field of endeavor, Xi teaches a gate driver on array (GOA) circuit including a plurality of stages (shift-register stages with TFTs) configured to supply gate signals to pixels (see fig. 1) wherein the GOA circuit is integrated directly on the array substrate (display panel).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify the stretchable display device of Lee to include the gate driver on array circuit of Xi. As such, a person having ordinary skill in the art would appreciate the motivation for doing so would have been to improve integration, reduce bezel size and electrical performance.
Regarding claim 2, Lee and Xi teach wherein the pattern layer further includes a plurality of second plate patterns and a plurality of second line patterns, and each of the plurality of stages includes at least one transistor and at least one capacitor disposed on the plurality of second plate patterns (Lee, figs. 7A-7D, multiple device elements 31 and interconnects 15; Xi, fig. 1, transistors T(n) and capacitors in bootstrap module 700).
Regarding claim 3, Lee and Xi teach further comprising: a plurality of first connection signal lines disposed on the plurality of second line patterns and the plurality of second plate patterns; a plurality of second connection signal lines disposed on the plurality of second plate patterns; and a plurality of third connection signal lines disposed on the plurality of second plate patterns (Lee, figs. 7A-7D, multiple interconnect lines 15; Xi, fig. 1, multiple independent signal paths, multiple internal nodes and signal paths within GOA stages).
Regarding claim 4, Lee and Xi teach wherein each of the plurality of first connection signal lines is electrically connected to at least one of the plurality of second connection signal lines and at least one of the plurality of third connection signal lines on the plurality of second place patterns (Lee, figs. 4A-4C, 7A-7D, Xi, fig. 1; it would have been obvious for the connection signal lines to be electrically connected to one another as required for signal transmission and circuit operation as shown in Xi).
Regarding claim 5, Xi teaches wherein the plurality of second connection signal lines and the plurality of third connection signal lines are electrically connected to at least one transistor and at least one capacitor included in the gate driver (fig. 1; it would have been obvious for connection signal lines to be electrically connected to transistors and capacitors within the gate driver circuit for circuit operation as shown in Xi).
Regarding 6, Xi teaches wherein a power voltage and a signal which drive the gate driver are transmitted to the plurality of first connection signal lines (fig. 1, CK(n), Vss).
Regarding claim 7, it would have been obvious to one or ordinary skill in the art to implement the gate driver stage using a particular arrangement of transistors and capacitors, as recited, as these variations represent routine design choices when implementing gate driver circuits.
Regarding claim 8, Lee teaches wherein the plurality of pixels include: first to fourth pixels disposed in a first row and sequentially disposed along first to fourth columns; and fifth to eighth pixels disposed in a second row adjacent to the first row and sequentially disposed along the first to fourth columns (figs. 4A-4C, 7A-7D pixel array).
Regarding claim 9, Lee and Xi teach wherein the first transistor is disposed on a second plate pattern disposed in the first row and disposed between the second column and the third column, among the plurality of second plate patterns, and the third and eighth transistors are disposed on a second plate pattern disposed in the second column and disposed between the first row and the second row, among the plurality of second plate patterns (Lee, figs. 4A-4C, 7A-7D, Xi, fig. 1; it would have been obvious to position the transistors at various locations within the substrate, including between rows and columns as recited. Such placement would be routine design choice in circuit arrangement on a display panel).
Regarding claim 10, Lee and Xi teach wherein the fourth transistor is disposed on a second plate pattern disposed in the first column and disposed between the first row and the second row, among the plurality of second plate patterns, and the fifth transistor is disposed on a second plate pattern disposed in the first row and disposed between the first column and the second column, among the plurality of second plate patterns (Lee, figs. 4A-4C, 7A-7D, Xi, fig. 1; the specific placement of the fourth and fifth transistor within particular rows and columns of the substrate represents a matter of layout design and obvious design choice since the placement does not result in any unexpected functional difference).
Regarding claim 11, Lee and Xi teach wherein the sixth transistor and the first capacitor are disposed on a second plate pattern disposed in the second row and disposed between the third column and the fourth column, among the plurality of second plate patterns, and the seventh transistor and the second capacitor are disposed on a second plate pattern disposed in the second row and disposed between the first column and the second column, among the plurality of second plate patterns (Lee teaches patterned regions in elements 31 and the grid structure, Xi teaches multiple transistors and capacitors all formed on the substrate shown in figs. 1-3; the specific placement of the sixth and seventh transistors and the first and second capacitors within particular rows and columns of the substrate represent layout design that would have been within the ordinary skill of a circuit designer).
Regarding claim 12, it has similar structural layout limitations to those of claim 7 and is rejected on the same grounds presented above.
Regarding claim 13, it has similar structural layout limitations to those of claim 8 and is rejected on the same grounds presented above.
Regarding claim 14, it has similar structural layout limitations to those of claim 9 and is rejected on the same grounds presented above.
Regarding claim 15, it has similar structural layout limitations to those of claim 10 and is rejected on the same grounds presented above.
Regarding claim 16, it has similar structural layout limitations to those of claim 11 and is rejected on the same grounds presented above.
Regarding claim 17, it has similar structural layout limitations to those of claim 11 and is rejected on the same grounds presented above.
Regarding claim 18, it has similar structural layout limitations to those of claim 9 and is rejected on the same grounds presented above.
Regarding claim 19, Lee teaches wherein the plurality of first plate patterns do not overlap the plurality of second plate patterns (figs. 7A-7D, elements 31).
Regarding claim 20, Lee teaches wherein the plurality of connection lines and the plurality of first connection signal lines include a same material (figs. 7A-7D, stretchable interconnects 15).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Wang et al. (US Pub. No. 2024/0221850) teaches a gate on array shift register driving method for a display device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH B LEE JR whose telephone number is (571)270-3147. The examiner can normally be reached Mon - Fri 9am-5pm.
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/KENNETH B LEE JR/Primary Examiner, Art Unit 2625
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