DETAILED ACTION
Status of the Claims
1. This action is in response to the application filed on September 13, 2023.
2. Claims 1-20 are currently pending and have been examined.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Terminal Disclaimer
4. Examiner asserts that a Terminal Disclaimer is warranted to the instant application 18/367,686 and US Patent 11,798,078 (formerly Application 17/169,670) sharing the same inventive entity and claim language which would otherwise result in a double patenting rejection.
Drawings
5. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference characters "2202" and "2214" have both been used to designate an order book allocator, which may also be referred to as an order router and/or balancer. (See Applicant Spec para 291, 294 and 299, Figures 22-23)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
6. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “2202” has been used to designate both a high performance order book controller and an order book allocator, which may also be referred to as an order router and/or balancer. (See Applicant Spec paras 291. 294 and 299 and Figures 22-23)
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation – Broadest Reasonable Interpretation
7. In determining patentability of an invention over the prior art, all claim limitations have been considered and interpreted using the “broadest reasonable interpretation consistent with the specification during the examination of a patent application since the applicant may then amend his claims.” See In re Prater and Wei, 162 USPQ 541, 550 (CCPA 1969); MPEP § 2111. Applicant always has the opportunity to amend the claims during prosecution, and broad interpretation by the examiner reduces the possibility that the claim, once issued, will be interpreted more broadly than is justified. See In re Prater, 162 USPQ 541, 550-51 (CCPA 1969); MPEP § 2111. Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 26 USPQ2d 1057 (Fed. Cir. 1993). See also MPEP 2173.05(q) All claim limitations have been considered. Additionally, all words in the claims have been considered in judging the patentability of the claims against the prior art. See MPEP 2143.03.
Claim limitations that contain statement(s) such as “if, may, might, can, could”, are treated as containing optional language. As matter of linguistic precision, optional claim elements do not narrow claim limitations, since they can always be omitted.
Claim limitations that contain statement(s) such as “wherein, whereby”, that fail to further define the steps or acts to be performed in method claims or the discrete physical structure required of system claims.
Similarly, a method step exercised or triggered upon the satisfaction of a condition, where there remains the possibility that the condition was not satisfied under the broadest reasonable interpretation, is an optional claim limitation. see MPEP § 2103(I)(C); In re Johnson, 77 USPQ2d 1788 (Fed Cir 2006). As the Applicant does not address what happens should the optional claim limitations fail, Examiner assumes that nothing happens (i.e. the method stops). An alternate interpretation is that merely the claim limitations based upon the condition are not triggered or performed.
The subject matter of a properly construed claim is defined by the terms that limit its scope. It is this subject matter that must be examined.
As a general matter, grammar and the plain meaning of terms as understood by one having ordinary skill in the art used in a claim will dictate whether, and to what extent, the language limits the claim scope. see MPEP §2013(I)(C). Language that suggests or makes a feature or step optional but does not require that feature or step does not limit the scope of a claim under the broadest reasonable claim interpretation. see MPEP §2013(I)(C).
Claim scope is not limited by claim language that suggests or makes optional but does not require steps to be performed, or by claim language that does not limit a claim to a particular structure. In addition, when a claim requires selection of an element from a list of alternatives, the prior art teaches the element if one of the alternatives is taught by the prior art. See, e.g., Fresenius USA, Inc. v. Baxter Int’l, Inc., 582 F.3d 1288, 1298 (Fed. Cir. 2009). See MPEP 2111.04, 2143.03.
Language in a method or system claim that states only the intended use or intended result, but does not result in a manipulative difference in the steps of the method claim nor a structural difference between the system claim and the prior art, fails to distinguish the claims from the prior art. In other words, if the prior art structure is capable of performing the intended use, then it meets the claim.
The following types of claim language may raise a question as to its limiting effect (this list is not exhaustive):
Statements of intended use or field of use, including statements of purpose or intended use in the preamble (MPEP 2111.02);
Clauses such as “adapted to”, “adapted for”, “wherein”, and “whereby” (MPEP 2111.04)
Contingent limitations (MPEP 2111.04)
Printed matter (MPEP 2111.05) and
Functional language associated with a claim term (MPEP 2181)
Examiner notes that during examination, “claims … are to be given their broadest reasonable interpretation consistent with the specification, and … claim language should be read in light of the specification as it would be interpreted by one of ordinary skill in the art.” See In re Bond, 15 USPQ 1566, 1568 (Fed. Cir. 1990), citing In re Sneed, 218 USPQ 385, 388 (Fed. Cir. 1983). However, "in examining the specification for proper context, [the examiner] will not at any time import limitations from the specification into the claims". See CollegeNet, Inc. v. ApplyYourself, Inc., 75 USPQ2d 1733, 1738 (Fed. Cir. 2005). Construing claims broadly during prosecution is not unfair to the applicant, because the applicant has the opportunity to amend the claims to obtain more precise claim coverage. See In re Yamamoto, 222 USPQ 934, 936 (Fed. Cir. 1984), citing In re Prater, 162 USPQ 541, 550 (CCPA 1969).
As such, while all claim limitations have been considered and all words in the claims have been considered in judging the patentability of the claimed invention, the following language is interpreted as not further limiting the scope of the claimed invention.
As in Claim 1:
a memory operative to store a plurality of databases, each of which is configured to store data indicative of a result of processing, by one of a plurality of hardware match engines of a transaction processing system, of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored in the others of the plurality of databases;
automatically identify which subset of the plurality of databases stored in the memory stores the data representative of previously received but unsatisfied transaction messages for the same item, and any item related thereto, as the incoming transaction message and determine whether exclusive access to the identified subset is currently allocated to any one of the plurality of hardware match engines and:
when it has been determined that exclusive access to the identified subset is currently allocated, forward the incoming transaction message via the network to the one of the plurality of hardware match engines to which exclusive access to the identified subset is currently allocated; and
when it has been determined that exclusive access to the identified subset is not currently allocated to any of the plurality of hardware match engines, identify one hardware match engine, of the plurality of hardware match engines, to which exclusive access to none of the plurality of databases is currently allocated, allocate exclusive access to the identified subset to the identified one hardware match engine and forward the incoming transaction message thereto via the network, the identified one hardware match engine being the same or different from a hardware match engine that was previously identified responsive to a previously received incoming transaction;
wherein each of the plurality of hardware match engines is operative to process a transaction message forwarded thereto by being further operative to perform a search of only the databases allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction in the database of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as the processed transaction;
wherein the allocation logic is further operative to automatically deallocate exclusive access to those of the plurality of databases currently allocated to any of the plurality of hardware match engines when that hardware match engine has completed the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto by the allocation logic.
As in Claim 18:
store a plurality of databases, each of which is configured to store data indicative of a result of processing, by one of a plurality of hardware match engines of a transaction processing system, of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored in the others of the plurality of databases;
identify, automatically responsive to receipt of each of the plurality of incoming transaction messages received by the transaction receiver via the network, each for one of the plurality of items and prior to forwarding each incoming transaction message to one of the plurality of hardware match engines, which subset of the plurality of databases stored in the memory stores the data representative of previously received but unsatisfied transaction messages for the same item, and any item related thereto, as the incoming transaction message and determine whether exclusive access to the identified subset is currently allocated to any one of the plurality of hardware match engines and:
when it has been determined that exclusive access to the identified subset is currently allocated, forward the incoming transaction message via the network to the one of the plurality of hardware match engines to which exclusive access to the identified subset is currently allocated; and
when it has been determined that exclusive access to the identified subset is not currently allocated to any of the plurality of hardware match engines, identify one hardware match engine, of the plurality of hardware match engines, to which exclusive access to none of the plurality of databases is currently allocated, allocate exclusive access to the identified subset to the identified one hardware match engine and forward the incoming transaction message thereto via the network, the identified one hardware match engine being the same or different from a hardware match engine that was previously identified responsive to a previously received incoming transaction;
wherein each of the plurality of hardware match engines is operative to process a transaction message forwarded thereto by being further operative to perform a search of only the databases allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction in the database of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as the processed transaction;
wherein the order book allocator is further configured to automatically deallocate exclusive access to those of the plurality of databases currently allocated to any of the plurality of hardware match engines when that hardware match engine has completed the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto by the allocation logic.
As in Claim 19:
storing, in a memory, a plurality of databases, each of which is configured to store data indicative of a result of processing, by one of a plurality of hardware match engines of a transaction processing system, of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored in the others of the plurality of databases;
identifying, automatically by allocation logic external to the plurality of match engines, responsive to receipt of each of the plurality of incoming transaction messages received by the transaction receiver via the network, each for one of the plurality of items and prior to forwarding each incoming transaction message to one of the plurality of hardware match engines:
wherein each of the plurality of hardware match engines is operative to process a transaction message forwarded thereto by being further operative to perform a search of only the databases allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction in the database of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as to the processed transaction;
As in Claim 3:
wherein the allocation logic further maintains a data structure which stores data representative of which items of the plurality of items have at least one component item in common.
As in Claim 4:
wherein the data structure further stores the locations in the memory in which each of the plurality of databases is stored.
As in Claim 10:
wherein the plurality of hardware match engines includes a minimum number of hardware match engines such that an unallocated hardware match engine is always available to have forwarded thereto an incoming transaction message associated with an unallocated database.
As in Claim 12:
wherein the allocation logic is further configured to detect an update to the stored data in one of the plurality of memory portions by the hardware match engine associated therewith and cause the update to be accessible by the others of the plurality of hardware match engines.
As in Claim 14:
further comprising an implicator coupled with the memory, the plurality of hardware match engines and the allocation logic, and operative to, when the processed transaction remains unsatisfied, identify at least one previously received but unsatisfied transaction message for an item related to the item of the processed transaction and generate a synthetic order therefore and submit the synthetic order to the transaction processing system.
As in Claim 16:
wherein the allocation logic is further operative to forward an incoming transaction message to one of the plurality of hardware match engines based on available processing capacity of each of the plurality of hardware match engines, the one of the plurality of hardware match engines being the same engine to which a prior incoming transaction message for the same item as the incoming transaction message was forwarded, or a combination thereof.
As in Claim 17:
wherein the allocation logic is operative to facilitate access to the identified subset by providing the data representative thereof to the particular hardware match engine for use thereby and retrieving the data representative of the identified subset from the hardware match engine subsequent to the completion of the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto by the allocation logic.
Applicant has recited a “transaction receiver”. The term is at least defined by the Applicant’s specification and drawing as follows:
“The system 200 includes a transaction receiver 210, e.g., an orderer as described above, which may be implemented as one or more logic components such as on an FPGA which may include a memory or reconfigurable component to store logic and processing component to execute the stored logic…” (See Applicant Specification para 126)
“The system 400 includes a transaction receiver 402, which may be implemented as one or more logic components of an FPGA, such as the same FPGA in which the orderer 210 and decider 212 are implemented as described above, or otherwise coupled therewith, such as via the network device backplane. Alternatively, the transaction receiver 402 may be implemented as logic, such as computer program logic, stored in a memory and executable by a processor coupled therewith to cause the processor to act as described.” (See Applicant Specification para 152)
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It appears that the recited “transaction receiver” (depicted as Orderer 210) is being recited as a logic component or computer program logic, and thus software, and will be interpreted as such for purposes of examination.
Applicant has recited an “order book allocator”. The term is at least defined by the Applicant’s specification and drawing(s) as follows:
“In one embodiment, the set of previously received but unsatisfied orders further may further include, or otherwise may be subdivided into one more financial instrument subsets, each financial subset, e.g., order book, comprising those previously received orders of the set which are for a transaction for the same financial instrument of the plurality of financial instruments, wherein the order book allocator 2202 is further operative to determine the subset of the set of previously received but unsatisfied orders by identifying those financial instrument subsets associated with financial instruments having at least one component thereof, e.g., are interdependent, in common with each other and the financial instrument of the incoming order. In this way all interdependent order books may be allocated to the particular selected match engine 2206 which, as will be described above and further below, may facilitation implication. For example, in one embodiment, each of the plurality of match engines 2206 may be further operative to attempt to identify an implied match for the incoming order among the orders of the allocated subset for financial instruments, described below, which are not identical to the financial instrument of the incoming order. (See Applicant Specification para 288)
“The system 2200 further includes an order book allocator 2202, which may also be referred to as an order router and/or balancer and which may be implemented as one or more logic components of an FPGA, such as the same FPGA in which the orderer 210 and decider 212 are implemented as described above, or otherwise coupled therewith, such as via the network device backplane. Alternatively, the order book allocator 2202 may be implemented as logic such as computer program logic, stored in a memory and executable by a processor coupled therewith to cause the processor to act as described. The order book allocator 2202 is coupled with the memory 2204 and the plurality of match engines 2206 and operative to, upon receipt of an incoming order from a market participant 204 for a transaction for a financial instrument, determine a subset of the set of previously received but unsatisfied orders each having at least one component of the associated financial instrument in common with the financial instrument of the incoming order, and determine if access to the subset has been previously allocated, e.g., accorded, provided or otherwise granted, to one of the plurality of match engines 2206, which may imply that the incoming order is related to a prior order which is still undergoing the match process, and, where access to the subset has been previously allocated to one of the plurality of match engines 2206, route, or otherwise provide, the incoming order thereto for a match attempt thereby, and wherein access to the subset has not been allocated to one of the match engines 2206, select one of the plurality of match engines 2206, allocate access to the subset to the selected match engine 2206 and route the incoming order to the selected match engine 2206 for a match attempt thereby. In one embodiment, the allocation of the subset may include transferring at least a copy of the subset to a memory 2208, e.g., a cache or other local memory, associated with the selected match engine 2206.” (See Applicant Specification para 291)
“In one embodiment, the order book allocator 2202 is operative to facilitate access to the subset by providing the data representative thereof to the particular match engine 2206 for use thereby and retrieving the data representative of the subset from the match engine 2206 subsequent to the updating thereby.” (See Applicant Specification para 292)
“In one embodiment, the order book allocator 2202 is further operative to deallocate access to the subset when the selected match engine 2206 has completed the attempt to match all incoming orders routed thereto prior to another incoming order being routed thereto.” (See Applicant Specification para 293)
“In one embodiment, the order book allocator 2202 may further maintain a data structure or database 2212, which may be a sparse matrix or array, which stores data representative of which financial instruments of the plurality of financial instruments have at least one component thereof in common with another of the financial instruments of the plurality of financial instruments, which financial instruments, and thereby which order books are interdependent. This data structure 2212 may further store the locations in the memory 2204 in which each set of the previously received but unsatisfied orders is stored, which as described above, may be subdivided logically and/or physically, by the order book.” (See Applicant Specification para 294)
“In one embodiment, the order book allocator 2202 is operative to select one of the plurality of match engines 2206 based on an availability thereof, e.g., based on a selection algorithm, such as round robin, least recently used, load balancing, etc.” (See Applicant Specification para 295)
“In one embodiment, the memory 2204 further comprises a plurality of memory portions 2208, e.g., cache or local memories, as described above, each associated with one of the plurality of match engines 2206 and capable of storing at least the data representative of the subset of the set of previously received but unsatisfied orders. The order book allocator 2202 may then be further operative to detect, e.g., via snooping or snarfing, an update to the stored data in one of the plurality of memory portions 2208 by the match engine 2206 associated therewith and cause the update to be available to the others of the plurality of match engines 2206, e.g., write back.” (See Applicant Specification para 297)
“In one embodiment, the system 2200 further includes an implicatory (not shown), such as the implicatory 1102 as was described above, coupled with the memory 2204, the plurality of match engines 2206 and the order book allocator 2202, and operative to, as described above, when a match engine 2206 is unable to match the incoming order with at least one previously received but unsatisfied order for a counter transaction for the particular financial instrument of the incoming order, identify at least one previously received but unsatisfied order for a counter transaction for a financial instrument having at least one component in common with the particular financial instrument of the incoming order, and generate a synthetic, e.g., implied, order therefore and submit the synthetic order to the electronic trading system 100 or otherwise directly to the associated match engine 2206.” (See Applicant Specification para 298)
“In one embodiment, the system 2200 further includes an order router 2214 coupled with the plurality of match engines 2206 and the order book allocator 2202 and operative to route an incoming order to one of the plurality of match engines 2206 based on available processing capacity of each of the plurality of match engines 2206, e.g., subject to a load balancing algorithm or other allocation algorithm, the one of the plurality of match engines 2206 being the same engine to which a prior incoming order for a transaction for the same financial instrument as the incoming order was routed, or a combination thereof.” (See Applicant Specification para 299)
“The operation of system 2200 includes storing, such as in a memory 2204, e.g., an order book memory, data representative of a set of previously received but unsatisfied orders, e.g., which may be grouped into order books, such as by product for which the order is for, each order being for a transaction, which may specify side (buy/sell), price and/or quantity, for at least one of the plurality of financial instruments (Block 2402).” (See Applicant Specification para 301)
“In one embodiment, the set of previously received but unsatisfied orders by identifying those financial instrument subsets associated with financial instruments having at least one component thereof, e.g., are interdependent, in common with each other and the financial instrument of the incoming order. In this way all interdependent order books may be allocated to the particular selected match engine 2206 which, as will be described above and further below, may facilitate implication. For example, in one embodiment, each of the plurality of match engines 2206 may be further operative to attempt to identify an implied match for the incoming order among the orders of the allocated subset for financial instruments, described below, which are not identical to the financial instrument of the incoming order.” (See Applicant Specification para 303)
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It appears that the recited “order book allocator” is being recited as a logic component and thus software, and will be interpreted as such for purposes of examination.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
8. Claim 18 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As currently claimed, Independent Claim 18 recites a system claim comprising an order book allocator and a memory coupled therewith and further coupled with a plurality of hardware match engines external thereto via a network coupled therebetween and a transaction receiver, followed by a recitation of “the order book allocator being configured to:” followed by a series of steps.
One of the following steps recites:
“wherein each of the plurality of hardware match engines is operative to process a transaction message forwarded thereto by being further operative to perform a search of only the databases allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction in the database of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as the processed transaction;”
It appears that Applicant is attempting to ascribe the operations of each of the plurality of hardware match engines to the order book allocator, which is not supported by the specification.
Appropriate correction is required.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
9. Claims 18-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding Claim 18, the claim recites the limitation "the allocation logic" in the last two lines of the claim. There is insufficient antecedent basis for this limitation in the claim as there is no prior recitation of allocation logic in the claim.
Regarding Claim 19, this claim recites the limitation “identifying, automatically by allocation logic external to the plurality of match engines, responsive to receipt of each of the plurality of incoming transaction messages received by the transaction receiver via the network, each for one of the plurality of items and prior to forwarding each incoming transaction message to one of the plurality of hardware match engines:”
There is unclear and/or Imperfect antecedent basis for this limitation in the claim as “the plurality of match engines” has not been referred to earlier in the claim. It is unclear if Applicant is attempting to claim another plurality of match engines or is attempting to refer to the plurality of hardware match engines recited earlier in the claim. For purposes of examination, Examiner will interpret the claim as reciting “…the plurality of hardware match engines…”, however appropriate clarification and correction is required. Dependent Claim 20 is further rejected as based on a rejected base claim.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
10. Claims 1-20 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to an abstract idea without significantly more.
ANALYSIS:
STEP 1:
Does the claimed invention fall within one of the four statutory categories of invention (process, machine, manufacture or composition matter?
Claim 1 recites a system claim. Claim 18 recites a system claim. Claim 19 recites a method claim. The claims have additional rejections as being non-statutory, however Examiner assumes Applicant will rectify the claims to properly claim the invention as within statutory categories.
STEP 2A:
Prong One: Does the Claim Recite A Judicial Exception (An Abstract Idea, Law of Nature or Natural Phenomenon)? (If Yes, Proceed to Prong Two, If No, the claim is not directed to a judicial exception and qualifies as subject matter patent eligible material)
Claim 1 recites the abstract idea of transaction processing. The idea is described by the following limitations:
store data indicative of a result of processing of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored;
receive a plurality of incoming transaction messages and forward each thereof;
responsive to receipt of each of the plurality of incoming transaction messages received, each for one of the plurality of items and prior to forwarding each incoming transaction message;
automatically identify which subset stores the data representative of previously received but unsatisfied transaction messages for the same item, and any item related thereto, as the incoming transaction message and determine whether exclusive access to the identified subset is currently allocated;
when it has been determined that exclusive access to the identified subset is currently allocated, forward the incoming transaction message to which exclusive access to the identified subset is currently allocated;
when it has been determined that exclusive access to the identified subset is not currently allocated, allocate exclusive access to the identified subset and forward the incoming transaction message thereto, the identified being the same or different from a previously identified responsive to a previously received incoming transaction;
wherein to process a transaction message forwarded thereto to perform a search of only those allocated thereto for another previously received but unsatisfied transaction stored therein, and when the processed transaction remains unsatisfied thereafter, store the processed transaction of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related to, as the processed transaction;
wherein to automatically deallocate exclusive access to those currently allocated when the completed processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto.
Claim 18 recites the abstract idea of transaction processing. The idea is described by the following limitations:
store data indicative of a result of processing of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored;
identify, automatically responsive to receipt of each of the plurality of incoming transaction messages received, each for one of the plurality of items and prior to forwarding each incoming transaction message, which subset stores the data representative of previously received but unsatisfied transaction messages for the same item and any item related thereto, as the incoming transaction message and determine whether exclusive access to the identified subset is currently allocated and:
when it has been determined that exclusive access to the identified subset is currently allocated, forward the incoming transaction message to the one to which exclusive access to the identified subset is currently allocated; and
when it has been determined that exclusive access to the identified subset is not currently allocated to any, identify one to which exclusive access to none is currently allocated, allocated exclusive access to the identified subset and forward the incoming transaction message thereto, the identified being the same or different from that that was previously identified responsive to a previously received incoming transaction;
automatically deallocated exclusive access to those currently allocated to any that has completed the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto.
Claim 19 recites the abstract idea of transaction processing. The idea is described by the following limitations:
storing data indicative of a result of processing, a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages stored;
receiving, a plurality of incoming transaction messages and forwarding each thereof;
identifying, automatically, responsive to receipt of each of the plurality of incoming transaction messages received, each for one of the plurality of items and prior to forwarding each incoming transaction message:
which subset stores the data representative of previously received but unsatisfied transaction messages for the same item, and any item related thereto, as the incoming transaction message and determining whether exclusive access to the identified subset is currently allocated and:
forwarding, when it has been determined that exclusive access to the identified subset is currently allocated, the incoming transaction message to which exclusive access to the identified subset is currently allocated; and
identifying, when it has been determined that exclusive access to the identified subset is not currently allocated, to which exclusive access to none is currently allocated, allocating exclusive access to the identified subset and forwarding the incoming transaction message thereto, being the same or different from that was previously identified responsive to a previously received incoming transaction;
wherein to process a transaction message forwarded thereto by being further operative to perform a search of only allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as to the processed transaction;
deallocating, automatically exclusive access to those currently allocated to any that has completed the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto
The abstract ideas outlined above describe fundamental economic principles or practices; commercial interactions and/or managing personal behavior or relationships or interactions between people (including following rules or instructions). (Step 2A – Prong 1: YES, the claims are abstract)
Prong Two: Does the Claim Recite Additional Elements That Integrate The Judicial Exception Into A Practical Application of the Exception? (If Yes, the claim is not directed to a judicial exception and qualifies as subject matter patent eligible material. If No, Proceed to Step 2B)
The claims do not include additional elements that integrate the judicial exception into a practical application of the exception because the claims do not provide improvements to another technology or technical field, improvements to the functioning of the computer itself, are not applying or using a judicial exception to effect a particular treatment or prophylaxis for a disease or medical condition, are not applying the judicial exception with, or by use of a particular machine, are not effecting a transformation or reduction of a particular article to a different state or thing, and are not applying the judicial exception in some other meaningful way beyond generally linking the use of the judicial exception to a particular technological environment.
Claim 1 recites a memory, a plurality of databases, a plurality of hardware match engines of a transaction processing system, a transaction receiver coupled with a network; allocation logic external to the plurality of match engines.
Claim 18 recites an order book allocator and a memory, a plurality of hardware match engines external thereto via a network, a transaction receiver, a plurality of databases of a transaction processing system, and allocation logic.
Claim 19 recites a memory, a plurality of databases, a plurality of hardware match engines of a transaction processing system, a transaction receiver coupled with a network, and allocation logic external to the plurality of match engines.
Further, the method outlines in Claim 19 does not sufficiently tie the method steps to a particular machine within the body of the claim. As such, the recitations are further failing to integrate the judicial exception into a practical application on this bsis.
In particular, the claims only recite a memory, a plurality of databases, a plurality of hardware match engines of a transaction processing system, a transaction receiver, a network, allocation logic, an order book allocator, which are recited at a high level of generality (i.e., as a generic processor performing generic computer functions) such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Accordingly, these additional elements, when considered separately and as an ordered combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea. Therefore, Claims 1 and 18-19 are directed to an abstract idea without a practical application. (Step 2A – Prong 2: No, the additional claimed elements are not integrated into a practical application)
STEP 2B: If there is an exception, determine if the claim as a whole recites significantly more than the judicial exception itself.
The courts have recognized the following computer functions as well‐understood, routine, and conventional functions when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: i) receiving or transmitting data over a network, e.g., using the Internet to gather data, Symantec, 838 F.3d at 1321, 120 USPQ2d at 1362 (utilizing an intermediary computer to forward information); TLI Communications LLC v. AV Auto. LLC, 823 F.3d 607, 610, 118 USPQ2d 1744, 1745 (Fed. Cir. 2016) (using a telephone for image transmission); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network); buySAFE, Inc. v. Google, Inc., 765 F.3d 1350, 1355, 112 USPQ2d 1093, 1096 (Fed. Cir. 2014) (computer receives and sends information over a network); but see DDR Holdings, LLC v. Hotels.com, L.P., 773 F.3d 1245, 1258, 113 USPQ2d 1097, 1106 (Fed. Cir. 2014) ("Unlike the claims in Ultramercial, the claims at issue here specify how interactions with the Internet are manipulated to yield a desired result‐‐a result that overrides the routine and conventional sequence of events ordinarily triggered by the click of a hyperlink." (emphasis added)); ii) performing repetitive calculations, Flook, 437 U.S. at 594, 198 USPQ2d at 199 (recomputing or readjusting alarm limit values); Bancorp Services v. Sun Life, 687 F.3d 1266, 1278, 103 USPQ2d 1425, 1433 (Fed. Cir. 2012) ("The computer required by some of Bancorp’s claims is employed only for its most basic function, the performance of repetitive calculations, and as such does not impose meaningful limits on the scope of those claims."); iii) electronic recordkeeping, Alice Corp., 134 S. Ct. at 2359, 110 USPQ2d at 1984 (creating and maintaining "shadow accounts"); Ultramercial, 772 F.3d at 716, 112 USPQ2d at 1755 (updating an activity log); iv) storing and retrieving information in memory, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1334, 115 USPQ2d 1681, 1701 (Fed. Cir. 2015); OIP Techs., 788 F.3d at 1363, 115 USPQ2d at 1092-93; v) electronically scanning or extracting data from a physical document, Content Extraction and Transmission, LLC v. Wells Fargo Bank, 776 F.3d 1343, 1348, 113 USPQ2d 1354, 1358 (Fed. Cir. 2014) (optical character recognition); and vi) a web browser’s back and forward button functionality, Internet Patent Corp. v. Active Network, Inc., 790 F.3d 1343, 1348, 115 USPQ2d 1414, 1418 (Fed. Cir. 2015). (MPEP §2106.05(d)(II))
This listing is not meant to imply that all computer functions are well‐understood, routine, conventional activities, or that a claim reciting a generic computer component performing a generic computer function is necessarily ineligible. Courts have held computer‐implemented processes not to be significantly more than an abstract idea (and thus ineligible) where the claim as a whole amounts to nothing more than generic computer functions merely used to implement an abstract idea, such as an idea that could be done by a human analog (i.e., by hand or by merely thinking). On the other hand, courts have held computer-implemented processes to be significantly more than an abstract idea (and thus eligible), where generic computer components are able in combination to perform functions that are not merely generic. (MPEP §2106.05(d)(II) – emphasis added)
Below are examples of other types of activity that the courts have found to be well-understood, routine, conventional activity when they are claimed in a merely generic manner (e.g., at a high level of generality) or as insignificant extra-solution activity: recording a customer’s order, Apple, Inc. v. Ameranth, Inc., 842 F.3d 1229, 1244, 120 USPQ2d 1844, 1856 (Fed. Cir. 2016); shuffling and dealing a standard deck of cards, In re Smith, 815 F.3d 816, 819, 118 USPQ2d 1245, 1247 (Fed. Cir. 2016); restricting public access to media by requiring a consumer to view an advertisement, Ultramercial, Inc. v. Hulu, LLC, 772 F.3d 709, 716-17, 112 USPQ2d 1750, 1755-56 (Fed. Cir. 2014); identifying undeliverable mail items, decoding data on those mail items, and creating output data, Return Mail, Inc. v. U.S. Postal Service, -- F.3d --, -- USPQ2d --, slip op. at 32 (Fed. Cir. August 28, 2017); presenting offers and gathering statistics, OIP Techs., 788 F.3d at 1362-63, 115 USPQ2d at 1092-93; determining an estimated outcome and setting a price, OIP Techs., 788 F.3d at 1362-63, 115 USPQ2d at 1092-93; and arranging a hierarchy of groups, sorting information, eliminating less restrictive pricing information and determining the price, Versata Dev. Group, Inc. v. SAP Am., Inc., 793 F.3d 1306, 1331, 115 USPQ2d 1681, 1699 (Fed. Cir. 2015) (MPEP 2106.05(d))
Here, the steps are receiving or transmitting data over a network (Symantec, TLI, OIP Techs – MPEP 2106.05(d)(II); storing and retrieving information in memory (Versata, OIP Techs – MPEP 2106.05(d)(II) and electronically scanning or extracting data (Content Extraction – MPEP 2106.05(d)(II)– all of which have been recognized by the courts as well-understood, routine and conventional functions.
The claims are directed to an abstract idea with additional generic computer elements that do not add meaningful limitations to the abstract idea because they require no more than a generic computer to perform generic computer functions that are well-understood, routine, and conventional activities previously known in the industry.
For the next step of the analysis, it must be determined whether the limitations present in the claims represent a patent-eligible application of the abstract idea. A claim directed to a judicial exception must be analyzed to determine whether the elements of the claim, considered both individually and as an ordered combination are sufficient to ensure that the claim as a whole amounts to significantly more than the exception itself.
For the role of a computer in a computer implemented invention to be deemed meaningful in the context of this analysis, it must involve more than performance of “well-understood, routine, [and] conventional activities previously known to the industry.” Further, “the mere recitation of a generic computer cannot transform a patent ineligible abstract idea into a patent-eligible invention.”
Applicant’s specification discloses the following:
“The electronic trading system 100 may be physically implemented with one or more mainframe, desktop or other computers, such as the computer 2500 described below with respect to Figure 25, reconfigurable logic components, network switches, gateways, routers and other communication devices operative to facilitate communications within the electronic trading system 100 and between the electronic trading system 100 and the market participants. Logically, the electronic trading system 100 implements numerous functions/functional modules, each of which, as will be described, may be implemented in software, hardware, or a combination thereof, as a single standalone component or combination of interconnected components or in combination with another function/functional module." (See Applicant Specification paragraph 109)
“Referring back to Figure 1, functions/functional modules of the electronic trading system 100 may include a user database 102, stored in a memory [sic] other storage component, e.g., see the description below with respect to Figure 25, which includes information identifying market participants, e.g., traders, brokers, etc., and other users of electronic trading system 100, such as account numbers or identifiers, user names and passwords. An account data function 104 may be provided which may process account information that may be used during the matching and trading process, such as processing trading fees or maintaining credit limits, etc. A match engine function 106, described in detail below, may be included to receive incoming transactions and access order books, such as may be stored in the order book function 110, and match incoming and resting transactions, such as bid and offer prices, and may be implemented with software that executes one or more algorithms for matching bids and offers, e.g., FIFO, pro rata, etc. A trade database 108, stored in a memory or other storage medium, may be included to store information identifying trades and descriptions of trades. In particular, a trade database may store information identifying the time that a trade took place and a contract price. An order book function 110 may be included to store resting offers to buy or sell for the various products traded on the exchanges and to compute or otherwise determine current bid and offer prices for those products. A market data function 112 may be included to collect market data and prepare the data for transmission to market participants. A risk management function 134 may be included to compute and determine a user's risk utilization in relation to the user's defined risk thresholds, i.e., implement credit controls as will be described. An order processing function 136 may be included to decompose delta based and bulk order types for processing by the order book function 110 and/or match engine function 106. A volume control function 140 may be included to, among other things, control the rate of acceptance of mass quote messages in accordance with one or more aspects of the disclosed embodiments. It will be appreciated that concurrent processing limits may be defined by or imposed separately or in combination, as was described above, on one or more of the electronic trading system 100 components, including the user database 102, the account data function 104, the match engine function 106, the trade database 108, the order book function 110, the market data function 112, the risk management function 134, the order processing function 136, or other component or function of the electronic trading system 100." (See Applicant Specification paragraph 113)
“The trading network environment shown in Figure 1 includes exemplary computer devices 114, 116, 118, 120 and 122 which depict different exemplary methods or media by which a computer device may be coupled with, either directly or indirectly, the electronic trading system 100 or by which a user may communicate, e.g., send and receive, trade or other information therewith. It will be appreciated that the types of computer devices deployed by market participants and the methods and media by which they communicate with the electronic trading system 100 is implementation dependent and may vary and that no all of the depicted computer devices and/or means/media of communication may be used and that other computer devices and/or means/media of communications, now available or later developed may be used. Each computer device, which may comprise a computer 2500 described in more detail below with respect to Figure 25, may include a central processor that controls the overall operation of the computer and a system bus that connects the central processor to one or more conventional components, such as a network card or modem. Each computer device may also include a variety of interface units and drives for reading and writing data or files and communicating with other computer devices and with the electronic trading system 100. Depending on the type of computer device, a user can interact with the computer with a keyboard, pointing device, microphone, pen device or other input device now available or later developed." (See Applicant Specification paragraph 114)
"The operations of computer devices and systems shown in Figure 1 may be controlled by computer-executable instructions stored on a non-transitory computer-readable medium. For example, the exemplary computer device 116 may include computer-executable instructions for receiving order information from a user and transmitting that order information to the electronic trading system 100. In another example, the exemplary computer device 118 may include computer-executable instructions for receiving market data from the electronic trading system 100 and displaying that information to a user." (See Applicant Specification paragraph 119)
“Of course, numerous additional servers, computers, handheld devices, personal digital assistants, telephones and other devices may also be connected to the electronic trading system 100. Moreover, one skilled in the art will appreciate that the topology shown in Figure 1 is merely an example and that the components shown in Figure 1 may include other components not shown and be connected by numerous alternate topologies." (See Applicant Specification paragraph 120)
“The electronic trading system 100, as described above, includes a match engine function 106 which may be implemented by one or more sets 206 of redundant transaction processors 208, i.e., match engines. While a single set 206 of match engines 208 will be described herein, it will be appreciated that many such sets 206 may be implemented both to improve fault tolerance through redundant operation and to increase the transaction handling capacity of the electronic trading system 100." (See Applicant Specification paragraph 122)
“Coupled with the set 206 of redundant match engines 208 via the interconnecting infrastructure is the order processing function 138 of the electronic trading system. In one embodiment, the order processing function 138 is implemented on one or more FPGA devices, i.e., by one or more logic components thereof, coupled with the network gateway device (not shown), such as via a backplane interconnect, through which incoming transactions ingress the electronic trading system 100 and outgoing messages egress the electronic trading system 100. The network gateway device is further coupled with the interconnecting infrastructure to which the set 206 of match engines 208 are also coupled. It will be appreciated that the set 206 of transaction processors may be coupled with the order processing function 138 via other means such as a dedicated interconnection there between. Further, as was discussed above, the disclosed mechanisms may be implemented at any logical and/or physical point(s) through which the relevant message traffic, and responses thereto, flows or is otherwise accessible, including one or more gateway devices, modems, the computers or terminals of one or more traders, etc." (See Applicant Specification paragraph 123)
“The system 200 also includes a plurality 206 of transaction processors 208, e.g., match engines, coupled with the transaction receiver 210, such as via the communications infrastructure 202, each of the plurality 206 of transaction processors 208 operative to receive each of the augmented financial transactions and process, e.g., apply the business logic/matching algorithm to, the received augmented financial transaction in accordance with the sequence data to determine the change in the current state of the electronic marketplace caused thereby. As was described above, the processing is irrespective of the sequence in which each of the augmented financial transactions are received from the orderer, which may be different from the relationship indicated by the sequence data and which may result in a different change in the state of the electronic marketplace.” (See Applicant Specification paragraph 127)
“In one embodiment of the system 200, each of the plurality 206 transaction processors 208 operates asynchronously with respect to the others of the plurality 206 of transaction processors 208, but, if operating properly, process the augmented financial transactions the, same, i.e., according to the sequence data and the applicable business rules. It will be appreciated that transaction processors 208 of redundant set 206 may be added or removed at will.” (See Applicant Specification paragraph 129)
“One skilled in the art will appreciate that one or more functions/modules described herein may be implemented using, among other things, a logic component such as a reconfigurable logic component, e.g., an FPGA, which may include a logical processing portion coupled with a memory portion, or as a tangible computer-readable medium comprising computer-executable instructions (e.g., executable software code) executable by a processor coupled therewith to implement the function(s). Alternatively, functions/modules may be implemented as software code, firmware code, hardware, and/or a combination of the aforementioned. For example, the functions/modules may be embodied as part of an electronic trading system 100 for financial instruments." (See Applicant Specification paragraph 312)
“Referring to Figure 25, an illustrative embodiment of a general computer system 2500 is shown. The computer system 2500 can include a set of instructions that can be executed to cause the computer system 2500 to perform any one or more of the methods or computer based functions disclosed herein. The computer system 2500 may operate as a standalone device or may be connected, e.g., using a network, to other computer systems or peripheral devices. Any of the components of the electronic trading system 100 discussed above may be a computer system 2500 or a component in the computer system 2500. The computer system 2500 may implement a match engine, margin processing, payment or clearing function on behalf of an exchange, such as the Chicago Mercantile Exchange, of which the disclosed embodiments are a component thereof." (See Applicant Specification paragraph 313)
“In a networked deployment, the computer system 2500 may operate in the capacity of a server or as a client user computer in a client-server user network environment, as a peer computer system in a peer-to-peer (or distributed) network environment or as a network device such as a switch, gateway or router. The computer system 2500 can also be implemented as or incorporated into various devices, such as a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile device, a palmtop computer, a laptop computer, a desktop computer, a communications device, a wireless telephone, a land-line telephone, a control system, a camera, a scanner, a facsimile machine, a printer, a pager, a personal trusted device, a web appliance, a network router, switch or bridge, or any other machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. In a particular embodiment, the computer system 2500 can be implemented using electronic devices that provide voice, video or data communication. Further, while a single computer system 2500 is illustrated, the term "system" shall also be taken to include any collection of systems or subsystems that individually or jointly execute a set, or multiple sets, of instructions to perform one or more computer functions." (See Applicant Specification paragraph 314)
“As illustrated in Figure 25, the computer system 2500 may include a processor 2502, e.g., a central processing unit (CPU), a graphics processing unit (GPU) or both. The processor 2502 may be a component in a variety of systems. For example, the processor 2502 may be part of a standard personal computer or workstation. The processor 2502 may be one or more general processors, digital signal processors, application specific integrated circuits, field programmable gate arrays, servers, networks, digital circuits, analog circuits, combinations thereof, or other now known or later developed devices for analyzing and processing data. The processor 2502 may implement a software program, such as code generated manually (i.e., programmed).” (See Applicant Specification paragraph 315)
“The computer system 2500 may include a memory 2504 that can communicate via a bus 2508. The memory 2504 may be a main memory, a static memory, or a dynamic memory. The memory 2504 may include, but is not limited to computer readable storage media such as various types of volatile and non-volatile storage media, including but not limited to random access memory, read only memory, programmable read-only memory, electrically programmable read-only memory, electrically erasable read-only memory, flash memory, magnetic tape or disk, optical media and the like. In one embodiment, the memory 2504 may be a memory component of a reconfigurable logic device e.g., an FPGA. In one embodiment, the memory 2504 includes a cache or random access memory for the processor 2502. In alternative embodiments, the memory 2504 is separate from the processor 2502, such as a cache memory of a processor, the system memory, or other memory. The memory 2504 may be an external storage device or database for storing data. Examples include a hard drive, compact disc ("CD"), digital video disc ("DVD"), memory card, memory stick, floppy disc, universal serial bus ("USB") memory device, or any other device operative to store data. The memory 2504 is operable to store instructions executable by the processor 2502. The functions, acts or tasks illustrated in the figures or described herein may be performed by the programmed processor 2052 executing the instructions 2512 stored in the memory 2504. The functions, acts or tasks are independent of the particular type of instructions set, storage media, processor or processing strategy and may be performed by software, hardware, integrated circuits, firm-ware, micro-code and the like, operating alone or in combination. Likewise, processing strategies may include multiprocessing, multitasking, parallel processing and the like." (See Applicant Specification paragraph 316)
Generic computer components recited as performing generic computer functions that are well-understood, routine and conventional activities amount to no more than implementing the abstract idea with a computerized system.
Looking at the limitations as an ordered combination adds nothing that is not already present when looking at the elements taken individually. There is no indication that the combination of elements improves the functioning of a computer or improves any other technology. The collective functions appear to be implemented using conventional computer systemization.
The claim(s) do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Upon reconsideration of the indicia noted under Step 2A in concert with the Step 2B considerations, the additional claim element(s) amounts to no more than mere instructions to apply the exception using generic computer components. The same analysis applies in Step 2B, i.e., mere instructions to apply an exception using a generic computer component cannot integrate a judicial exception into a practical application at Step 2A or provide an inventive concept in Step 2B. The claim does not provide an inventive concept significantly more than the abstract idea.
Accordingly, these additional elements, when considered separately and as an ordered combination, do not integrate the abstract idea into a practical application because they do not impose any meaningful limits on practicing the abstract idea.
The independent claims 1 and 18-19 are not patent eligible. (Step 2B: NO. The claims do not provide significantly more)
Dependent Claims 2-17 further define the abstract idea that is presented in the respective independent Claims 1, 18 and 19 and are further grouped as certain methods of organizing human activity and are abstract for the same reasons and basis as presented above.
Claim 3 further recites that the allocation logic further maintains a data structure. Claim 5 further recites a back channel protocol. Claim 6 further recites a RDMA protocol. Claims 7 and 8 further recite a match algorithm. Claim 13 further recites that the database allocator is implemented by a FPGA. Claim 14 further recites an implicator and the transaction processing system. Claim 15 further details that the plurality of hardware match engines comprise a set of redundant hardware match engines. In each instance, the additional elements are recited at a high level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component.
No further additional hardware components other than those found in the respective independent claims is recited, thus it is presumed that the claim is further utilizing the same generic systemization as presented above. The dependent claims do not include any additional elements that integrate the abstract idea into a practical application of the exception or are sufficient to amount to significantly more than the judicial exception when considered both individually and as an ordered combination. Therefore, the dependent claims are also directed to an abstract idea .
Thus, Claims 1-20 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claims 1-17 are rejected under 35 U.S.C. § 101 because the claimed invention is directed to non-statutory subject matter.
The preamble of Claim 1 indicate that the claims pertain to a system. However, it is unclear how the system of claim 1 functions when the "system" is only recited in its broadest sense. Specifically, there is no specific structure set forth delineating exactly what accomplishes the steps of the claim. It is unclear if applicant is seeking to claim every possible system that could perform the steps of claim 1, or if applicant is seeking to claim a specific system.
The claims recites a memory which is not instantiated on any particular hardware. The recited “one of a plurality of hardware match engines of a transaction processing system” appears to be outside of the system defined in the claim. The recitation of a “transaction receiver” and “allocation logic” are disclosed to be software, and as defined by the specification (noted above) the transaction receiver may be instantiated on an FPGA – however there is no processor upon which a FPGA (not claimed in the independent claim) could be operating on. Thus, the claims are reciting system elements that are comprising a series of logic components, which under a BRI, denotes software or a computer program. Software and computer programs are not physical "things." They are neither computer components nor statutory processes, as they are not "acts" being performed. Such claimed computer programs do not define any structural and functional interrelationships between the computer program and other claimed elements of a computer which permit the computer program's functionality to be realized. Dependent claims 2-17 are further rejected as based on a rejected base claim. Thus, Claims 1-17 are deemed to be non-statutory.
The preamble of Claim 18 indicate that the claims pertain to a system. However, it is unclear how the system of claim 1 functions when the "system" is only recited in its broadest sense. Specifically, there is no specific structure set forth delineating exactly what accomplishes the steps of the claim. It is unclear if applicant is seeking to claim every possible system that could perform the steps of claim 18, or if applicant is seeking to claim a specific system.
The claims recites a memory which is not instantiated on any particular hardware. The recited “one of a plurality of hardware match engines of a transaction processing system” appears to be outside of the system defined in the claim.
The recitation of a “transaction receiver”, “order book allocator” and “allocation logic” are disclosed to be software, and as defined by the specification (noted above) the transaction receiver and order book allocator may be instantiated on an FPGA – however there is no processor upon which a FPGA (not claimed in the independent claim) could be operating on. Thus, the claims are reciting system elements that are comprising a series of logic components, which under a BRI, denotes software or a computer program. Software and computer programs are not physical "things." They are neither computer components nor statutory processes, as they are not "acts" being performed. Such claimed computer programs do not define any structural and functional interrelationships between the computer program and other claimed elements of a computer which permit the computer program's functionality to be realized. Thus, Claim 18 is deemed to be non-statutory.
Regarding Claim 19, Examiner notes that the method of Claim 19 would also have been rejected under the earlier §101 standards based upon In re Bilski, which have been superseded by the current §101 standards based upon the Alice-Mayo test. Specifically, Claim 19 contains an insufficient recitation of a machine or transformation as the involvement of the machine.
As recited, the machine is merely nominally, insignificantly or tangentially related to the performance of the steps. Examiner notes that the only explicit reference to a machine is in the preamble of Independent Claim 1 as being “computer-implemented”.
A memory is recited, however there is no hardware upon which the memory is instantiated. The processing by one of the plurality of hardware match engines of a transaction processing system appears to be occurring outside of the bounds of the method claimed. The transaction receiver and allocation logic are defined as logic/software, however there is no processor upon which a FPGA (not claimed in the independent claim) could be operating on. Thus, the claim is reciting logic components, which are not physical things or acts being performed.
There is no direct tie between a machine and the limitations of the independent claim, nor to the subsequent dependent claims. Examiner is only noting this as §101 under the Alice-Mayo test is considered a substantially higher bar than under In re Bilski. Examiner suggests Applicant incorporate language into the body of the claim reciting the machine elements performing the recited process.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
11. Claim(s) 1-4 and 7-20 are rejected under 35 U.S.C. 103 as being unpatentable over over Boudreault et al (US PG Pub. 2014/0006243) (“Boudreault”) in view of Morano et al. (US PG Pub. 2005/0097026)
Regarding Claim 1, Boudreault discloses the following:
A system comprising:
a memory operative to store a plurality of databases, each of which is configured to store data indicative of a result of processing, by one of a plurality of hardware match engines of a transaction processing system, of a set of previously received but unsatisfied transaction messages for a subset of a plurality of items different from a subset of the plurality of items for which data indicative of the result of processing previously received but unsatisfied transaction messages is stored in the others of the plurality of databases; (See Boudreault paras 17-18, 81, 106-109)
a transaction receiver coupled with a network and with the plurality of hardware match engines and operative to receive a plurality of incoming transaction messages and forward each thereof to one of plurality of hardware match engines; (See Boudreault paras 17-19, 71-72
allocation logic external to the plurality of match engines and coupled therewith and with the transaction receiver and memory via the network, the allocation logic being operative to, responsive to receipt of each of the plurality of incoming transaction messages received by the transaction receiver via the network, each for one of the plurality of items and prior to forwarding each incoming transaction message to one of the plurality of hardware match engines: (See Boudreault paragraphs 11, 17-19, 71-72, 81-85, 93-94, 106-109, 112, 119, Claim 1 and Fig. 2)
automatically identify which subset of the plurality of databases stored in the memory stores the data representative of previously received but unsatisfied transaction messages for the same item, and any item related thereto, as the incoming transaction message and determine whether exclusive access to the identified subset is currently allocated to any one of the plurality of hardware match engines and: (See Boudreault paragraphs 11, 17-19, 71-72, 81-85, 93-94, 106-109, 112, 119, Claim 1 and Fig. 2)
when it has been determined that exclusive access to the identified subset is currently allocated, forward the incoming transaction message via the network to the one of the plurality of hardware match engines to which exclusive access to the identified subset is currently allocated; and (See Boudreault paragraphs 11, 17-19, 71-72, 81-85, 93-94, 106-109, 112, 119, Claim 1 and Fig. 2)
when it has been determined that exclusive access to the identified subset is not currently allocated to any of the plurality of hardware match engines, identify one hardware match engine, of the plurality of hardware match engines, to which exclusive access to none of the plurality of databases is currently allocated, allocate exclusive access to the identified subset to the identified one hardware match engine and forward the incoming transaction message thereto via the network, the identified one hardware match engine being the same or different from a hardware match engine that was previously identified responsive to a previously received incoming transaction; (See Boudreault paragraphs 11, 17-19, 71-72, 81-85, 93-94, 106-109, 112, 119, Claim 1 and Fig. 2)
wherein each of the plurality of hardware match engines is operative to process a transaction message forwarded thereto by being further operative to perform a search of only the databases allocated thereto for another previously received but unsatisfied transaction stored therein and, when the processed transaction remains unsatisfied thereafter, store the processed transaction in the database of the allocated subset which stores the data representative of previously received but unsatisfied transactions for the same item, or an item related thereto, as the processed transaction; (See Boudreault paras 11, 17-18, 71-72)
wherein the allocation logic is further operative to automatically deallocate exclusive access to those of the plurality of databases currently allocated to any of the plurality of hardware match engines when that hardware match engine has completed the processing of all incoming transaction messages forwarded thereto prior to another incoming transaction message being forwarded thereto by the allocation logic.
Boudreault discloses his invention as to systems and methods which match or otherwise allocate an incoming order to trade with “resting” i.e., previously received but not yet matched, orders. (See Boudreault paragraph 11) In particular, the disclosed embodiments relate to an adaptive match engine which draws upon different matching algorithms, e.g. rules which dictate how a given order should be allocated among qualifying resting orders, depending on market conditions, to improve the operation of the market. (See Boudreault paragraph 11) Boudreault further discloses that embodiments of the subject matter and functional operations disclosed may be implemented in hardware. (See Boudreault para 112 – thus match engines may be hardware)
While Boudreault discloses a match engine coupled with a memory and the claim as recited, Boudreault does not fully disclose a plurality of match engines where access to a determined subset of previously received by unsatisfied orders having at least one component in common with the incoming order determining if access to the subset has been previously allocated to one of the plurality of match engines and where it has route the incoming order thereto for a match and where the subset has not been allocated allocate access to the subset to the selected match engine or that the access is deallocated when processing has been completed of all incoming transaction messages prior to another incoming transaction message being forwarded thereto.
Morano discloses his invention as to a distributed trading system for handling a plurality of order requests, each order request comprising parameters under which a participant will buy and/or sell a futures contract. (See Morano Abstract and paragraph 18) A match engine is coupled to the messaging bus and has an interface for receiving validated order messages from a RAV (risk allocation value) component wherein the match engine implements processes for matching orders based on the order-specific criteria. (See Morano Abstract and paragraph 18) A persist component is coupled to the messaging bus and has an interface for receiving messages related to orders and trades, wherein the persist component implements processes for persistently storing information related to orders and trades. (See Morano Abstract and paragraph 18)
Morano further discloses that the invention may be implemented in a manner that supports multiple “contract clusters” or in a manner in which contract clustering is not involved. A contract cluster is essentially a group of contracts that are sufficiently related that offers to sell and bids to but the contracts within a contract cluster can be matched against each other. (See Morano paragraph 49) For example, a “contract cluster” may comprise two contracts sharing a spread or strip relationship that requires that implied markets be generated between the two markets. In some implementations, it may improve performance and efficiency to create and maintain components such as match engine 315 and persist component 317 on a contract cluster basis rather than a single instance for all contracts. (See Morano paragraph 49 – plurality of contract clusters created for related contracts to be matched to each other (plurality of match engines). When contract clustering is used, a unique identification called the cluster ID is associated with each cluster. (See Morano paragraph 49 - distinct clusters with IDs) In the particular example, each message placed in the EMA bus is tagged with the cluster ID and each component is configured to recognize a particular cluster ID and ignore messages associated with other cluster IDs. (See Morano paragraph 49 – related contracts are tagged with a cluster ID and recognized by the relevant cluster (and its match engine) if the match engine already exists and is available for that contract) Accordingly, when a new cluster is added or removed, the component configuration files are updated accordingly. (See Morano paragraph 49 – access allocated to a new cluster if one does not already exist and deallocated when removed)
The match engine will reject orders for a variety of reasons but in the case of a well-formed order, match engine passes all new orders, regardless of whether they are matched or not, to the persist component. (See Morano paragraph 54) The match engine and persist component are scaled at a contract cluster level of granularity - i.e., an instance of match engine and persist component are created for every contract cluster, rather than for every contract. (See Morano paragraphs 56-58) A match engine instance will remain alive in the system for as long as the contract cluster exists. (See Morano paragraph 58) As each new contract cluster is added, a new corresponding match engine is created and as each contract cluster rolls off the corresponding match engine is destroyed. (See Morano paragraph 58) When a contract cluster is added or rolled off, the configuration files for each of the system components are updated to reflect a current list of active contract clusters. (See Morano paragraph 58)
Each order is preferably associated with a time in force value indicating whether the order is a day order, good until cancelled or good until the end of a specific date. (See Morano paragraph 60) The match engine may identify a matching order at any time during its existence for orders than remain active. (See Morano paragraph 60) When a match is found the match engine publishes a TRADES EMA bus message to the persist component. (See Morano paragraph 60) Match engine generates the trade sequence IDs and trade timestamp. (See Morano paragraph 60) The persist component is responsible for synchronizing the persistence of orders and trades that change due to the same event and in a particular embodiment, match engine tags data with an event ID and orders tagged with the same event ID are matched, which enables the persist component to know what records to synchronize and when. (See Morano paragraph 60)
Upon expiry of the time in force, the Persist process will expire orders upon the close of a market, e.g., or at the beginning of a new trading day. (See Morano paragraph 61) The matching engine receives a message to cancel the expired order(s) and processes the request at which point the order is cancelled by the matching engine due to its expiry and removed from the memory allocated to the match engine handling the order. (See Morano paragraph 61 – update to stored data, updating activity at a particular match engine)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the systems and methods of matching or otherwise allocating an incoming order to trade with a resting order using an adaptive match engine drawing upon different algorithms as disclosed in Boudreault with the contract clusters [plurality of match engines] each related to contracts with some sufficient relatedness where additional messages may be recognized as related to a cluster or a new cluster added or removed as disclosed by Morano in order use distributed computing to leverage improved abilities to communicate between system components so that complex functions can be implemented as many small components to provide improved performance and efficiency.
Regarding Claims 18-19, these claims recites substantially similar limitations as those seen in Claim 1 and as to those limitations are rejected for the same basis and reasons as disclosed above.
Regarding Claim 2, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 3, this claim recites the limitations of Claim 2 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 4, this claim recites the limitations of Claim 3 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 7, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above. In addition to the rejections above as if recited herein in full, Boudreault further discloses the following:
wherein the allocation logic is further configured to provide a match algorithm associated with the allocated identified subset for the hardware match engine, to which the identified subset has been allocated, to apply to a forwarded transaction message when more than one previously received but unsatisfied transaction are located by the search of the databases of the allocated subset. (See Boudreault paras 11, 70-72, 87-88 and 96)
Regarding Claim 8, this claim recites the limitations of Claim 7 and as to those limitations is rejected for the same basis and reasons as disclosed above. Further, Boudreault discloses the following:
wherein the match algorithm comprises a pro-rata algorithm, a first in first out (“FIFO”) algorithm, a Price Explicit Time algorithm, an Order Level Pro Rata algorithm, an Order Level Priority Pro Rata algorithm, a Preference Price Explicit Time algorithm, a Preference Order Level Pro Rate algorithm, a Preference Order Level Priority Pro Rata algorithm, a Threshold Pro-Rate algorithm, a Priority Threshold Pro-Rata algorithm, a Preference Threshold Pro-Rata algorithm, a Priority Preference Threshold Pro-Rata algorithm, or a Split Price-Time Pro-Rata algorithm. (See Boudreault paras 88 and Claims 6 and 19)
Regarding Claim 9, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above. Further, Boudreault discloses the following:
wherein the allocation logic is further operative to transfer at least a copy of the databases of the identified subset to a memory associated with the hardware match engine to which the identified databases have been allocated. (See Boudreault paras 81-84, 106, 119)
Regarding Claim 10, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 11, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above. In addition to the rejections set forth above as if recited herein in full, Boudreault further discloses the following:
wherein the memory further comprises a plurality of memory portions each associated with one of the plurality of hardware match engines and capable of storing at least one of the plurality of databases. (See Boudreault paras 81-85, 106, 109)
Regarding Claim 12, this claim recites the limitations of Claim 11 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 13, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above. Further, Boudreault discloses the following:
wherein the allocation logic is implemented by a field programmable gate array. (See Boudreault para 118)
Regarding Claim 14, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above. Further, Boudreault discloses the following:
further comprising an implicator coupled with the memory, the plurality of hardware match engines and the allocation logic, and operative to, when the processed transaction remains unsatisfied, identify at least one previously received but unsatisfied transaction message for an item related to the item of the processed transaction and generate a synthetic order therefore and submit the synthetic order to the transaction processing system. (See Boudreault paras 81-84)
Regarding Claim 15, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 16, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 17, this claim recites the limitations of Claim 1 and as to those limitations is rejected for the same basis and reasons as disclosed above or are otherwise disclosed by the prior art applied in previously rejected claims.
Regarding Claim 20, this claim recites the limitations of Claim 19 and as to those limitations is rejected for the same basis and reasons as disclosed above. Further, Boudreault discloses the following:
further comprising transferring at least a copy of the databases of the identified subset to a memory associated with the hardware match engine to which the identified databases have been allocated. (See Boudreault paras 81-84, 106, 119)
12. Claim(s) 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Boudreault et al (US PG Pub. 2014/0006243) (“Boudreault”) in view of Morano et al. (US PG Pub. 2005/0097026) as applied to claim 1 above, and further in view of Winbom et al. (US PG Pub. 2011/0264577) (“Winbom”)
Regarding Claims 5 and 6, these claims recite the limitations of Claim 1 and as to those limitations are rejected for the same basis and reasons as disclosed above.
wherein each of the plurality of hardware match engines is operative to update the stored data in the memory using a back channel protocol.
wherein each of the plurality of hardware match engines is operative to store the unsatisfied processed transaction in the allocated database using a remote direct memory access (“RDMA”) protocol.
In addition to the rejections above in relation to Claim 1, referenced here as if incorporated in full herein, Winbom discloses a distributed computing structure that may be used to implement parallel order matching and multi-threaded order validation in an electronic trading exchange. (See Winbom paragraph 52) Order data can be transmitted between network nodes via the network fabric. (See Winbom paragraph 52) Winbom further discloses that any suitable high performance computing architecture may be used, in particular referring to RDMA, remote direct memory access that permits high throughput, low latency networking. (See Winbom paragraph 55) Winbom also discloses a share nothing approach and that third generation SMP multiprocessing may also be used (other back channel protocols). See Winbom paragraphs 53, 57-58)
It would have been further obvious to one of ordinary skill in the art at the time of the invention to further modify the systems and methods of matching or otherwise allocating an incoming order to trade with a resting order using an adaptive match engine drawing upon different algorithms as disclosed in Boudreault in view of Morano to include the use of storing data via SMP or RDMA protocols in order to permit higher throughput and lower latency in parallel computer clusters.
Conclusion
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/AMBREEN A. ALLADIN/Primary Examiner, Art Unit 3691
September 14, 2025
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