Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Objections
Claims are objected to because of the following informalities:
As to claim 16, 17 and 19, “The SoC of claim 8” should read -- The SoC of claim 15--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-9, 11-16 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by EP 3137965 to Park et al. (hereafter Park).
Park was cited in applicant’s IDS filed on 1/13/25.
As to claim 1, Park teaches the invention as claimed including a method for operating a Central Processing Unit (CPU), the method comprising:
estimating, by the CPU, a plurality of specific timeframes that a plurality of workloads are to be completed to determine a plurality of workload completion windows [serialized and parallelized graphic workloads are detected and their execution timeframes (i.e. frame deadlines) are observed and estimated in part on estimated GPU and CPU power consumption for different DCVS levels in meeting the frame deadlines, paragraphs 19, 23, 27-28, 31 and 34-36; Figures 5a-5c and 11a-11b and corresponding text];
identifying, by the CPU, a process that is performing the plurality of workloads from among a plurality of processes that are being executed by the CPU over the plurality of workload completion windows [detecting serialized graphic workloads are performed partly by processes running on the CPU, paragraphs 19 and 24; DCVS module/process running on respective processors, paragraph 2, lines 1-8; paragraph 11, line 3];
provisioning, by the CPU, a performance state from among a plurality of different performance states to execute the process to complete the plurality of workloads within the plurality of workload completion windows [an appropriate CPU performance state/mode is selected based on the identified workload type (e.g. serialized graphic workloads) that enables the CPU to execute the workload with minimum power while respecting the workload completion windows, paragraphs 23-24, 26 and 34; Fig. 9 and corresponding text];
determining, by the CPU, whether the plurality of workloads being performed by the process are a plurality of deadline-bound workloads [determining DCVS levels that meet respect frame deadlines of workloads, paragraphs 26 and 34; Fig. 9 and corresponding text]; and
executing, by the CPU based on determining the plurality of workloads are the deadline-bound workloads, the plurality of workloads in accordance with the performance state [serialized graphic processing workloads are executed by the CPU in optimized performance level(s), Fig. 5a-5c and corresponding text; paragraphs 27-30].
As to claim 2, Park teaches the invention as claimed including wherein the estimating comprises identifying the plurality of specific timeframes that coincide with swapping between a visible buffer and a working buffer within a frame buffer of a Graphics Processing Unit (GPU). [frames corresponding to serialized workload stored and output from frame buffer having respective frame deadline, Figs. 5a-5c and corresponding text; paragraphs 14 and 28-30].
As to claim 4, Park teaches the invention as claimed including wherein the provisioning comprises provisioning the performance state that optimizes power consumption or performance of the CPU while completing the plurality of workloads within the plurality of workload completion windows [CPU/GPU power consumption is optimized, paragraphs 24, 26 and 34; Fig. 9 and corresponding text].
As to claim 5, Park teaches the invention as claimed including wherein the provisioning comprises provisioning the performance state that optimizes power consumption or performance of the CPU while completing the plurality of workloads within the plurality of workload completion windows less a deadline margin [CPU/GPU power consumption is optimized, paragraphs 24, 26 and 34; Fig. 9 and corresponding text; optimize CPU power consumption while performing the deadline-bound workloads on a tighter time margin, Fig. 5c versus Fig. 5b; paragraph 30].
As to claim 6, Park teaches the invention as claimed including further comprising: switching, by the CPU in response to detecting a compute-bound workload, from the performance state to a utilization-based control for the process to perform the compute-bound workload; and executing, by the CPU, the compute-bound workload in accordance with the utilization-based control [CPU DCVS level set for CPU is usage based allocation in executing CPU activity data such that CPU frequency and/or voltage are adjusted based on workload types, paragraphs 5-6 and 26; Fig. 4] (Note: compute-bound workload and deadline-bound workload are not mutually exclusive).
As to claim 7, Park teaches the invention as claimed including further comprising provisioning the performance state to execute the process to complete the plurality of workloads within the plurality of workload completion windows in response to completing the compute-bound workload [CPU DCVS level set for CPU is usage-based allocation in executing CPU activity data such that CPU frequency and/or voltage are adjusted based on workload types, paragraphs 5-6 and 26; Fig. 4].
As to claims 8-9 and 11-12, Park teaches the method for operating a CPU as claimed in claims 1-2 and 4-5 therefore Park teaches the computing device for implementing the method.
As to claims 15-16, Park teaches the method for operating a CPU as claimed in claims 1-2 therefore Park teaches the system for implementing the method [system components being incorporated on SoC, paragraphs 6 and 16; Fig. 1 ].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3, 10 and 17-18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park as applied to claims 1, 4-5, 8 and 15 above.
As to claim 3, Park teaches the invention as substantially as claimed including identifying a plurality of candidate processes from among the plurality of processes that are representative of the plurality of deadline-bound workloads over the plurality of workload completion windows; estimating a plurality of workloads completed by the plurality of candidate processes over the plurality of workload completion windows; statistically measuring total power consumption of the plurality of workloads completed by the plurality of candidate processes over the plurality of workload completion windows; and identifying the process as being a candidate process from among the plurality of candidate processes having the lowest power consumption [detecting serialized graphic workloads are performed partly by processes running on the CPU, paragraphs 19 and 24; DCVS module/process running on respective processors, paragraph 2, lines 1-8; paragraph 11, line 3; serialized graphic processing workloads are executed by the CPU in optimized performance level(s) in different scenarios/processes with lowest power consumption as the ideal or most optimized candidate, Fig. 5a-5c and corresponding text; paragraphs 27-30].
Park does not specifically teach the measurement of variances of workloads completed by processes in identifying a candidate process based on the process having the lowest variance. However, measure of low variance in identifying an ideal or optimal candidate is well known in the art due to preference for candidate that produces stable and predictable results. Therefore, it is obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have implement an alternative to low power consumption in identifying candidate process by implementing a process that identify low variance as a matter of design choice.
As to claims 10 and 17, these claims are rejected for the same reason as claim 3 above.
As to claim 18, this claim s is rejected for the same reason as claim 5 above.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PG Pub. 2015/0317762 is related to EP 3137965 relied on in the rejection above.
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/QING YUAN WU/Primary Examiner, Art Unit 2199