Office Action Predictor
Last updated: April 15, 2026
Application No. 18/367,773

Optical Sensing Apparatus

Non-Final OA §103
Filed
Sep 13, 2023
Examiner
CHOI, CALVIN Y
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Artilux, INC.
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
94%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
686 granted / 842 resolved
+13.5% vs TC avg
Moderate +13% lift
Without
With
+13.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
30 currently pending
Career history
872
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
65.0%
+25.0% vs TC avg
§102
23.9%
-16.1% vs TC avg
§112
5.6%
-34.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 842 resolved cases

Office Action

§103
DETAILED ACTION This Office Action is in response to the application filed on 13 September 2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wei et al. (US 2021/0082992 A1; hereinafter Wei). In regards to claim 1, Wei teaches, e.g. in figs. 1 and 10, an optical sensing apparatus comprising: a first photo-detecting layer ([0036], [0038]; fig. 1: e.g. (110D)) comprising a first absorption region (114D) [0038] configured to absorb light in at least a visible spectrum [0036]; a second photo-detecting layer ([0036], [0038]; fig. 1: e.g. (110B)) formed over the first photo-detecting layer, the second photo-detecting layer comprising a second absorption region (114B) [0038] configured to absorb light in at least a mid-infrared spectrum [0036]; a first buffer layer ([0040-0044]; fig. 1: e.g. (112B)) formed at the top of the second photo-detecting layer; and a second buffer layer ([0040-0044]; fig. 1: e.g. (112D)) formed at the top of the first photo-detecting layer and under the second photo-detecting layer. Wei appears to be silent as to, but does not preclude, the limitations comprising the first buffer layer formed over the second photo-detecting layer and the second buffer layer formed over the first photo-detecting layer and under the second photo-detecting layer; however Wei teaches that each layer can be each of the recited components depending on the desired application of the overall device [0036]. Therefore, one having ordinary skill in the art at the time the application at hand was filed would have found it obvious to have an arrangement of the elements of the device as taught by Wei such that the first buffer layer is formed over the second photo-detecting layer and the second buffer layer formed is over the first photo-detecting layer and under the second photo-detecting layer because Wei teaches that the arrangement of the layers is the use or an application of a one of a number of finite number of identified, predictable solutions, with a reasonable expectation of success (e.g. dependent on the desired application of the device in question). See MPEP §2141 III. In regards to claim 2, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 1. Wei further teaches the limitations further comprising: a first contact (e.g. (650A-3)) formed over the first photo-detecting layer (114D) (fig. 10: e.g. (650A-3) is formed to protrude over (110D)) [0077]; and a second contact (e.g. (650A-1)) formed over the first buffer layer (fig. 10: e.g. (650A-1) is formed to protrude over (112B)) [0077]. In regards to claim 3, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 2. Wei further teaches the limitations wherein the first photo-detecting layer further comprises a charge region configured to amplify charge-carriers generated in the second absorption region [0043-0045]. In regards to claim 4, Wei teaches the limitations discussed above in addressing claim 3. Wei further teaches the limitations wherein the first photo-detecting layer further comprises a well region electrically coupled to the second contact, the well region configured to guide the amplified charge-carriers to the second contact ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include well structures). In regards to claim 5, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 1. Wei further teaches the limitations further comprising: a third photo-detecting layer ([0036], [0038]; fig. 1: e.g. (110C)) formed between the first photo-detecting layer (110D) and the second photo-detecting layer (110B), the third photo-detecting layer comprising a third absorption region (114C) [0038] configured to absorb light in at least a short-wavelength mid-infrared spectrum [0036]. In regards to claim 6, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 5. Wei further teaches the limitations further comprising: a third contact (e.g. (650A-2)) formed over the third photo-detecting layer (fig. 10: e.g. (650A-2) is formed to protrude over (110C)) [0077]. In regards to claim 7, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 5. Wei further teaches the limitations further comprising: a passivation layer (114B) formed between the third photo-detecting layer (110C) and the second buffer layer (112B) ([0048]; fig. 10). In regards to claim 8, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 7. Wei further teaches the limitations wherein the first photo-detecting layer (110D) ([0036], [0038]) comprises silicon [0051], the second photo-detecting layer comprises a two-dimensional material ([0045]: e.g. nBn device architectures), the third photo-detecting layer (110C) ([0036], [0038]) comprises germanium [0051], and the passivation layer comprises epitaxy silicon or amorphous silicon [0041]. In regards to claim 9, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 7. Wei further teaches the limitations wherein the first photo-detecting layer includes p-doping ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include p-doped structures), the second photo-detecting layer includes p-doping, n-doping, or an intrinsic region ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include p-i-n doped structures), the third photo-detecting layer includes p-doping ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include p-doped structures), and the passivation layer includes p-doping ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include p-doped structures). In regards to claim 10, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 7. Wei further teaches the limitations wherein the first photo-detecting layer includes n-doping, the second photo-detecting layer includes p-doping, the third photo- detecting layer includes p-doping, and the passivation layer including p-doping ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include p-i-n doped structures). In regards to claim 11, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 1. Wei further teaches the limitations wherein at least one of the first buffer layer or the second buffer layer comprises a monolayer graphene or a multi-layer graphene ([0045]: e.g. nBn device architectures). In regards to claim 12, Wei teaches, e.g. in figs. 1 and 10, an optical sensing apparatus comprising a silicon layer [0051] comprising: a first absorption region (114D) [0038] configured to absorb light in at least a visible spectrum [0036]; a germanium layer [0051] formed over the silicon layer, the germanium layer comprising: a second absorption region (114B) [0038] configured to absorb light in at least a short-wave infrared (SWIR) spectrum [0036]; a black phosphorus layer [0051] formed over the germanium layer, the black phosphorus layer comprising: a third absorption region (114C) [0038] configured to absorb light in at least a mid- infrared spectrum [0036]; a first buffer layer ([0040-0044]; fig. 1: e.g. (112B)) formed at the top of the black phosphorus layer; and a second buffer layer ([0040-0044]; fig. 1: e.g. (112D)) formed at the top of the silicon layer and under the black phosphorus layer. Wei appears to be silent as to, but does not preclude, the limitations comprising the first buffer layer formed over the black phosphorus layer and the second buffer layer formed over the silicon layer and under the black phosphorus layer; however Wei teaches that each layer can be each of the recited components depending on the desired application of the overall device [0036]. Therefore, one having ordinary skill in the art at the time the application at hand was filed would have found it obvious to have an arrangement of the elements of the device as taught by Wei such that the first buffer layer formed over the black phosphorus layer and the second buffer layer formed over the silicon layer and under the black phosphorus layer because Wei teaches that the arrangement of the layers is the use or an application of a one of a number of finite number of identified, predictable solutions, with a reasonable expectation of success (e.g. dependent on the desired application of the device in question). See MPEP §2141 III. In regards to claim 13, Wei teaches, e.g. in figs. 1 and 10, the limitations discussed above in addressing claim 12. Wei further teaches the limitations further comprising a silicon-based passivation layer (114B) formed between the germanium layer (110C) and the second buffer layer (112B) ([0048], [0051]; fig. 10). In regards to claim 14, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 12. Wei further teaches the limitations wherein the silicon layer further comprises a charge region configured to amplify charge-carriers generated in the black phosphorus layer [0043-0045]. In regards to claim 15, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 14. Wei further teaches the limitations wherein the silicon layer further comprises a well region configured to guide the amplified charge-carriers to a readout circuitry ([0043-0045]: Wei discloses a plurality of different possible electromagnetic radiation sensitive semiconductor devices, some of which include well structures). In regards to claim 16, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 12. Wei further teaches the limitations wherein at least one of the first buffer layer or the second buffer layer comprises a monolayer graphene or a multilayer graphene ([0045]: e.g. nBn device architectures). In regards to claim 17, Wei teaches, e.g. in figs. 1 and 10-12, an optical sensing apparatus comprising: a silicon layer comprising: a first absorption region (114D) [0038] configured to absorb light in at least a visible spectrum [0036]; a germanium layer [0051] formed over the silicon layer, the germanium layer comprising: a second absorption region (114B) [0038] configured to absorb light in at least a SWIR spectrum [0036]; a two-dimensional-material layer ([0045]: e.g. nBn device architectures) formed over the germanium layer, the two-dimensional-material layer comprising: a third absorption region (114C) [0038] configured to absorb light in at least a mid-infrared spectrum [0036]; a first buffer layer ([0040-0044]; fig. 1: e.g. (112B)) formed at the top of the two-dimensional-material layer; a second buffer layer ([0040-0044]; fig. 1: e.g. (112D)) formed at the top of the silicon layer and under the two-dimensional material layer. Wei appears to be silent as to, but does not preclude, the limitations comprising the first buffer layer formed over the two-dimensional-material layer and the second buffer layer formed over the silicon layer and under the two-dimensional material layer; however Wei teaches that each layer can be each of the recited components depending on the desired application of the overall device [0036]. Therefore, one having ordinary skill in the art at the time the application at hand was filed would have found it obvious to have an arrangement of the elements of the device as taught by Wei such that the first buffer layer formed over the two-dimensional-material layer and the second buffer layer formed over the silicon layer and under the two-dimensional material layer because Wei teaches that the arrangement of the layers is the use or an application of a one of a number of finite number of identified, predictable solutions, with a reasonable expectation of success (e.g. dependent on the desired application of the device in question). See MPEP §2141 III. In regards to claim 18, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 17. Wei further teaches the limitations wherein the two-dimensional-material layer comprises graphene, MXene, topological insulators, or transition metal dichalcogenides ([0045]: e.g. nBn device architectures). In regards to claim 19, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 17. Wei further teaches the limitations wherein the silicon layer further comprises a charge region configured to amplify charge-carriers generated in the two-dimensional material layer [0043-0045]. In regards to claim 20, Wei teaches, e.g. in figs. 10-12, the limitations discussed above in addressing claim 17. Wei further teaches the limitations further comprising a silicon-based passivation layer (114B) formed between the germanium layer (110C) and the second buffer layer (112B) ([0048]; fig. 10). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tian et al. (US 2011/0309236 A1) and Niu et al. (US 2023/0087411 A1). Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time). Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William (Blake) Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. CALVIN CHOI Patent Examiner Art Unit 2812 /CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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Prosecution Timeline

Sep 13, 2023
Application Filed
Dec 26, 2025
Non-Final Rejection — §103
Mar 25, 2026
Interview Requested
Mar 31, 2026
Examiner Interview Summary
Mar 31, 2026
Applicant Interview (Telephonic)
Apr 01, 2026
Response Filed

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
94%
With Interview (+13.0%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 842 resolved cases by this examiner. Grant probability derived from career allow rate.

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