DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because:
In FIG 2, boxes or simple shapes are labeled only with reference numbers, without descriptive legends. The Examiner directs the applicant to 37 C.F.R. 1.84(n) and 1.84(o) which state, “Graphical drawing symbols may be used for conventional elements when appropriate” while “[o]ther symbols which are not universally recognized may be used, subject to approval by the Office” and that “[s]uitable descriptive legends may be used subject to approval by the Office, or may be required by the examiner where necessary for understanding of the drawing”. Since the boxes or simple shapes in FIG 2 are not universally recognized for the elements they represent, the Examiner may require descriptive legends for better understanding of the drawings. See MPEP 608.02.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 10-17 are objected to because of the following informalities:
In claim 10, line 9, The “and” in the end of the line is redundant, and should be deleted.
In claim 10, line 16, There should be an “and” in the end of the line.
In claim 11, the status marking “Original” is incorrect.
The other claim(s) not discussed above, or depending on the above claim(s), are objected to for inheriting the issue(s) from their linking claim(s).
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over George et al. (US 20200234428 A1; cited previously; hereinafter “George”) in view of Samsung Semiconstory ("Part 8, “Electrical Die Sorting (EDS)” 2018; available at https://semiconductor.samsung.com/support/tools-resources/fabrication-process/eight-essential-semiconductor-fabrication-processes-part-8-eds-electrical-die-sorting-for-the-perfect-chips/).
Regarding claim 10, George teaches a defect detection device (see FIG. 3) comprising:
an optical device (i.e., 140; see FIG. 3) configured to radiate light onto a chip of a substrate (i.e., “a wafer 103 is illuminated by a normal incidence beam 104 generated by one or more illumination sources 101. Alternatively, the illumination subsystem may be configured to direct the beam of light to the specimen at an oblique angle of incidence”; see [0035]; “a wafer may include a plurality of dies having repeatable pattern features”; see [0123]) and obtain a plurality of spectrum images of each of a plurality of blocks (i.e., locations) in the substrate (i.e., “Illumination may be provided to the specimen over any suitable range of wavelengths”; see [0036]; “collect the light scattered and/or reflected by wafer 103 and focus that light onto detector arrays 115, 120, and 125, respectively… their locations”; see [0043]; “wafer 103 is repeatedly scanned in the lateral directions (e.g., x-direction and y-direction) for two dimensional scans. In addition, wafer 103 may be repeated scanned in the lateral directions at different z-positions for three dimensional scans”; see [0053] and FIG. 2);
a server comprising one or more processors (i.e., “computing system 130”; see [0038]) configured to:
perform an (i.e., locations) of the substrate by classifying types of defects of each of the plurality of blocks based on (i.e., “the SEM images allow a user to accurately classify the type of DOI. The result of SEM review is set of labeled defects identifying the location of nuisance defects and DOIs on a wafer and the classification of the DOIs”; see [0006]; “Defect verification measurements are performed on the diversity set of candidate defects. The defect locations, defect classification, and associated defect images from the defect verification measurements are stored in a memory”; see [0076]; “Defect verification can be accomplished in many different ways. In some embodiments, voltage contrast inspection is performed to verify defects. In these embodiments, a wafer is decorated in accordance with a small sample plan and voltage contrast measurements are performed on the decorated wafer by a voltage contrast inspection tool”; see [0072]), and
match the plurality of spectrum images with defect information of each of the plurality of blocks (i.e., “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see [0077]),
train a defect detection model by using a defect grade as an output value and the plurality of spectrum images and the defect information (i.e., “The defect verification data and the corresponding defect image patches are employed to train a nuisance filter, defect classifier, or both”; see [0077]; “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see [0082]; “After a reduction step is performed, the reduced neural network model is retrained on the same image data and known classifications”; see [0087]), and
extract a feature vector (i.e., “estimating the values of one or more automatically generated attributes derived from images of a candidate defect”; see [0011]) from a target spectrum image obtained from the optical device (i.e., “images of a candidate defect”; see [0011]) by using the defect detection model and detect a target defect grade of the target spectrum image based on the feature vector (i.e., “automatically generated attributes are determined by iteratively training, reducing, and retraining a deep learning model”; see [0012]; “one or more attribute vectors are extracted from the collected image data and defect detection is performed based on the measured attribute vectors”; see [0058]);
a database storing the plurality of matched spectrum images and the defect information corresponding to the plurality of spectrum images (i.e., “The defect locations, defect classification, and associated defect images from the defect verification measurements are stored in a memory (e.g., memory 162 on board computing system 160)… In some embodiments, the defect location, classification, and associated defect images associated with the diversity set of candidate defects is also stored in a KLARF file format.”; see [0076]).
George does not explicitly disclose (see only the underlined):
perform an electrical die sorting (EDS) test on the substrate and inspect defects of each of the plurality of blocks of the substrate by classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test.
But Samsung Semiconstory teaches:
perform an electrical die sorting (EDS) test on the substrate and inspect defects of each of the plurality of blocks of the substrate by classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test (i.e., EDS to sort and mark defective chips based on voltage and current characteristics parameters of the chips; see the document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, by configuring the server to perform an electrical die sorting (EDS) test on the substrate and inspect defects of each of the plurality of blocks of the substrate by classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test, as claimed. The rationale would be to utilize a known defect classification tool for labeling the training data for its known ability of classification a defect.
Regarding claim 12, George further teaches:
wherein the server is further configured to select a target defect that is an inspection target (i.e., “Defect classification based on attributes identified based on deep learning enables learning of attributes tailored to specific use cases. In general, desired classification task guides the selection of outputs and the objective function employed during training of the deep learning based model. In this manner, the same data is employed to learn different attributes, each optimally suited for a particular classification task based on the selection of outputs and objective function. In some examples, attributes are learned that best separate one defect type from another (i.e., defect classification)”; see [0033]).
Regarding claim 13, George further teaches:
wherein the optical device is further configured to obtain the plurality of spectrum images of each of the plurality of blocks in the substrate by using spectral reflectometry (i.e., “Illumination may be provided to the specimen over any suitable range of wavelengths”; see [0036]; “collect the light scattered and/or reflected by wafer 103 and focus that light onto detector arrays 115, 120, and 125, respectively”; see [0043]; see, also, FIG. 1).
Regarding claim 14, George further teaches:
wherein the defect detection model is based on at least one of a deep neural network (DNN), a convolution neural network (CNN), or a recurrent neural network (RNN) (i.e., “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see [0082]).
Regarding claim 15, George further teaches:
wherein the optical device is further configured to obtain the plurality of spectrum images by using light having a wavelength of about 270 nm to about 750 nm (i.e., “the illumination light includes wavelengths ranging from 260 nanometers to 950 nanometers”; see [0036]).
Claims 1-3, 5, 6, 8, 9, 11, and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over George in view of Samsung Semiconstory and Sofer et al. (US 20220291138 A1; cited in IDS: hereinafter “Sofer”).
Regarding claim 1, George teaches a defect detection method comprising:
radiating light onto a chip of a substrate (i.e., “a wafer 103 is illuminated by a normal incidence beam 104 generated by one or more illumination sources 101. Alternatively, the illumination subsystem may be configured to direct the beam of light to the specimen at an oblique angle of incidence”; see [0035]; “a wafer may include a plurality of dies having repeatable pattern features”; see [0123]);
obtaining a spectrum image indicating an amount of the light according to a wavelength (i.e., “Illumination may be provided to the specimen over any suitable range of wavelengths”; see [0036]) from reflected light reflected from the substrate (i.e., “collect the light scattered and/or reflected by wafer 103 and focus that light onto detector arrays 115, 120, and 125, respectively”; see [0043]);
performing an (i.e., “the SEM images allow a user to accurately classify the type of DOI. The result of SEM review is set of labeled defects identifying the location of nuisance defects and DOIs on a wafer and the classification of the DOIs”; see [0006]);
inspecting defects of each of a plurality of blocks (i.e., locations) of the substrate comprising classifying types of defects of each of the plurality of blocks based on (i.e., “the SEM images allow a user to accurately classify the type of DOI. The result of SEM review is set of labeled defects identifying the location of nuisance defects and DOIs on a wafer and the classification of the DOIs”; see [0006]); “Defect verification measurements are performed on the diversity set of candidate defects. The defect locations, defect classification, and associated defect images from the defect verification measurements are stored in a memory”; see [0076]; “Defect verification can be accomplished in many different ways. In some embodiments, voltage contrast inspection is performed to verify defects. In these embodiments, a wafer is decorated in accordance with a small sample plan and voltage contrast measurements are performed on the decorated wafer by a voltage contrast inspection tool”; see [0072]);
generating a defect map indicating a defect grade of each of the plurality of blocks based on the classified defects (i.e., “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see [0077]);
generating spectrum image information comprising the spectrum image and defect information corresponding to the spectrum image by matching the spectrum image with the defect map (i.e., “The defect verification data and the corresponding defect image patches are employed”; see [0067]);
training a defect detection model by using the defect grade as an output value and the spectrum image information as an input value (i.e., “The defect verification data and the corresponding defect image patches are employed to train a nuisance filter, defect classifier, or both”; see [0077]; “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see [0082]; “After a reduction step is performed, the reduced neural network model is retrained on the same image data and known classifications”; see [0087]);
obtaining a target spectrum image with respect to a target substrate (i.e., “images of a candidate defect”; see [0011]);
extracting a feature vector from the target spectrum image (i.e., “estimating the values of one or more automatically generated attributes derived from images of a candidate defect”; see [0011]) by using the defect detection model (i.e., “automatically generated attributes are determined by iteratively training, reducing, and retraining a deep learning model”; see [0012]), and detecting a target defect grade of the target spectrum image based on the feature vector (i.e., “The reduced model is subsequently employed to generate values of the identified attributes associated with images of candidate defects having unknown classification. The attribute values are employed by a statistical classifier to classify the candidate defects”; see [0012]; “one or more attribute vectors are extracted from the collected image data and defect detection is performed based on the measured attribute vectors”; see [0058]); and
George does not explicitly disclose (see only the underlined):
performing an electrical die sorting (EDS) test on the substrate;
inspecting defects of each of a plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test.
But Samsung Semiconstory teaches:
inspecting defects of each of a plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test (i.e., EDS to sort out and marking defective chips based on voltage and current characteristics parameters).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, by performing an electrical die sorting (EDS) test on the substrate; inspecting defects of each of a plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test, as claimed. The rationale would be to utilize a known defect classification tool for labeling the training data for its known ability of classification a defect.
George does not explicitly disclose:
generating a target defect map based on the target defect grade.
Sofer teaches:
generating a target defect map of the target defect grade (i.e., “a defect map is produced to show locations on the specimen suspected of having high probability of a defect”; see [0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory , further in view of Sofer by generating a target defect map based on the target defect grade, as claimed. The rationale would be to help providing an overview of the defects with corresponding locations on a wafer map.
Regarding claim 2, George further teaches: wherein the obtaining of the spectrum image includes:
generating the spectrum image in units of one or more of a whole substrate, a shot, a chip, and a block (i.e., “records image patches (e.g., 32×32 pixel patches, 64×64 pixel patches, etc.) associated with defect locations identified in each of the initial inspections at the one or more focus planes or focus range, rather than throughout the entire depth of the structure”; see [0066] and FIG. 2); and
extracting the spectrum image of each of the plurality of blocks (i.e., “records image patches (e.g., 32×32 pixel patches, 64×64 pixel patches, etc.) associated with defect locations identified in each of the initial inspections at the one or more focus planes or focus range, rather than throughout the entire depth of the structure”; see [0066] and FIG. 2)
George does not explicitly disclose (see only the underlined):
extracting the spectrum image of each of the plurality of blocks based on chip layout information of the substrate and location information of each of the plurality of blocks of the substrate.
But Sofer teaches:
extracting the spectrum image of each of the plurality of blocks based on hierarchical physical layout information of the substrate and location information of each of the plurality of blocks of the substrate (i.e., “selecting of one or more specimen locations from a collection of specimen locations obtained from an inspection tool or from any other source, for example received from a user, extracted from design data”; see [0035]; “The term “design data” used in the specification should be expansively construed to cover any data indicative of hierarchical physical design (layout) of a specimen”; see [0034]).
Also, Samsung Semiconstory teaches performing EDS on a chip (see document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to further modify George in view of Samsung Semiconstory and Sofer by extracting the spectrum image of each of the plurality of blocks based on chip layout information of the substrate and location information of each of the plurality of blocks of the substrate, as claimed. The rationale would be to facilitate the defect detection by its physical components of interest in the wafer design (e.g., chip level).
Regarding claim 3, as a result of modification applied to claim 1 above, George in view of Samsung Semiconstory and Sofer further teaches: wherein the inspecting of the defects includes:
selecting a target defect that is an inspection target based on the classified types of the defects (i.e., “Defect classification based on attributes identified based on deep learning enables learning of attributes tailored to specific use cases. In general, desired classification task guides the selection of outputs and the objective function employed during training of the deep learning based model. In this manner, the same data is employed to learn different attributes, each optimally suited for a particular classification task based on the selection of outputs and objective function. In some examples, attributes are learned that best separate one defect type from another (i.e., defect classification)”; see George, [0033]),
wherein the generating of the defect map includes generating the defect map of the target defect (see discussion of claim 1 above).
Regarding claim 5, George further teaches:
wherein the generating of the spectrum image information includes matching an image corresponding to each of the plurality of blocks in the spectrum image with the defect grade of each of the plurality of blocks of the defect map (i.e., “The defect verification data and the corresponding defect image patches are employed”; see [0067]; “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see [0077]).
Regarding claim 6, George further teaches:
wherein the spectrum image is obtained by spectral reflectometry (i.e., “Illumination may be provided to the specimen over any suitable range of wavelengths”; see [0036]; “collect the light scattered and/or reflected by wafer 103 and focus that light onto detector arrays 115, 120, and 125, respectively”; see [0043]; see, also, FIG. 1).
Regarding claim 8, George further teaches:
wherein the defect detection model is based on at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN) (i.e., “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see [0082]).
Regarding claim 9, as a result of modification applied to claim 1 above, George in view of Samsung Semiconstory and Sofer further teaches:
wherein the defect map and the target defect map are maps in which a target defect that is an inspection target is marked on each of the plurality of blocks in the substrate (i.e., “The outputs of detectors 115, 120, and 125 are communicated to computing system 130 for processing the signals and determining the presence of candidate defects and their locations”; see George, [0043]; “Defect locations and associated defect images 152 associated with defect verification measurements are stored in a memory”; see George, [0074]; “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see George, [0077]; “a defect map is produced to show locations on the specimen suspected of having high probability of a defect”; see Sofer, [0006]).
Regarding claim 11, the prior art applied to the preceding linking claim(s) teaches the features of the linking claim(s).
George does not explicitly disclose:
wherein the optical device is further configured to generate spectrum data of the chip and obtain the plurality of spectrum images of each of the plurality of blocks in the substrate based on layout information and address information of the chip of the spectrum data.
But Sofer teaches:
wherein the optical device is further configured to generate spectrum data of one hierarchical component of the substrate and obtain the plurality of spectrum images of each of the plurality of blocks in the substrate based on hierarchical physical layout information and address information of the chip of the spectrum data (i.e., “selecting of one or more specimen locations from a collection of specimen locations obtained from an inspection tool or from any other source, for example received from a user, extracted from design data”; see [0035]; “The term “design data” used in the specification should be expansively construed to cover any data indicative of hierarchical physical design (layout) of a specimen”; see [0034]).
Also, Samsung Semiconstory teaches performing EDS on a chip (see document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, further in view of Sofer, such that the optical device is further configured to generate spectrum data of the chip of the substrate and obtain the plurality of spectrum images of each of the plurality of blocks in the substrate based on layout information and address information of the chip of the spectrum data, as claimed. The rationale would be to facilitate the defect detection by its physical components of interest in the wafer design (e.g., a chip).
Regarding claim 16, the prior art applied to the preceding linking claim(s) teaches the features of the linking claim(s).
George does not explicitly disclose:
wherein the server using the defect detection model is configured to generate a defect grade of each of a plurality of target blocks of the target spectrum image.
However, Sofer teaches:
select the locations for defect detection based on wafer hierarchical physical design or layout (i.e., “selecting of one or more specimen locations from a collection of specimen locations obtained from an inspection tool or from any other source, for example received from a user, extracted from design data”; see [0035]; “The term “design data” used in the specification should be expansively construed to cover any data indicative of hierarchical physical design (layout) of a specimen”; see [0034]); and
generating a target defect map of the target defect grade (i.e., “a defect map is produced to show locations on the specimen suspected of having high probability of a defect”; see [0006]).
Also, Samsung Semiconstory teaches performing EDS on a chip (see document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, further in view of Sofer, such that the server using the defect detection model is configured to generate a defect grade of each of a plurality of target blocks of the target spectrum image, as claimed. The rationale would be to facilitate the defect detection by its physical components of interest in the wafer design (e.g., a chip) for an entire wafer.
Regarding claim 17, George in view of Samsung Semiconstory further teaches:
wherein the server is further configured to perform the EDS test (see discussion of claim 10) on the location of the substrate (i.e., “Defect verification measurements are performed on the diversity set of candidate defects. The defect locations, defect classification, and associated defect images from the defect verification measurements are stored in a memory”; see George, [0076]; “Defect verification can be accomplished in many different ways. In some embodiments, voltage contrast inspection is performed to verify defects. In these embodiments, a wafer is decorated in accordance with a small sample plan and voltage contrast measurements are performed on the decorated wafer by a voltage contrast inspection tool”; see George, [0072]).
George does not explicitly disclose (see only the underlined):
wherein the server is further configured to perform the EDS test on the chip.
However, Sofer teaches:
select the locations for defect detection based on wafer hierarchical physical design or layout (i.e., “selecting of one or more specimen locations from a collection of specimen locations obtained from an inspection tool or from any other source, for example received from a user, extracted from design data”; see [0035]; “The term “design data” used in the specification should be expansively construed to cover any data indicative of hierarchical physical design (layout) of a specimen”; see [0034]).
Also, Samsung Semiconstory teaches performing EDS on a chip (see document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, further in view of Sofer, such that the defect inspection unit is further configured to perform the EDS test on a chip of the substrate and classify types of the defects of each of the plurality of blocks based on an electrical signal of the chip, as claimed. The rationale would be to facilitate the defect detection by its physical components of interest in the wafer design (e.g., a chip).
Regarding claim 18, George teaches a defect detection method comprising:
radiating light onto a chip of a substrate (i.e., “a wafer 103 is illuminated by a normal incidence beam 104 generated by one or more illumination sources 101. Alternatively, the illumination subsystem may be configured to direct the beam of light to the specimen at an oblique angle of incidence”; see [0035]; “a wafer may include a plurality of dies having repeatable pattern features”; see [0123]);
generating a spectrum image (i.e., “Illumination may be provided to the specimen over any suitable range of wavelengths”; see [0036]) in units of any one or more of a whole substrate, a shot, a chip, and a block (i.e., “records image patches (e.g., 32×32 pixel patches, 64×64 pixel patches, etc.) associated with defect locations identified in each of the initial inspections at the one or more focus planes or focus range, rather than throughout the entire depth of the structure”; see [0066] and FIG. 2) from reflected light reflected from the substrate (i.e., “collect the light scattered and/or reflected by wafer 103 and focus that light onto detector arrays 115, 120, and 125, respectively”; see [0043]);
extracting a spectrum image of each of a plurality of blocks (i.e., “records image patches (e.g., 32×32 pixel patches, 64×64 pixel patches, etc.) associated with defect locations identified in each of the initial inspections at the one or more focus planes or focus range, rather than throughout the entire depth of the structure”; see [0066] and FIG. 2)
performing an (i.e., “the SEM images allow a user to accurately classify the type of DOI. The result of SEM review is set of labeled defects identifying the location of nuisance defects and DOIs on a wafer and the classification of the DOIs”; see [0006]);
inspecting defects of each of the plurality of blocks (i.e., locations) of the substrate comprising classifying types of defects of each of the plurality of blocks based on (i.e., “the SEM images allow a user to accurately classify the type of DOI. The result of SEM review is set of labeled defects identifying the location of nuisance defects and DOIs on a wafer and the classification of the DOIs”; see [0006]); “Defect verification measurements are performed on the diversity set of candidate defects. The defect locations, defect classification, and associated defect images from the defect verification measurements are stored in a memory”; see [0076]; “Defect verification can be accomplished in many different ways. In some embodiments, voltage contrast inspection is performed to verify defects. In these embodiments, a wafer is decorated in accordance with a small sample plan and voltage contrast measurements are performed on the decorated wafer by a voltage contrast inspection tool”; see [0072]);
generating a defect map indicating a defect grade of each of the plurality of blocks based on the classified defects (i.e., “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see [0077]);
generating spectrum image information comprising the spectrum image and defect information corresponding to the spectrum image by matching the spectrum image with the defect map (i.e., “The defect verification data and the corresponding defect image patches are employed”; see [0067]);
training a defect detection model by using the defect grade as an output value and the spectrum image information as an input value (i.e., “The defect verification data and the corresponding defect image patches are employed to train a nuisance filter, defect classifier, or both”; see [0077]; “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see [0082]; “After a reduction step is performed, the reduced neural network model is retrained on the same image data and known classifications”; see [0087]);
obtaining a target spectrum image from an optical device (i.e., “images of a candidate defect”; see [0011]);
extracting a feature vector from the target spectrum image (i.e., “estimating the values of one or more automatically generated attributes derived from images of a candidate defect”; see [0011]) by using the defect detection model (i.e., “automatically generated attributes are determined by iteratively training, reducing, and retraining a deep learning model”; see [0012]), and detecting a target defect grade of the target spectrum image based on the feature vector (i.e., “The reduced model is subsequently employed to generate values of the identified attributes associated with images of candidate defects having unknown classification. The attribute values are employed by a statistical classifier to classify the candidate defects”; see [0012]; “one or more attribute vectors are extracted from the collected image data and defect detection is performed based on the measured attribute vectors”; see [0058]); and
wherein the inspecting of the defects comprises:
classifying types of the defects of each of the plurality of blocks of the substrate based on a result of the i.e., “Computing system 160 samples the identified defects to generate a diversity set of candidate defects 153 communicated to defect verification tool 151. In some embodiments, computing system 160 bins the defects identified by inspection system 100 during defect discovery (e.g., 100 million or more DOIs) and selects a few defects from each bin to generate the diversity set of candidate defects 153”; see [0075]; “The defect classification may be performed with the assistance of a human user or automatically”; see, [0076]); and
selecting a target defect that is an inspection target based on the classified types of the defects (i.e., “Defect classification based on attributes identified based on deep learning enables learning of attributes tailored to specific use cases. In general, desired classification task guides the selection of outputs and the objective function employed during training of the deep learning based model. In this manner, the same data is employed to learn different attributes, each optimally suited for a particular classification task based on the selection of outputs and objective function. In some examples, attributes are learned that best separate one defect type from another (i.e., defect classification)”; see, [0033]).
George does not explicitly disclose (see only the underlined):
performing an electrical die sorting (EDS) test on the substrate;
inspecting defects of each of the plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test.
But Samsung Semiconstory teaches:
inspecting defects of each of a plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test (i.e., EDS to sort out and marking defective chips based on voltage and current characteristics parameters).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, by performing an electrical die sorting (EDS) test on the substrate; inspecting defects of each of the plurality of blocks of the substrate comprising classifying types of defects of each of the plurality of blocks based on at least one of a duration, a voltage, or a current of an electrical signal of the chip obtained from the EDS test, as claimed. The rationale would be to utilize a known defect classification tool for labeling the training data for its known ability of classification a defect.
George does not explicitly disclose (see only the underlined):
extracting a spectrum image of each of a plurality of blocks based on chip layout information of the substrate and location information of each of the plurality of blocks of the substrate; and
generating a target defect map based on the target defect grade.
But Sofer teaches:
extracting the spectrum image of each of the plurality of blocks based on hierarchical physical layout information of the substrate and location information of each of the plurality of blocks of the substrate (i.e., “selecting of one or more specimen locations from a collection of specimen locations obtained from an inspection tool or from any other source, for example received from a user, extracted from design data”; see [0035]; “The term “design data” used in the specification should be expansively construed to cover any data indicative of hierarchical physical design (layout) of a specimen”; see [0034]); and
generating a target defect map of the target defect grade (i.e., “a defect map is produced to show locations on the specimen suspected of having high probability of a defect”; see [0006]).
Also, Samsung Semiconstory teaches performing EDS on a chip (see document throughout).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory, further in view of Sofer by extracting the spectrum image of each of the plurality of blocks based on hierarchical physical layout information of the substrate and location information of each of the plurality of blocks of the substrate and generating a target defect map of the target defect grade, as claimed. The rationale would be to facilitate the defect detection by its physical components of interest in the wafer design (e.g., chip level), and help providing an overview of the defects with corresponding locations on a wafer map.
Regarding claim 19, as a result of modification applied to claim 18 above, George in view of Samsung Semiconstory and Sofer further teaches: wherein
the defect detection model is based on at least one of a deep neural network (DNN), a convolutional neural network (CNN), or a recurrent neural network (RNN) (i.e., “Deep learning based attribute model training module 172 generates a deep learning based model having defect image data as input and the known classification of the defect as output”; see George, [0082]), and
the defect map and the target defect map are maps in which a target defect that is an inspection target is marked on each of the plurality of blocks in the substrate (i.e., “The outputs of detectors 115, 120, and 125 are communicated to computing system 130 for processing the signals and determining the presence of candidate defects and their locations”; see George, [0043]; “Defect locations and associated defect images 152 associated with defect verification measurements are stored in a memory”; see George, [0074]; “Defect verification data from the diversity set of candidate defects, any other set of verified defects, or a combination thereof, are mapped to the saved defect image patches as labeled defect data 171”; see George, [0077]; “a defect map is produced to show locations on the specimen suspected of having high probability of a defect”; see Sofer [0006]).
Regarding claim 20, George further teaches:
wherein the light radiated onto the substrate is light having a wavelength of about 270 nm to about 750 nm (i.e., “the illumination light includes wavelengths ranging from 260 nanometers to 950 nanometers”; see [0036]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over George in view of Samsung Semiconstory, Sofer, and OH et al. (KR 20210158195 A; cited previously; machine translation provided previously; hereinafter “OH”).
Regarding claim 7, the prior art applied to the preceding linking claim(s) teaches the features of the linking claim(s).
George does not explicitly disclose:
performing a second EDS test on the target substrate of the target spectrum image;
determining consistency of the target defect grade by comparing the target defect grade with the result of the second EDS test; and
training the defect detection model again based on the consistency of the target defect grade.
But OH teaches:
training a model by reinforcement learning using feedback as to whether the result of the defect determination according to the learning is correct (see translation p. 10, ¶ 1).
Since George teaches using EDS to establish the labels of defects (i.e., ground truth), it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify George in view of Samsung Semiconstory and Sofer, further in view of OH, by performing a second EDS test on the target substrate of the target spectrum image; determining consistency of the target defect grade by comparing the target defect grade with the result of the second EDS test; and training the defect detection model again based on the consistency of the target defect grade, as claimed. The rationale would be to verify the correctness of the result by comparing the model output with the ground truth to provide feedback for training the model.
Response to Arguments
The objections to the specification have been withdrawn in view of the amendment.
The amendment to the drawing has been considered. However, there is a remaining informality as indicated above.
The issue of claim objections has been considered. However, there are remaining informalities as indicated above.
The rejections under 35 USC 112(a) and (b) have been withdrawn in view of the amendment.
Applicant’s arguments regarding 35 USC 102/103 have been considered but are moot because a new ground has been found to address the argued features at issue, by further in view of Samsung Semiconstory, as indicated in the rejections above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOHN C KUAN/Primary Examiner, Art Unit 2857
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