DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/13/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e. a law of nature, a natural phenomenon, or an abstract idea) without significantly more. Claims 1-20 are directed to Mental Processes. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional computer elements, which are recited at a high level of generality, provide conventional computer functions that do not add meaningful limits to practicing the abstract ideas.
Claims 1 and 11 recites in part a system and method for determining performance of a computational storage device by obtaining execution time of a program and data retrieval time/latency of a storage medium. The limitation is directed to concepts performed in the human mind, via the use of generic computer components, such as Mental Processes (including an observation, evaluation, judgement, opinion). Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claims only recite additional elements such as processor, non-volatile storage medium, software program and application which are well-known parts of a generic computer. The generic computer components are recited at a high-level of generality (e.g. perform and action with respect to the program, retrieve data from the non-volatile medium) such that it amounts to no more than mere instruction to apply the exception using a generic computer component. Accordingly, this additional element does not integrate the abstract idea into a practical application because it does not impose any meaningful limits on practicing the abstract idea. The claim is directed to an abstract idea.
Next the claims as a whole are analyzed to determine whether any element, or combination of elements, is sufficient to ensure the claim amounts to significantly more than an abstract idea. The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception because the additional elements of processor, non-volatile storage medium, software program and application are merely additional elements performing the abstract idea on a generic device i.e., abstract idea and apply it. There is no improvement to computer technology or computer functionality MPEP 2106.05(a) nor a particular machine MPEP 2106.05(b) nor a particular transformation MPEP 2106.05(c). Given the above reasons, the additional elements of processor, non-volatile storage medium, software program and application are not Inventive Concepts. Thus, the claims are not patent eligible.
The dependent claims 2-10, and 12-20 have been given the full two-part analysis (Step 2A- 2 -prong tests and step 2B) including analyzing the additional limitations both individually and in combination. The Dependent claim(s) when analyzed both individually and in combination are also held to be patent ineligible under 35 U.S.C. 101 because for the same reasoning as above and the additional recited limitation(s) fail(s) to establish that the claim(s) is/are not directed to an abstract idea. The additional limitations of the dependent claim(s) when considered individually and as ordered combination do not amount to significantly more than the abstract idea.
Therefore, claims 1-20 are not drawn to eligible subject matter as they are directed to an abstract idea without significantly more.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Jones US 20220244960, and in view of Watts et al US 20140373024.
Regarding claim 1, Jones teaches a system (see figure 2) comprising:
a non-volatile storage medium (hard drives 132c-d); and
a processor coupled to the non-volatile storage medium (processor 120), the processor being configured to:
identify a program configured to be executed by a computational storage device (see para 0018, the native instruction set is allocated to instruction slots 118 to operate on the native instruction processor 120 to process data from the memory 130);
perform an action with respect to the program (see para 0018, the execution of the native instruction set of the CIS at the native instruction processor 120);
compute a first performance value based on performing the action with respect to the program (see para 0018, an execution monitor 124 monitors the execution of the native instruction set of the CIS at the native instruction processor 120 to collect various execution parameters of the CIS. For example, the execution monitor 124 may monitor (a) total execution time of the program);
retrieve data from the non-volatile medium (see para 0018, the native instruction processor 120 to process data from the memory 130).
But Jones fails to teach compute a second performance value based on retrieving the data from the non-volatile storage medium; and compute total performance of the computational storage device based on the first performance value and the second performance value.
However, Watts teaches a performance monitoring tool (see figure 2, performance monitoring tool 22) that compute a second performance value based on retrieving the data from a memory (see para 0020, the tool 22 can monitor the memory latency experienced by the modem CPU 4 when executing a memory access); and compute total performance of the computational storage device based on the first performance value and the second performance value (see figure 2, multiple performance parameters including execution time delta-T and latency are combined in a weighted sum).
Therefore, it would have been obvious to modify the performance monitoring of Jones and incorporate monitoring both execution time and latency.
The motivation for doing so is to provide more completed performance report based on both the processor’s execution time and the memory’s latency.
Regarding claim 2, Jones further teaches the processor is further configured to: receive a first command and a second command from an application (see para 0016, downloads one or more CIS from the host 150); and
translate the first command to a translated first command, and the second command to a translated second command (see para 0021, the optimized CIS is translated to native instruction set before being allocated to native instruction slots 118), wherein the processor is configured to perform the action with respect to the program based on the translated first command, and the processor is configured to retrieve the data from the non-volatile storage medium based on the translated second command (see para 0018, the native instruction set is allocated to instruction slots 118 to operate on the native instruction processor 120 to process data from the memory 130).
Regarding claim 3, Jones further teaches the first command and the second command are based on a first interface for communicating with the computational storage device (see figure 2, NVMe interface 140), and the translated first command and the translated second command are based on a second interface for communicating with the computational storage device (CIS translator interface 218).
Regarding claim 4, Jones further teaches the non-volatile storage medium includes a solid state drive (see para 0014, the CSD 102 may include a memory 130 implemented using hard disc drives (HDDs), solid state drives (SSDs), hybrid drives, etc. In the illustrated implementation, the memory 130 is implemented using HDDs 132 a-132 c (HDDs 132)).
Regarding claim 5, Jones further teaches the processor being configured to perform the action with respect to the program includes the processor being configured to: receive the program from an application (see para 0016, downloads one or more CIS from the host 150); execute the program; and measure an execution time for the program, wherein the first performance value includes the execution time (see para 0018, an execution monitor 124 monitors the execution of the native instruction set of the CIS at the native instruction processor 120 to collect various execution parameters of the CIS. For example, the execution monitor 124 may monitor (a) total execution time of the program).
Regarding claim 6, Jones further teaches the processor being configured to perform the action with respect to the program includes the processor being configured to: receive the program from an application (see para 0016, downloads one or more CIS from the host 150); identify latency information associated with the computational storage device; and determine an execution time of the program based on the latency information, wherein the first performance value includes the execution time (see para 0013, using a computational instruction set (CIP) such as enhanced Berkeley Packet Filter (eBPF) within the CSD and profiling the performance of the CIP to generate one or more CIP execution parameters. In example implementations, these parameters may include, for example, (a) total execution time of the program).
Regarding claim 7, Jones further teaches the processor is further configured to: transmit a signal to the application based on detecting a criterion associated with the execution time (see para 0026, an operation 412 communicates the execution parameters to the host).
Regarding claim 8, Jones further teaches the latency information includes data processing latency of at least one of an ARM processor, field-programmable gate array (FPGA), or graphics processing unit (GPU) (see para 0013, the native instruction set of the computational storage processors such as ARM, RISC-V, etc).
Regarding claim 9, Jones further teaches the first performance value includes at least one of command processing latency, message passing latency, hardware access latency, or memory access latency (see para 0018, a) total execution time of the program e.g. the command processing latency/time).
Regarding claim 10, Jones further teaches transmit a command to the non-volatile storage medium to retrieve the data (see para 0018, the native instruction set is allocated to instruction slots 118 to operate on the native instruction processor 120 to process data from the memory 130).; and
Watts further teaches measure a latency in retrieving the data based on the command (see para 0020, the tool 22 can monitor the memory latency experienced by the modem CPU 4 when executing a memory access).
Regarding claim 11, Jones teaches a method comprising:
identifying a program configured to be executed by a computational storage device (see para 0018, the native instruction set is allocated to instruction slots 118 to operate on the native instruction processor 120 to process data from the memory 130);
performing an action with respect to the program (see para 0018, the execution of the native instruction set of the CIS at the native instruction processor 120);
computing a first performance value based on performing the action with respect to the program (see para 0018, an execution monitor 124 monitors the execution of the native instruction set of the CIS at the native instruction processor 120 to collect various execution parameters of the CIS. For example, the execution monitor 124 may monitor (a) total execution time of the program);
retrieving data from a non-volatile storage medium (see para 0018, the native instruction processor 120 to process data from the memory 130);
But Jones fails to teach computing a second performance value based on retrieving the data from the non-volatile storage medium; and computing total performance of the computational storage device based on the first performance value and the second performance value.
However, Watts teaches a performance monitoring tool (see figure 2, performance monitoring tool 22) that compute a second performance value based on retrieving the data from a memory (see para 0020, the tool 22 can monitor the memory latency experienced by the modem CPU 4 when executing a memory access); and compute total performance of the computational storage device based on the first performance value and the second performance value (see figure 2, multiple performance parameters including execution time delta-T and latency are combined in a weighted sum).
Therefore, it would have been obvious to modify the performance monitoring of Jones and incorporate monitoring both execution time and latency.
The motivation for doing so is to provide more completed performance report based on both the processor’s execution time and the memory’s latency.
Regarding claims 12-20, please refer to the rejections of claims 2-10 above since the claimed subject matter is substantially similar.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Dwivedi et al US 20240378094 discloses profiling and performance monitoring of distributed computational pipelines
Park et al US 20170024316 discloses a processor workload profiler to monitor instruction execution time and a cache demand profiler to monitor memory access latency
Walker et al US 20150052241 discloses computer system productivity monitoring including disk access latency and processor usage
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/PHONG H DANG/Primary Examiner, Art Unit 2184