Attorney’s Docket Number: Q287208
Filing Date: 9/13/2023
Claimed Foreign Priority Date: 2/3/2023 (KR 10-2023-0014780)
Applicant: Kim
Examiner: Rianna B. Greer
DETAILED ACTION
This Office Action responds to the application filed on 9/13/2023.
Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The application serial no. 18/367,851 filed on 9/13/2023 has been entered. Pending in this Office Action are claims 1-20.
Specification
The abstract of the disclosure is objected to because the abstract exceeds 150 words in length. A corrected abstract of the disclosure is required and must be presented on a separate sheet, apart from any other text. See MPEP § 608.01(b).
The disclosure is objected to because of the following informalities:
In Par. [0005], “One or more embodiments of the present disclosure provide a semiconductor device that may have improved power, performance, area, and cost (PPAC) are provided.” should read --One or more embodiments of the present disclosure provide a semiconductor device that may have improved power, performance, area, and cost (PPAC) .--
In Par. [0055], “The ferroelectric material film may further include a doped dopant.” should read --The ferroelectric material film may further include a
In Par. [0059], “The paraelectric material film may have the paraelectric properties.” should read --The paraelectric material film may have
In Par. [0070], the specification reads “For example, the source/drain region 160 may be an epitaxial pattern formed by an epitaxial growth process. As shown in FIG. 2, the cross-section of each of a plurality of the source/drain region 160 intersecting the first direction X may be pentagonal, but this is merely an example.” However, the cross-section featured in FIG. 2 is hexagonal. The specification and drawings should be consistent.
In Par. [0129], “The anisotropic deposition processes may include, for example, but is not limited to, a high density plasma chemical vapor deposition (HDPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) processes or a physical vapor deposition process.” should read --The anisotropic deposition processes may include, for example, but is not limited to, a high density plasma chemical vapor deposition (HDPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process or a physical vapor deposition process.--
Appropriate corrections are required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Seo et al. (US2024/0243064).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Seo (see Figs. 3B-3C) shows all aspects of the instant invention including a semiconductor device comprising:
a substrate (e.g., substrate 102) comprising a first side and a second side opposite to the first side
an active pattern (e.g., fin-type active regions F1) that is on the first side and extends in a first direction (e.g., X direction)
an etch stop layer (e.g., etch stop film 182) that extends along the first side of the substrate and does not extend along side faces of the active pattern
a field insulating film (e.g., device isolation film 112) that is on the first side and covers at least a part of the side faces of the active pattern
a gate structure (e.g., gate lines 160) that extends in a second direction intersecting the first direction on the active pattern and the field insulating film (e.g., Y direction)
a through contact (e.g., via power rail VPR) that extends in a third direction (e.g., Z direction) intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer
a buried pattern (e.g., backside power rail BPW) connected to the through contact, inside the substrate
a backside wiring structure that is on the second side and electrically connected to the buried pattern (see, e.g., Par. [0090]: backside surface 102B and BPW may be covered by a backside wiring structure (not shown))
Regarding Claim 3, Seo shows that the field insulating film may comprise a silicon oxide layer (see, e.g., Par. [0043]: 112 may include a silicon oxide film), and wherein the etch stop layer may comprise at least one from among a silicon nitride layer, a silicon carbonitride layer, a silicon boron carbonitride layer, a silicon oxycarbide layer, and an aluminum oxide layer (see, e.g., Par. [0080]: 182 may include silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), silicon oxycarbide (SiOC), aluminum oxide (AlO), or a combination thereof).
Regarding Claim 9, Seo (see, e.g., Fig. 3B) shows that at least a part of the field insulating film (e.g., 112) is between the substrate (e.g., 102) and the etch stop layer (e.g., 182).
Claims 1, 3, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kim et al. (US2024/0213119).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Kim (see Figs. 3B-3C) shows all aspects of the instant invention including a semiconductor device comprising:
a substrate (e.g., substrate 102) comprising a first side and a second side opposite to the first side
an active pattern (e.g., fin-type active regions F1) that is on the first side and extends in a first direction (e.g., X direction)
an etch stop layer (e.g., etch stop film 182) that extends along the first side of the substrate and does not extend along side faces of the active pattern
a field insulating film (e.g., device isolation film 112) that is on the first side and covers at least a part of the side faces of the active pattern
a gate structure (e.g., gate lines 160) that extends in a second direction intersecting the first direction on the active pattern and the field insulating film (e.g., Y direction)
a through contact (e.g., via power rail VPR) that extends in a third direction (e.g., Z direction) intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer
a buried pattern (e.g., backside power rail BPW) connected to the through contact, inside the substrate
a backside wiring structure that is on the second side and electrically connected to the buried pattern (e.g., backside wiring structure BWS)
Regarding Claim 3, Kim shows that the field insulating film may comprise a silicon oxide layer (see, e.g., Par. [0037]: 112 may include, for example, a silicon oxide film), and wherein the etch stop layer may comprise at least one from among a silicon nitride layer, a silicon carbonitride layer, a silicon boron carbonitride layer, a silicon oxycarbide layer, and an aluminum oxide layer (see, e.g., Par. [0070]: 182 may include silicon nitride (SiN), nitrogen-doped silicon carbide (SiC:N), silicon oxycarbide (SiOC), aluminum oxide (AlO), or a combination thereof).
Regarding Claim 9, Kim (see, e.g., Fig. 3B) shows that at least a part of the field insulating film (e.g., 112) is between the substrate (e.g., 102) and the etch stop layer (e.g., 182).
Claims 1, 3, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lee et al. (US2024/0222450).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Lee (see Figs. 3, 4) shows all aspects of the instant invention including a semiconductor device comprising:
a substrate (e.g., first substrate 100) comprising a first side and a second side opposite to the first side
an active pattern (e.g., first and second lower patterns BP1/BP2) that is on the first side and extends in a first direction (e.g., X direction)
an etch stop layer (e.g., source/drain etch stop film 185) that extends along the first side of the substrate and does not extend along side faces of the active pattern
a field insulating film (e.g., field filling film 106) that is on the first side and covers at least a part of the side faces of the active pattern
a gate structure (e.g., gate electrode 120) that extends in a second direction intersecting the first direction on the active pattern and the field insulating film (e.g., Y direction)
a through contact (e.g., contact connection via 180) that extends in a third direction (e.g., Z direction) intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer
a buried pattern (e.g., buried conductive pattern 70) connected to the through contact, inside the substrate
a backside wiring structure that is on the second side and electrically connected to the buried pattern (e.g., rear wiring line 50)
Regarding Claim 3, Lee shows that the field insulating film may comprise a silicon oxide layer (see, e.g., Par. [0059]: 106 may include or may be formed of, for example, silicon oxide), and wherein the etch stop layer may comprise at least one from among a silicon nitride layer, a silicon carbonitride layer, a silicon boron carbonitride layer, a silicon oxycarbide layer, and an aluminum oxide layer (see, e.g., Par. [0102]: 185 may include or may be formed of, for example, at least one of silicon nitride, silicon oxycarbide, and a combination thereof).
Regarding Claim 9, Lee (see, e.g., Fig. 4) shows that at least a part of the field insulating film (e.g., 106) is between the substrate (e.g., 100) and the etch stop layer (e.g., 185).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8, and 11-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US2024/0136254) in view of Lan et al. (US2024/0021708).
The applied reference has a common assignee with the instant application. Based upon the earlier effectively filed date of the reference, it constitutes prior art under 35 U.S.C. 102(a)(2). This rejection under 35 U.S.C. 102(a)(2) might be overcome by: (1) a showing under 37 CFR 1.130(a) that the subject matter disclosed in the reference was obtained directly or indirectly from the inventor or a joint inventor of this application and is thus not prior art in accordance with 35 U.S.C. 102(b)(2)(A); (2) a showing under 37 CFR 1.130(b) of a prior public disclosure under 35 U.S.C. 102(b)(2)(B) if the same invention is not being claimed; or (3) a statement pursuant to 35 U.S.C. 102(b)(2)(C) establishing that, not later than the effective filing date of the claimed invention, the subject matter disclosed in the reference and the claimed invention were either owned by the same person or subject to an obligation of assignment to the same person or subject to a joint research agreement.
Regarding Claim 1, Kang (see, e.g., Figs. 3B-3C) shows most aspects of the instant invention including a semiconductor device comprising:
- a substrate (e.g., substrate 102) comprising a first side and a second side opposite to the first side
- an active pattern (e.g., fin-type active regions F1) that is on the first side and extends in a first direction (e.g., X direction)
- an etch stop layer (e.g., insulating stopper 106) that extends along the first side of the substrate and does not extend along side faces of the active pattern
- a field insulating film (e.g., device isolation film 112) that is on the first side and covers at least a part of the side faces of the active pattern
- a gate structure (e.g., gate lines 160) that extends in a second direction (e.g., Y direction) intersecting the first direction on the active pattern and the field insulating film
- a through contact (e.g., via power rail VPR) that extends in a third direction (e.g., Z direction) intersecting the first direction and the second direction and penetrates the field insulating film and the etch stop layer
- a buried pattern (e.g., backside power rail BPW) connected to the through contact, inside the substrate
However, Kang is silent about a backside wiring structure that is on the second side and electrically connected to the buried pattern. Lan (see, e.g., Fig. 2T and Par. [0105], [0111]-[0115], [0120]), on the other hand and in the same field of endeavor, teaches that interconnection structures 252/256 can be formed on the backside of a semiconductor device and electrically connect to a buried power rail 246 thereof, to enable transistor functionality through providing bias to its source/drain regions 138.
Accordingly, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to have a backside wiring structure on the second side and electrically connected to the buried pattern in the structure of Kang, because backside wiring structures are known in the semiconductor art for providing bias to the source/drain regions of transistors, as suggested by Lan, and implementing a known electrical connection arrangement for its conventional use would have been a common sense choice by the skilled artisan. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
Regarding Claim 2, Kang (see, e.g., Fig. 3B) shows that the etch stop layer (e.g., 106) is interposed between the substrate (e.g., 102) and the field insulating film (e.g., 112).
Regarding Claim 3, Kang shows that the field insulating film may comprise a silicon oxide layer (see, e.g., Par. [0036]: 112 may include a silicon oxide film), and wherein the etch stop layer may comprise at least one from among a silicon nitride layer, a silicon carbonitride layer, a silicon boron carbonitride layer, a silicon oxycarbide layer, and an aluminum oxide layer (see, e.g., Par. [0039]: 106 may include a silicon nitride film).
Regarding Claim 4, Kang (see, e.g., Par. [0043]) shows that the thickness of the etch stop layer must be such that both VPR and BPW pass at least through a portion of the etch stop structure ES in the vertical direction (Z direction) without either of them completely passing through said ES. Therefore, Kang implicitly recognizes the thickness of the etch stop layer as a result effective variable. Accordingly, the specific thickness of the etch stop layer claimed by the applicant, i.e., a thickness of 1 nm to 100 nm, is only considered to be the “optimum” etch stop layer thickness disclosed by Kang that a person having ordinary skill in the art would have been able to obtain using routine experimentation based on ES materials, etching chemistry used to form openings for VPR and BPW, etc. (see In re Boesch, 205 USPQ 215 (CCPA 1980)), and since neither non-obvious nor unexpected results, i.e., results which are different in kind and not in degree from the results of the prior art, will be obtained so long as an etch stop layer is formed to enable depth control during the formation of openings for through vias, as already suggested by Kang in Par. [0078]. Therefore, Kang in view of Lan also shows that the etch stop layer has a thickness of 1 nm to 100 nm.
Regarding Claim 5, Kang (see, e.g., Fig. 3B) shows that the semiconductor device further comprises an epitaxial liner film (e.g., insulating liner 104) extending along the first side of the substrate (e.g., 102) and the side faces of the active pattern (e.g., F1).
Regarding Claim 6, Kang (see, e.g., Fig. 3B) shows that the epitaxial liner film (e.g., 104) is between the substrate (e.g., 102) and the etch stop layer (e.g., 106).
Regarding Claim 8, Kang shows that the epitaxial liner film (e.g., 104) comprises a silicon layer (see, e.g., Par. [0039]: 104 may include a crystalline silicon film).
Regarding Claim 11, Kang (see, e.g., Figs. 3B-3C, 6) shows most aspects of the instant invention including a semiconductor device comprising:
- a substrate (e.g., substrate 102) comprising a first side and a second side opposite to the first side
- an active pattern (e.g., fin-type active regions F1) that is on the first side and extends in a first direction (e.g., X direction)
- a field insulating film (e.g., device isolation film 112) that is on the first side and covers at least a part of the side faces of the active pattern
- an etch stop layer (e.g., insulating stopper 106) that is between the substrate and the field insulating film and not between the active pattern and the field insulating film
- a gate structure (e.g., gate lines 160) that extends in a second direction (e.g., Y direction) intersecting the first direction, on the active pattern and the field insulating film
- a through contact (e.g., via power rail VPR) that extends in a third direction (e.g., Z direction) intersecting the first direction and the second direction, and penetrates the field insulating film and the etch stop layer
- a buried pattern (e.g., backside power rail BPW) connected to the through contact, inside the substrate
However, Kang is silent about a backside wiring structure that is on the second side and electrically connected to the buried pattern. Lan (see, e.g., Fig. 2T and Par. [0105], [0111]-[0115], [0120]), on the other hand and in the same field of endeavor, teaches that interconnection structures 252/256 can be formed on the backside of a semiconductor device and electrically connect to a buried power rail 246 thereof, to enable transistor functionality through providing bias to its source/drain regions 138. See comments stated above in Par. 27 with regards to Claim 1, which are considered repeated here.
Regarding Claim 12, Kang (see, e.g., Figs. 3B-3C, 6) shows a semiconductor device further comprising a source/drain region (e.g., source/drain region 130) connected to the active pattern (e.g., F1) on side faces of the gate structure (e.g., 160), wherein the through contact (e.g., VPR) is electrically connected to the source/drain region.
Regarding Claim 13, Kang (see, e.g., Fig. 6) shows a semiconductor device further comprising a frontside wiring structure that is on the first side and electrically connected to the source/drain region (e.g., 130) or the gate structure (e.g., 160) (see, e.g., Pars. [0088], [0090]: a source/drain contact CA4 may be formed on a source/drain region 130 and may be electrically connectable to a front-side wiring structure located over a plurality of upper wiring layers M1).
Regarding Claim 14, Kang (see, e.g., Fig. 3B) shows that a width of the through contact (e.g., VPR) decreases toward the buried pattern (e.g., BPW), and that a width of the buried pattern decreases toward the through contact.
Regarding Claim 15, Kang (see, e.g., Figs. 3B-3C) shows that the buried pattern (e.g., BPW) extends in the first direction (e.g., X direction).
Regarding Claim 16, Kang (see, e.g., Figs. 3B-3C, 6) shows most aspects of the instant invention including a semiconductor device comprising:
- a substrate (e.g., substrate 102) comprising a first side and a second side that is opposite to the first side
- an active pattern (e.g., fin-type active regions F1) that is on the first side and extends in a first direction (e.g., X direction)
- an epitaxial liner film (e.g., insulating liner 104) extending along the first side of the substrate and side faces of the active pattern
- an etch stop layer (e.g., insulating stopper 106) that extends, on the epitaxial liner film, along the first side and does not extend along the side faces of the active pattern
- a field insulating film (e.g., device isolation film 112) that is on the etch stop layer and covers at least a part of the side faces of the active pattern
- a gate structure (e.g., gate lines 160) that extends on the active pattern and the field insulating film in a second direction (e.g., Y direction) intersecting the first direction
- a source/drain region (e.g., source/drain region 130) connected to the active pattern on the side faces of the gate structure
- a frontside wiring structure that is on the first side and electrically connected to the source/drain region or the gate structure (see, e.g., Pars. [0088], [0090]: a source/drain contact CA4 may be formed on a source/drain region and may be electrically connectable to a front-side wiring structure located over a plurality of upper wiring layers M1)
- a through contact (e.g., via power rail VPR) that is electrically connected to the source/drain region, and penetrates the field insulating film and the etch stop layer
- a buried pattern (e.g., backside power rail BPW) connected to the through contact, inside the substrate
However, Kang is silent about a backside wiring structure that is on the second side and electrically connected to the buried pattern. Lan (see, e.g., Fig. 2T and Par. [0105], [0111]-[0115], [0120]), on the other hand and in the same field of endeavor, teaches that interconnection structures 252/256 can be formed on the backside of a semiconductor device and electrically connect to a buried power rail 246 thereof, to enable transistor functionality through providing bias to its source/drain regions 138. See comments stated above in Par. 27 with regards to Claim 1, which are considered repeated here.
Regarding Claim 17, Kang (see, e.g., Fig. 3C) shows that the active pattern comprises a plurality of bridge patterns which are sequentially stacked on the substrate and spaced apart from each other (e.g., nanosheet stacks NSS), and wherein each of the plurality of bridge patterns extends in the first direction (e.g., X direction) and penetrates the gate structure (e.g., 160).
Regarding Claim 18, Lan (see, e.g., Fig. 2T) shows that the backside wiring structure is configured to apply a power supply voltage to the source/drain region (e.g., source/drain regions 138) through the buried pattern (e.g., conductive feature 250) and the through contact (e.g., conductive structure 246).
Regarding Claim 19, Kang (see, e.g., Fig. 6) shows a semiconductor device further comprising a source/drain contact (source/drain contact CA4) that is on the source/drain region (e.g., 130) and connects the source/drain region and the frontside wiring structure (see, e.g., Pars. [0088], [0090]: a source/drain contact CA4 may be formed on a source/drain region and may be electrically connectable to a front-side wiring structure located over a plurality of upper wiring layers M1).
Regarding Claim 20, Kang (see, e.g., Fig. 6) shows that the through contact (e.g., VPR) connects the frontside wiring structure and the buried pattern (e.g., BPW) (see, e.g., Pars. [0088], [0090]: a source/drain contact CA4 may be formed on a source/drain region connected to a via power rail and may be electrically connectable to a front-side wiring structure located over a plurality of upper wiring layers M1).
Allowable Subject Matter
Claims 7 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional references cited disclose transistor structures comprising a through contact and an etch-stop, and having arrangements of features similar to the instant inventions.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Rianna B. Greer whose telephone number is (571) 272-7985. The examiner can normally be reached Monday - Friday, 8 AM - 6 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached at (571) 272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/R.B.G./Examiner, Art Unit 2814
/WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814