Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 6, 9, 12, 16, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US Patent No. 20170250138) in view of Gan et al (US Patent No. 20120168942 A1).
Regarding claims 1 and 12, Hsieh et al. disclose a first circuit structure (160) disposed at the top surface of the encapsulation layer (paragraph 24); a second circuit structure (110) disposed at the bottom surface of the encapsulation layer 130 (paragraph 16, Fig. 15) and a connecting structure disposed in the at least one opening (Fig 5, 112), wherein the at least one electronic element is electrically connected to the second circuit structure (Fig. 5 110) through the first circuit structure (Fig. 20, 160) and the connecting structure (Fig. 5, 112).
However, Hsieh et al. do not disclose the connecting structure includes a first sub layer and a second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the at least one opening.
On the other hand, Gan et al. disclose the connecting structure includes a first sub layer (40) and a second sub layer (44), the first sub layer is located between the encapsulation layer (58) and the second sub layer, and the first sub layer covers the sidewall of the at least one opening (Fig. 3, paragraph 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the above references according to the teachings of Gan et al. such that the connecting structure includes a first and second sub layer, the first sub layer is located between the encapsulation layer and the second sub layer, and the first sub layer covers the sidewall of the opening. Doing so would allow the first sub layer to act as a seed layer for the second sub layer, provide electrical connection and routing, and insulation.
Regarding claims 6, 16, Hsieh et al. disclose an electronic device comprising a bonding element (116) disposed at a surface of the second circuit structure (110) (Fig. 25) opposite to the at least one electronic element (paragraph 63).
Regarding claims 9, 18, Hsieh et al. disclose an electronic device, wherein the first circuit structure comprises a first conductive layer contacts the top surface of the encapsulation layer (Fig. 19, paragraph 24), and the second circuit structure comprises a second conductive layer contacts the bottom surface of the encapsulation layer (Fig. 19, paragraph 16).
Claim(s) 2-3, 4-5, 13, 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US Patent No. 20170250138) and Gan et al (US Patent No. 20120168942 A1) as applied to claim 1 above, and further in view of Takemura et al. (US Patent No. 20170077043 A1).
Regarding claims 2, 3, and 13, Hsieh and Gan fail to disclose a first insulating layer disposed on a top surface of the at least one electronic element and a second insulating layer disposed on the first insulating layer, wherein a thickness of the second insulating layer is greater than a thickness of the first insulating layer.
However, regarding claims 2-3, Takemura et al. disclose a first insulating layer disposed on a top surface of the at least one electronic element (paragraph 19) and a second insulating layer disposed on the first insulating layer (paragraph 19).
However, regarding claim 13, Takemura does not disclose the thickness of the second insulating layer is greater than a thickness of the first insulating layer, but it does mention the first insulating film have a thickness of 1 to 20 μm, the second insulating film have a thickness of 5 to 100 μm, the third insulating film have a thickness of 5 to 100 μm, and the semiconductor apparatus have a thickness of 50 to 300 μm (paragraph 24).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Takemura et al. such that the thickness of the second insulating layer is greater than the thickness of the first insulating layer based on the provide ranges of Takemura et al. to provide better electrical isolation and thermal management.
Regarding claims 4-5, 14-15, Takemura et al. disclose the thickness of the first insulating layer ranges from 0.5 micrometers to 3 micrometers and the thickness of the second insulating layer ranges from 5 micrometers to 25 micrometers (paragraph 24).
Claim(s) 7, 10-11, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US Patent No. 20170250138) and Gan et al (US Patent No. 20120168942 A1) as applied to claims 1, 6, 9, 12, 18 above, and further in view of Jo et al. (US Patent No. 20190267351 A1).
Regarding claim 7, Hsieh and Gan do not disclose the bonding element is disposed misaligned with the at least one opening in a top view direction of the electronic device.
However, Jo et al disclose misaligned solder balls (2170, Fig. 7) and with a via (2143, Fig 7).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the arts cited above so that the bonding element is disposed misaligned with the at least one opening in a top view to simplify manufacturing.
Regarding claims 10 and 19, Hsieh, and Gan do not disclose the first conductive layer and the second conductive layer are overlapped with the at least one opening of the encapsulation layer in a top view direction of the electronic device.
However, Jo et al. disclose the first conductive layer (Fig. 9, 142) and the second conductive layer (Fig. 9, 152a) are overlapped with the at least one opening (Fig. 9, 161) of the encapsulation layer in a top view direction of the electronic device (Fig 9, paragraph 64).
Regarding claims 11 and 20. Hsieh and Gan do not disclose one of the first conductive layer and the second conductive layer is disposed in the at least one opening of the encapsulation layer and contacts another one of the first conductive layer and the second conductive layer.
However, Jo et al. disclose a first connection via 161 penetrating through the second encapsulant 131 and electrically connecting the first redistribution layer 142 and the second redistribution layer 152a (paragraph 64, Fig. 9)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the above references according to the teachings of Jo et al. such that the opening connects the first and second conductive layers. Doing so would enable vertical signal and power to flow between the layers.
Claim(s) 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hsieh et al. (US Patent No. 20170250138) and Gan et al (US Patent No. 20120168942 A1) as applied to claim 1, 12 above, and further in view of Ting et al. (US Patent No. 20230129218 A1).
Regarding claims 8, 17, Hsieh and Gan do not disclose the sidewall of the at least one opening has a rough surface.
However, Ting et al. disclose the sidewall of the at least one opening has a rough surface (Fig. 3, paragraph 37).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the references above according to the teachings of Ting et al. such that the sidewall of the opening has a rough surface. Doing so would alter ion trajectories, helping to prevent over-etching at certain angles.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817