Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “differential input/output” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 10 is objected to because of the following informalities:
Regarding claim 10, “claim 1” should correctly be “claim 9”. Note, claim 10 is a method claim and should be depended on method claim 9.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 9 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 1 and 9, which disclose an amplifying device for processing a differential input signal and providing a differential output signal. As it is well known in the art “differential input/output …” means “two inputs/outputs”, wherein applicant’s submitted drawings only disclose single input and single output. Therefore, it is not clear if this was a mistake. However, if it was not a mistake, it is suggested applicant needs to provide a drawing(s) that clearly show differential input/output signal as claimed. Clarification is needed.
Regarding claims 2-8 and 10 are rejected due to their dependency on rejected independent claims 1 and 9.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 8 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Khlat et al. (10,944,365), hereafter called KHLAT.
Regarding claims 1 and 9, KHLAT (Figs. 1B and 2) discloses an audio signal (72) amplifier circuit comprising: amplifying device (58) configured to process a differential input signal (70) and thereby generate a differential output signal (72), which can be a differential output signal, the audio signal amplifying device comprising: a signal detection circuit (read on blocks 86 and 76 (square-root)) configured to detect a variation in an amplitude of the differential input signal and thereby generate a detection result (62); a voltage supply circuit (60) configured to output one of multiple voltages (VCC and V’CC, also Fig. 1B) as a supply voltage according to the detection result, wherein when the detection result indicates that the amplitude of the differential input signal satisfies a first condition, the supply voltage (VCC) is a first voltage of the multiple voltages, and when the detection result indicates that the amplitude of the input signal satisfies a second condition, the supply voltage is a second voltage (V’CC) of the multiple voltages lower than the first voltage; and an amplifying circuit (80) configured to receive the supply voltage, then process the differential input signal according to the supply voltage, and then generate the differential output signal, wherein the amplitude of the differential input signal satisfying the first condition is a first amplitude, the amplitude of the differential input signal satisfying the second condition is a second amplitude, and the first amplitude (VCC) is greater than the second amplitude (V’CC), also see column 6, lines 13-26 and column 8 line 10 to column 9, line 24.
Regarding claim 2, wherein the signal detection circuit is an envelope detection circuit, see ABSTRACT.
Regarding claim 8, wherein claimed subject matter is considered an intended use of the invention, which the reference circuit can be used in combination with another circuit, such as playback device in wireless communication.
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Leung et al. (11,658,764), hereafter called LEUNG.
Regarding claims 1 and 9, LEUNG (Figs. 2 and 6) disclose an audio signal amplifier circuit comprising: amplifying device (200) configured to process an input signal (VRFI) and thereby generate an output signal (VRFA), the audio signal amplifying device comprising: a signal detection circuit (232) configured to detect a variation in an amplitude of the input signal and thereby generate a detection result (Vp); a voltage supply circuit (240) configured to output one of multiple voltages (VDD1-VDDN and also Fig. 6) as a supply voltage according to the detection result, wherein when the detection result indicates that the amplitude of the differential input signal satisfies a first condition, the supply voltage (VDD1) is a first voltage of the multiple voltages, and when the detection result indicates that the amplitude of the input signal satisfies a second condition, the supply voltage is a second voltage (VDD2) of the multiple voltages lower than the first voltage; and an amplifying circuit (222) configured to receive the supply voltage, then process the input signal according to the supply voltage, and then generate the output signal, wherein the amplitude of the input signal satisfying the first condition is a first amplitude, the amplitude of the differential input signal satisfying the second condition is a second amplitude, and the first amplitude (VDD2 is 1.2V) is greater than the second amplitude (VDD1 is 0.8V).
Allowable Subject Matter
Claims 3-5 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, prior art(s) does not disclose the envelope detection circuit comprises: an envelope detector configured to output a detection signal according to the variation in the amplitude of the differential input signal; and a mapping circuit configured to store multiple preselected results and to output one of the multiple preselected results as the detection result in accordance with the detection signal.
Regarding claim 4, prior art(s) does not disclose the envelope detection circuit comprises: an envelope detector configured to output a detection signal according to the variation in the amplitude of the differential input signal; and a comparison circuit configured to compare the detection signal with at least one reference signal and thereby generate the detection result.
Regarding claim 5, prior art(s) does not disclose the voltage supply circuit comprises: a first voltage terminal configured to provide the first voltage; a second voltage terminal configured to provide the second voltage; a first switch coupled between the first voltage terminal and the amplifying circuit, the first switch configured to be turned on when the detection result indicates that the amplitude of the differential input signal satisfies the first condition, and configured to be turned off when the detection result indicates that the amplitude of the differential input signal satisfies the second condition; and a second switch coupled between the second voltage terminal and the amplifying circuit, the second switch configured to be turned off when the detection result indicates that the amplitude of the differential input signal satisfies the first condition, and configured to be turned on when the detection result indicates that the amplitude of the differential input signal satisfies the second condition.
Regarding claim 6, prior art(s) does not disclose a common-mode voltage modulation circuit configured to output one of multiple reference voltages as a common-mode voltage to the amplifying circuit in accordance with the detection result, wherein when the detection result indicates that the amplitude of the differential input signal satisfies the first condition, the common-mode voltage is a first reference voltage of the multiple reference voltages; when the detection result indicates that the amplitude of the differential input signal satisfies the second condition, the common-mode voltage is a second reference voltage of the multiple reference voltages; and the second reference voltage is lower than the first reference voltage.
Regarding claims 7 and 10, prior art(s) does not disclose the common-mode voltage modulation circuit comprises: a first reference voltage terminal configured to provide the first reference voltage; a second reference voltage terminal configured to provide the second reference voltage; a first switch coupled between the first reference voltage terminal and the amplifying circuit, the first switch configured to be turned on when the detection result indicates the 11 amplitude of the differential input signal satisfies the first condition, and configured to be turned off when the detection result indicates the amplitude of the differential input signal satisfies the second condition; and a second switch coupled between the second reference voltage terminal and the amplifying circuit, the second switch configured to be turned off when the detection result indicates the amplitude of the differential input signal satisfies the first condition, and configured to be turned on when the detection result indicates the amplitude of the differential input signal satisfies the second condition.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843