Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2-4, 6, 8-9 is/are rejected under 35 U.S.C 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1) and Matsuura et al. (US 20220223456 A1).
Regarding claim 1, Lee et al. disclose a semiconductor package (200B) comprising a redistribution structure (203a and 203b) on the package body layer (paragraph 26, Fig. 3); and alignment marks (150) on the redistribution structure (203a) in a plan view (Fig. 1).
However, Lee et al do not disclose a base structure having a fan-in area and fan-out areas surrounding the fan-in area; a semiconductor chip in the fan-in area; a package body layer in the fan-in area and the fan-out areas, the package body layer covering the semiconductor chip;
On the other hand, Lai et al. disclose a semiconductor package having a fan-in area (1061) and fan-out areas (1060) surrounding the fan-in area (paragraph 44, Fig1A-1); a semiconductor die (120) are disposed in the fan-in area (1061) (paragraph 48), and a molding compound (140) encapsulating the semiconductor die (120) (paragraph 61, Fig 1G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. such that the semiconductor package has fan-in and fan-out areas, and the package is covered by a molding layer. Doing so would enable direct chip connection, enable higher I/O density, and protect the chip from environmental factors.
Neither Lee et al. nor Lai et al. do not disclose each of the alignment marks comprises a plurality of metal layers.
On the other hand, Matsuura et al. disclose alignment mark (P) is comprised of metal layer (18) (paragraph 30, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. and Matsuura et al. such that the alignment marks have a plurality of metal layers. Doing so would allow the metal layers to function as an etching stopper and an antireflection to the metal foil (Matsuura, paragraph 45).
None of the references above disclose a plurality of auxiliary patterns are in the upper redistribution structure under the alignment marks to assist in recognition of the alignment marks.
However, Lee et al. disclose alignment marks (150-1, 150-2, 150-3, and 150-4) (Fig 6-9) are applicable to the arrangement of alignment marks (150a) of Fig. 4 and 5 (paragraph 113). This means alignment marks (150a) may be formed on the upper redistribution structure (203) (paragraph 88). Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above such that the auxiliary patterns are in upper redistribution under the alignment marks. Doing so would enable robust, multi-level alignment references to ensure better contrast and redundancy.
Regarding claim 2, Lee et al. disclose the plurality of auxiliary patterns (MP) comprise a plurality of sub auxiliary patterns (130) apart from one another in an X direction and a Y direction perpendicular to the X direction in the plan view (paragraph 29, Fig. 2)
Regarding claim 3, Lee et al. disclose the plurality of auxiliary patterns (MP) comprise a plurality of redistribution pattern in a transparent redistribution insulating layer (203b) in the plan view (paragraph 28, Fig. 2).
Regarding claim 4, Lee et al. disclose the base structure (200B) comprises a lower redistribution structure (201), and wherein the redistribution structure comprises an upper redistribution structure (203) (paragraph 43).
Regarding claim 6, Lee et al. does not disclose each of the alignment marks comprises a triple metal layer or a double metal layer.
However, Matsuura et al. disclose the alignment marks (P) comprises of two metal layers (18a and 18b) (paragraph 44, Fig. 2)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Matsuura et al. such that the alignment marks contain two or more metal layers. Doing so would allow the metal layers to function as an etching stopper and an antireflection to the metal foil (Matsuura, paragraph 45).
Regarding claim 8, Lee et al disclose each of the alignment marks (150) is in the redistribution structure (203) (paragraph 61).
Regarding claim 9, Lee et al. disclose each of the alignment marks (150a) is on the redistribution structure (203) (paragraph 106).
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1) and Matsuura et al. (US 20220223456 A1) as applied to claim 1 above, in further view of Lin (US 20160118333 A1).
Regarding claim 5, Lee et al. disclose the package body layer comprises a molding layer (213).
However, neither Lee et al., Lai et al. nor Matsuura et al. disclose a metal post layer electrically connecting the base structure to the redistribution structure is in the package body layer.
On the other hand, Lin discloses conductive pillars (120) connecting the first side redistribution structure (124) and second side redistribution structure (170) (paragraph 101, Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. in view of Lai et al., and Matsuura et al. according to the teachings of Lin such that the metal posts are formed through the molding layer to electrically connect the first and second redistribution structures. Doing so would improve electrical performance and enable 3D stacking.
Claim 7(s) is/are rejected under 35 U.S.C 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1) and Matsuura et al. (US 20220223456 A1) as applied to claim 1 above, in further view of Seo (US 20230154860 A1).
Regarding claim 7, none of the above references disclose each of the alignment marks contacts the plurality of auxiliary patterns.
However, Seo discloses an insulating pattern (130) is disposed to contact a side surface of the alignment mark pattern (124) (paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. in view of Lai et al and Matsuura et al. according to the teachings of Seo such that the alignment marks contact the auxiliary patterns. Doing so would create redundancy and robustness, allowing for both coarse and fine alignment.
Claim(s) 10-12, 15-17 is/are rejected under 35 U.S.C 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1), Lin (US 20160118333 A1), and Matsuura et al. (US 20220223456 A1).
Regarding claim 10, Lee et al. disclose a semiconductor package comprising an upper redistribution structure (203) on the package molding layer (213); and alignment marks (150) on the upper redistribution structure (203a) in a plan view (Fig. 1).
However, Lee et al. does not disclose a lower redistribution structure having a fan-in area and fan-out areas surrounding the fan-in area; a semiconductor chip in the fan-in area; a package molding layer in the fan-in area and the fan-out areas.
On the other hand, Lai et al. disclose a semiconductor package having a fan-in area (1061) and fan-out areas (1060) surrounding the fan-in area (paragraph 44, Fig1A-1); a semiconductor die (120) are disposed in the fan-in area (1061) (paragraph 48), and a molding compound (140) encapsulating the semiconductor die (120) (paragraph 61, Fig 1G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. such that the semiconductor package has fan-in and fan-out areas, and the package is covered by a molding layer. Doing so would enable direct chip connection, enable higher I/O density, and protect the chip from environmental factors.
Neither Lee et al., Lai et al., nor Matsuura et al. discloses a metal post layer electrically connecting the base structure to the redistribution structure is in the package body layer.
On the other hand, Lin discloses conductive pillars (120) connecting the first side redistribution structure (124) and second side redistribution structure (170) (paragraph 101, Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lin such that the metal posts are formed through the molding layer to electrically connect the first and second redistribution structures. Doing so would improve electrical performance and enable 3D stacking.
None of the references above disclose each of the alignment marks comprises a plurality of metal layers.
On the other hand, Matsuura et al. disclose alignment mark (P) is comprised of metal layer (18) (paragraph 30, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. and Matsuura et al. such that the alignment marks have a plurality of metal layers. Doing so would allow the metal layers to function as an etching stopper and an antireflection to the metal foil (Matsuura, paragraph 45).
None of the references above disclose a plurality of auxiliary patterns are in the upper redistribution structure under the alignment marks to assist in recognition of the alignment marks.
However, Lee et al. disclose alignment marks (150-1, 150-2, 150-3, and 150-4) (Fig 6-9) are applicable to the arrangement of alignment marks (150a) of Fig. 4 and 5 (paragraph 113). This means alignment marks (150a) may be formed on the upper redistribution structure (203) (paragraph 88). Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above such that the auxiliary patterns are in upper redistribution under the alignment marks. Doing so would enable robust, multi-level alignment references to ensure better contrast and redundancy.
Regarding claim 11, Lee et al. disclose the upper redistribution structure comprises a transparent redistribution insulating layer (203b) (paragraph 28), and wherein the plurality of auxiliary patterns (MP) comprise a plurality of redistribution layers (130b) insulated from the transparent redistribution layer (203b) (paragraph 28-29, Fig 2).
Regarding claim 12, Lee et al. disclose the plurality of auxiliary patterns (MP) comprise a plurality of sub auxiliary patterns (130) apart from one another in an X direction and a Y direction perpendicular to the X direction in the plan view (paragraph 29, Fig. 2)
Regarding claim 13, none of the above references disclose the plurality of auxiliary patterns comprise a plurality of redistribution layers at an uppermost part of the upper redistribution structure.
However, Lee et al. disclose a lower redistribution layer (201a) may be a multilayer structure in which a plurality of redistribution patterns is stacked (paragraph 56). Lee et al. also disclose a quadrangular insulating patterns (130a) and a metal layer (130b) between the plurality of insulating patterns (130a). Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. in view of the prior references such that the auxiliary patterns comprise a plurality of redistribution layers of the redistribution structure. Doing so would enhance contrast, enhance thermal management, and improve manufacturability.
Regarding claim 15, Lee et al. disclose each of the alignment marks (150 is on the upper redistribution structure (203) separated from the upper redistribution structure by a redistribution insulating layer (203b) (paragraph 61).
Regarding claim 16, Lee et al. disclose each of the alignment marks (150a) is on the upper redistribution structure (203) in the plan view (paragraph 106, Fig 2).
Regarding claim 17, Lee et al. disclose exposure holes exposing top surfaces of the plurality of auxiliary patterns are further formed around each of the alignment marks (150a) (paragraph 150, Fig. 6).
Claim(s) 14 is/are rejected under 35 U.S.C 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1), Lin (US 20160118333 A1), and Matsuura et al. (US 20220223456 A1) as applied to claim 10 above, in further view of Seo (US 20230154860 A1).
Regarding claim 14, Lee et al. disclose alignment marks (150a) is in the upper redistribution structure (203) (paragraph 88, Fig. 4).
However, Seo discloses an insulating pattern (130) is disposed to contact a side surface of the alignment mark pattern (124) (paragraph 28).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Seo such that the alignment marks contact the auxiliary patterns. Doing so would create redundancy and robustness, allowing for both coarse and fine alignment.
Claim(s) 18 is/are rejected under 35 U.S.C 103 as being unpatentable over Lee et al. (US 20210074691 A1) in view of Lai et al. (US 20230066598 A1), Lin (US 20160118333 A1), and Matsuura et al. (US 20220223456 A1).
Regarding claim 18, Lee et al. disclose a semiconductor package comprising a lower semiconductor package (200B); an upper semiconductor package (200T) stacked on the lower semiconductor package (Fig. 3), the upper semiconductor package having a size (W2) less than a size of the lower semiconductor package (W1) (paragraph 25); and a plurality of package connection terminals (292) electrically connecting the lower semiconductor package to the upper semiconductor package (paragraph 67), an upper redistribution structure (203) on the package molding layer (213); and alignment marks (150) on the upper redistribution structure (203a) in a plan view (Fig. 1).
However, Lee et al. does not disclose a lower redistribution structure having a fan-in area and fan-out areas surrounding the fan-in area; a semiconductor chip in the fan-in area; a package molding layer in the fan-in area and the fan-out areas.
On the other hand, Lai et al. disclose a semiconductor package having a fan-in area (1061) and fan-out areas (1060) surrounding the fan-in area (paragraph 44, Fig1A-1); a semiconductor die (120) are disposed in the fan-in area (1061) (paragraph 48), and a molding compound (140) encapsulating the semiconductor die (120) (paragraph 61, Fig 1G).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. such that the semiconductor package has fan-in and fan-out areas, and the package is covered by a molding layer. Doing so would enable direct chip connection, enable higher I/O density, and protect the chip from environmental factors.
Lee et al does not disclose a metal post layer electrically connecting the base structure to the redistribution structure is in the package body layer.
On the other hand, Lin discloses conductive pillars (120) connecting the first side redistribution structure (124) and second side redistribution structure (170) (paragraph 101, Fig. 11).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lin such that the metal posts are formed through the molding layer to electrically connect the first and second redistribution structures. Doing so would improve electrical performance and enable 3D stacking.
None of the references above disclose each of the alignment marks comprises a plurality of metal layers.
On the other hand, Matsuura et al. disclose alignment mark (P) is comprised of metal layer (18) (paragraph 30, Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lee et al. according to the teachings of Lai et al. and Matsuura et al. such that the alignment marks have a plurality of metal layers. Doing so would allow the metal layers to function as an etching stopper and an antireflection to the metal foil (Matsuura, paragraph 45).
None of the references above disclose a plurality of auxiliary patterns are in the upper redistribution structure under the alignment marks to assist in recognition of the alignment marks.
However, Lee et al. disclose alignment marks (150-1, 150-2, 150-3, and 150-4) (Fig 6-9) are applicable to the arrangement of alignment marks (150a) of Fig. 4 and 5 (paragraph 113). This means alignment marks (150a) may be formed on the upper redistribution structure (203) (paragraph 88). Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above such that the auxiliary patterns are in upper redistribution under the alignment marks. Doing so would enable robust, multi-level alignment references to ensure better contrast and redundancy.
Regarding claim 19, Lee et al. disclose a plurality of external connection pads (294b) connected to the plurality of package connection terminals (292) are on the upper redistribution structure (203), and wherein each of the alignment marks (150) is at a same vertical level as a level of the plurality of external connection pads (paragraph 31, 62).
Regarding claim 20, Lee et al. disclose a plurality of external connection pads (294b) connected to the plurality of package connection terminals (292) are on the upper redistribution structure (203), and wherein each of the alignment marks (150) contacts a respective portion of the plurality of auxiliary patterns (130) (Fig. 1).
None of the above references disclose the alignment marks is at a level lower than a level of the plurality of external connection pads.
However, Lee et al. disclose the alignment marks (150a) may be coplanar with the upper surface of the redistribution structure (203) (paragraph 88). Rearrangement of parts is within the routine skill level of one in the art. This is a design choice. In re Japikse, 181 F.2d 1019, 86 USPQ70 (CCPA 1950).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination as discussed above such that the alignment marks are at a level lower than a level of the plurality of connection pads. Doing so would provide protection during chemical-mechanical polishing and clearer optical visibility.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVE Q PHAN whose telephone number is (571)272-1227. The examiner can normally be reached Monday - Friday 8am - 5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at (571) 272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVE PHAN/Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817