DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 21 September 2026 has been entered.
DETAILED ACTION
The instant action is in response to application 14 September 2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s remarks on the merits have been considered, and but are not persuasive. Applicant argues that "mirror the current sensing using at least two resistors" is not taught by the combination. Examiner respectfully disagrees. The current mirror shown in Fig. 4B explicitly shows two resistors (81, 82) and Fig. 4A shows two transistors with a constant voltage being fed to them, making them act as a resistor variant upon their channel length, which Qin mentions as channel resistance multiple times throughout his specification. As such, the argument with respect to the merits is not persuasive. Especially given language in the MPEP regarding art recognized equivalence (2144.06; 2183) especially when the transistor and resistor are performing the same function.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Korea on 19 April 2023.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
For method claims, note that under MPEP 2112.02, the principles of inherency, if a prior art device, in its normal and usual operation, would necessarily perform the method claimed, then the method claimed will be considered to be anticipated by the prior art device. When the prior art device is the same as a device described in the specification for carrying out the claimed method, it can be assumed the device will inherently perform the claimed process. In re King, 801 F.2d 1324, 231 USPQ 136 (Fed. Cir. 1986). Therefore the previous rejections based on the apparatus will not be repeated. (The claims have been condensed.)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 8 are rejected under 35 U.S.C. 103 as being unpatentable over Qin (US 20140253089) in view of Walter (US 2010/0237840) and Jung (US 20070115741).
As to claim 1, Qin discloses a signal, and wherein the bi-directional DC-DC converter further comprises an output circuit configured to mirror (Fig. 4B, item 68) the sensing current using at least two resistors (81, 82) to provide the sensing current as a sensing output (Vcs).
Though Qin teaches much of the claimed invention, he does not explicitly teach a bi-directional direct current to direct current (DC-DC) converter, sense a bi-directional current flowing through the second switching transistor in a boost mode or the bi-directional current sensor is further configured to generate a virtual voltage of a positive voltage in a negative feedback method regardless of the sign of the switching node voltage or and wherein the sensing transistor is matched to a drain-source voltage of the second switching transistor..
As to the limitation, the bi-directional current sensor is further configured to generate a virtual voltage of a positive voltage in a negative feedback method regardless of the sign of the switching node voltage, this is not explicitly taught. However, this is obvious. First, note that Figs 3A/3B always have a positive Vcs signal, which while heavily implies always positive voltage, does not explicitly state as such. Note that in Fig. 2. The output of Vcs = R12*(Ios-Iout). This means that as long as Ios is greater than Iout, Vcs will always have a positive voltage. If one of ordinary skill sets the magnitude of Ios to be greater than that of Iout, the signal RCS will always be positive. The expected advantage of this would be increase the noise immunity of the wires.
As to the limitation, a bidirectional converter, this is implied but not explicitly taught. However, Walter teaches a bidirectional converter (Fig. 2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use bidirecitonality as disclosed in Walter to sink or source current from the load.
As to the limitation and wherein the sensing transistor is matched to a drain-source voltage of the second switching transistor, this is heavily implied sense in order to have a sensing value, the transistors must have similar saturation and conduction values, but it is not explicitly taught.
Jung teaches and wherein the sensing transistor is matched to a drain-source voltage of the second switching transistor (¶50 “Accordingly, the amount of the gate-source voltage of the NMOS transistor MN23 becomes equal to the amount of the gate-source voltage of the NMOS transistor MN24. Therefore, the amount of the drain-source voltage of the NMOS transistor MN22, which is a current sensing transistor, becomes equal to the amount of the drain-source voltage of the NMOS transistor MN21, which is a power MOSFET.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device above to use transistors with the similar characteristics in order to ensure that the sensing remains linear.
As to the limitation, sense a bi-directional current flowing through the second switching transistor in a boost mode this is taught by the combination. This would occur when the boost mode of Walter is function, and the current sensor outputs a value.
As to claim 8, Qin in view of Walter and Jung teaches further comprising an output circuit configured to mirror the sensing current and to provide it as a sensing output (Qin, Figs. 4A, 4B, and 5 show current mirrors feeding VCS).
Allowable Subject Matter
Claims 9-20 allowed.
Claims 2-7 would be allowable if rewritten to overcome to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
As to claim 2, the prior art fails to disclose: wherein the bi-directional current sensor comprises: a voltage clamp circuit configured to generate a clamp voltage by clamping the switching node voltage; a first amplifier configured to generate a first amplified voltage by amplifying a differential voltage between the clamp voltage and the ground voltage; a polarity selector circuit configured to convert a polarity of the first amplified voltage into a positive voltage, based on the boost mode or the buck mode; a second amplifier configured to amplify the differential voltage between the virtual voltage and the ground voltage and to generate a second amplified voltage;a subtractor circuit configured to generate an amplified voltage by subtracting the second amplified voltage from the first amplified voltage; a source follower transistor configured to transmit the amplified voltage to the virtual voltage; and a sensing transistor configured to generate a sensing current corresponding to the virtual voltage.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 9, the prior art fails to disclose: “a polarity selector circuit configured to convert a polarity of the first amplified voltage into a positive voltage, based on a mode; a second amplifier configured to amplify a differential voltage between a virtual voltage and the ground voltage and to generate a second amplified voltage; a subtractor circuit configured to generate an amplified voltage by subtracting the second amplified voltage from the first amplified voltage.” in combination with the additionally claimed features, as are claimed by the Applicant.
As to claim 19, the prior art fails to disclose " generating a second amplified voltage by amplifying a differential voltage between a virtual voltage and the ground voltage using a second amplifier; generating an amplified voltage by subtracting the second amplified voltage from the first amplified voltage; transferring the amplified voltage as the virtual voltage to a sensing transistor through a source follower; and detecting a sensing current flowing through the sensing transistor by the virtual voltage” in combination with the additionally claimed features, as are claimed by the Applicant.
Please note: while objected or allowed claims have been indicated, only the presented claims have been examined for compliance with form and 35 USC 112 consideration. As a reminder, claims that are dependent upon objected claims still require examination for form and 35 USC 112 issues even if they overcome 35 USC 102 and 103 rejections. Similarly, amendments incorporating allowable subject matter into independent claims requires reconsideration for dependent claim form and any possible 35 USC 112 issues that arise through amendments even if the 35 USC 102 and 103 rejections are overcome. As such, applicant is advised that while examiner can enter previously allowed claims or previously objected claims rewritten into independent form after final rejection, any other claims may not be entered.
Conclusion
Examiner has cited particular column, paragraph, and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PETER M NOVAK whose telephone number is (571)270-1375. The examiner can normally be reached on 9AM-5PM,Monday through Thursday, EST.
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/PETER M NOVAK/ Primary Examiner, Art Unit 2839