Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
2. Applicant's arguments filed 04/23/2026 have been fully considered but they are not persuasive.
On pages 7-10 of the amendment, Applicant argued that Zakharchenko, Van der Auwera and their combination do not teach wherein a basemesh is level 0, vertices are level 1 after dividing each edge in half, and additional levels are implemented.
However, the Examiner respectfully disagrees. Van der Auwera clearly teaches wherein a basemesh is level 0, vertices are level 1 after dividing each edge in half, and additional levels are implemented (Paragraph 0041, The reconstructed base meshes, see for instance the base mesh at s0 in FIG. 8, may be subdivided into finer meshes with additional vertices and, hence, additional triangles, see finer meshes at s1 and s2 in FIG. 8; paragraph 0090, V-DMC encoder 200 and V-DMC decoder 300 may be configured to implement a subdivision scheme. Various subdivision schemes may be used. A possible solution is the mid-point subdivision scheme, which at each subdivision iteration subdivides each triangle into 4 sub-triangles as described in FIG. 8. New vertices are introduced in the middle of each edge. Thus, Fig. 8, which shows a mid-point subdivision scheme used by V-DMC encoder and V-DMC decoder, teaches base mesh at s0, considered level 0; at first iteration s1, considered level 1, new vertices are introduced in the middle of each edge; and each sub-triangle can be further divided in a subsequent iteration s2, considered additional levels).
See the rejection below regarding the argument related to the amended limitation of claim 1.
Claim Rejections - 35 USC § 112
3. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
4. Claims 1, 9 and 17 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The claims teach the limitation “wherein the one or more blocks for the LoD are determined based on a difference between a first cumulative position count associated with the LoD and a second cumulative position count associated with a preceding LoD, so that displacement information corresponding to different LoDs does not occupy the same block.” It is unclear where said limitation is taught in the specification as-originally filed. Applicant stated on page 6 of the amendment that the support can be found at least at page 7, line 7 through page 9, line 19; however, nothing in those pages teaches the difference between a first cumulative position count associated with the LoD and a second cumulative position count associated with a preceding LoD.
Claim Interpretation
5. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
6. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: “an encoder configured for…” in claim 17 and “a decoder configured for…” in claims 17-19 and 22-24.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Specification (on page 17) describes the encoder and decoder as software embodied in a structure of a processor. Thus, the claimed encoder and decoder are interpreted to be embodied on a processor.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
9. Claim(s) 1-4, 6-12, 14-20, and 22-24 is/are rejected under 35 U.S.C. 103 as being unpatentable over ZAKHARCHENKO et al. (WO 2024/039703 A1) hereinafter “ZAKHARCHENKO” in view of Van der Auwera et al. (US 2024/0348825) hereinafter “Van der Auwera”.
As per claim 1, ZAKHARCHENKO discloses a method programmed in a non-transitory memory of a device comprising:
…when the first flag indicates LoD block packing, then packing displacement information of a single LoD into one or more blocks (see FIG. 16B; paragraphs 0077, 0078, 0080, and 0083, LoD-based packing for displacement wavelet coefficients in 2D displacement samples…packing the samples belonging to each of the plurality of levels of detail into one of the plurality of blocks) and packing filler bits until an end of a current block of the one or more blocks (see LoD_0_Pad, LoD_1_Pad, and LoD_2_Pad in FIG. 16B; paragraph 0083)…wherein the one or more blocks for the LoD are determined based on a difference between a first cumulative position count associated with the LoD and a second cumulative position count associated with a preceding LoD (paragraph 0070, the syntax element dmsps_mesh_LoD_vcrtcx_count[i] refers to a vertex count to indicate a difference between the number of vertexes in a level of details such as LoD(i) and the number of vertexes in another level of details such as LoD(i-l)… the syntax element “dmsps_mesh_LoD_vertex_count[i]” can be used to indicate a number of samples directly in LoD with index “i”), so that displacement information corresponding to different LoDs does not occupy the same block (intended use statement); and
when the second flag indicates LoD packing together, then packing displacement information of LoDs into the one or more blocks (the limitations are conditional claim limitations related to two possibilities, either the first flag indicates Level-of-Detail (LoD) block packing or the second flag indicates LoD packing together. Thus, only one of the two possibilities needs to be examined, see MPEP §2111.04).
However, ZAKHARCHENKO does not explicitly disclose determining when a first flag indicates Level-of-Detail (LoD) block packing or a second flag indicates LoD packing together…wherein a basemesh is level 0, vertices are level 1 after dividing each edge in half, and additional levels are implemented.
In the same field of endeavor, Van der Auwera discloses determining when a first flag indicates Level-of-Detail (LoD) block packing or a second flag indicates LoD packing together (paragraph 0110, The encoder may explicitly signal in the bitstream the used packing scheme; see also paragraphs 0106 and 0201)…wherein a basemesh is level 0, vertices are level 1 after dividing each edge in half, and additional levels are implemented (Paragraphs 0041 and 0090, The reconstructed base meshes may be subdivided into finer meshes with additional vertices and, hence, additional triangles…V-DMC encoder 200 and V-DMC decoder 300 may be configured to implement a subdivision scheme. Various subdivision schemes may be used. A possible solution is the mid-point subdivision scheme, which at each subdivision iteration subdivides each triangle into 4 sub-triangles as described in FIG. 8. New vertices are introduced in the middle of each edge. Fig. 8 shows a first iteration s1, considered level 1, that introduces new vertices in the middle of each edge and each sub-triangle can be further divided in a subsequent iteration s2).
Note that the first limitation discloses “determining when a first flag indicates Level-of-Detail (LoD) block packing or a second flag indicates LoD packing together” emphasis added, which requires the determination of either the first flag or the second flag. Also, the claim teaches the limitations “when the first flag indicates LoD block packing, then…” and “when the second flag indicates LoD packing together, then…” It is clear that claim 1 recites two conditional limitations that are mutually exclusive, such that if one is performed, then the other does not need to be performed. Although both conditional limitations are examined, only one of them is required. See In Rebstock, the PTAB echoed the Schulhauser guidance, see Ex Parte Schulhauser, No. 2013-007847, 2016 WL 6277792 (P.T.A.B. Apr. 28, 2016), that when there are two mutually exclusive steps, “the broadest reasonable interpretation of [the claim] requires performance of only one of the two mutually exclusive steps.
One of ordinary skill in the art, before the effective filing date of the claimed invention, would have been motivated to combine the elements taught by ZAKHARCHENKO, with those of Van der Auwera, because both references are drawn to the same field of endeavor, because indeed both references are related to mesh encoding/decoding process using level of detail (LoD)-based packing for displacement wavelet coefficients in 2D displacement, and because such a combination represents a mere combination of prior art elements, according to known methods, to yield a predictable result, such as signaling the used packing scheme to a decoder and getting a better approximation of the original curve. This rationale applies to all combinations of ZAKHARCHENKO and Van der Auwera used in this Office Action unless otherwise noted.
As per claim 2, ZAKHARCHENKO discloses repeating the packing displacement information of the single LoD into the one or more blocks (see FIG. 16B; paragraphs 0077-0078, 0080-0081, and 0083, several LoDs, such as LoD_0, LoD_l’, and LoD_2’, are discontinuously packed in the block-boundary-aligned arrangement) and packing the filler bits until the end of the current block of the one or more blocks for subsequent LoDs until all of the displacement information is packed (see LoD_0_Pad, LoD_1_Pad, and LoD_2_Pad in FIG. 16B; paragraph 0083).
As per claim 3, ZAKHARCHENKO discloses receiving position count information which indicates where each LoD begins and ends (see FIG. 16B; paragraphs 0060, 0062, 0084, and 0087).
As per claim 4, ZAKHARCHENKO discloses wherein each subsequent LoD begins at a beginning of a block (see FIG. 16B).
As per claim 6, ZAKHARCHENKO discloses dividing mesh information into different LoDs (see LoD_0_Pad, LoD_1_Pad, and LoD_2_Pad in FIG. 16B; paragraph 0073).
As per claim 7, ZAKHARCHENKO discloses performing slice decoding (paragraph 0084).
As per claim 8, ZAKHARCHENKO discloses decoding the displacement information (paragraph 0087).
As per claims 9-12 and 14-16, arguments analogous to those applied for claims 1-4 and 6-8 are applicable for claims 9-12 and 14-16; in addition, ZAKHARCHENKO discloses using a memory and processor for storing and processing an application related to the claimed method (paragraphs 0122-0124).
As per claim 17, arguments analogous to those applied for claim 1 are applicable for claim 17; in addition, ZAKHARCHENKO discloses an encoder configured for encoding a 3D mesh (see FIG. 1 and paragraph 0033) and a decoder for performing the claimed method (paragraphs 0084-0088); and Van der Auwera discloses implementing inverse packing utilizing width, height, bit depth, block size, and position count as input (paragraphs 0123-0129, V-DMC decoder 300 may be configured to perform inverse image packing of wavelet coefficients. Inputs to this process are: width, which is a variable indicating the width of the displacements video frame; height, which is a variable indicating the height of the displacements video frame; bitDepth, which is a variable indicating the bit depth of the displacements video frame;…blockSize, which is a variable indicating the size of the displacements coefficients blocks; positionCount, which is a variable indicating the number of positions in the subdivided submesh).
As per claims 18-20 and 22-24, arguments analogous to those applied for claims 2-4 and 6-8 are applicable for claims 18-20 and 22-24.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED JEBARI whose telephone number is (571)270-7945. The examiner can normally be reached Mon-Fri: 10:00am-10:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chris Kelley can be reached on 571-272-7331. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED JEBARI/Primary Examiner, Art Unit 2482
Prosecution Insights