DETAILED ACTION
Claims 1-20 are pending in this application.
Claims 1-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 7-12, 15-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hagersten et al. (U.S. PGPub No. 2003/0097539) in view of Lyon et al. (U.S. PGPub No. 2005/0273571) in view of Davis et al. (U.S. PGPub No. 2023/0131039).
Claim 1
Hagersten (2003/0097539) teaches:
A computing node in a multi-node computing system, the computing node comprising: a local memory; FIG. 1 and P. 0045 Computer system 10 includes multiple SMP nodes 12A-12D, SMP node 12A is configured with a memory 22
at least one processor configured to run an operating system, the operating system being configured to run an application in a virtual address space, and […] the application comprising a process that generates a first memory access request comprising a first virtual address; and P. 0073 Processors 16 execute instructions in virtual addresses; P. 0062 and FIG. 1B applications execute on architecture 40
an access library comprising a data structure on the computing node, the access library configured to be responsive to the first memory access request by: converting the first virtual address into a first physical address; P. 0073 MMUs 76 perform a virtual to physical address translation for instructions executed on processors 16, through an address translation mechanism [data structure]
accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory; and P. 0099-100 a local physical address includes an address bit, called a CMR bit, which indicates whether the local physical address corresponds to the requesting node or to the CMR address space (i.e, a shadow copy of data from a remote node). If the CMR bit is clear, the requesting node is the home node and the local physical address corresponds to local data (i.e. in memory 22, see 0098)
accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node, […] P. 0099 If the CMR bit is set, the system interface 24 translates the local physical address to a global address corresponding to a copy of data from a remote node; P. 0092 LPA2GA translation unit 82 (or LPA2GA translation table 104, see 0113-114) translates the local physical address into a corresponding global address
Hagersten does not explicitly teach an application running on multiple nodes generating a memory access.
Lyon (2005/0273571) teaches:
the application being part of a distributed job running on multiple nodes of the multi-node computing system, and the application comprising a process that generates a first memory access request comprising a first virtual address; and […] P. 0023 and FIG. 2 application programs 215 hosted by the operating system are assigned to the virtual processors of the DVM 200; P. 0026 a processing unit in one of the DVM nodes 201 encounters a memory access instruction including a virtual address (VA)
[…] accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node, wherein the GAT table stores entries identifying the multiple nodes including the second computing node […] P. 0026 virtual machine page table 242_A translates a virtual address (VA) into an apparent physical address (APA) in the unified address range; P. 0030 The page directory field 281 in the APA 267 is used to identify a node of the DVM that hosts a page directory for the APA 267 (also P. 0033); P. 0035 a node which contains the page directory for an APA also contains a shared copy of the page; P. 0027 when two or more nodes hold copies of the same page, an APA may be mapped to physical addresses in two different nodes as shown at 260
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten with the application running on multiple nodes generating a memory access taught by Lyon
The motivation being for distributed concurrent execution of applications (see Lyon P. 0023)
The systems of Hagersten and Lyon do not explicitly teach entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node.
Davis (2023/0131039) teaches:
the entry of the GAT table including a node identifier of the second computing node and a block identifier of a block of memory within the second computing node. P. 0056 Remote Address translation module 305 converts local addresses steered to the remote bus personality module (RBPM) to [Remote Node, Remote Node Address] using a set of mapping tables from [local address, size] to [Node ID, Remote address]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node taught by Davis.
The motivation being the ability to remote memory, I/O, and interrupt transactions across the fabric (see Davis P. 0044)
The systems of Hagersten, Lyon and Davis are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Davis to obtain the invention as recited in claims 1-8.
Claim 2
Hagersten (2003/0097539) teaches:
The computing node of claim 1, wherein the first physical address comprises a multi-bit address, and the first indication whether the first memory access request is for the local memory and the second indication whether the first memory access request is for memory located on the second computing node comprises a state of one or more bits of the first physical address. P. 0099-100 a local physical address includes a CMR bit, which when set indicates the local physical address corresponds to a copy of data from a remote node, and when clear indicates the local physical address corresponds to local data in the home node
Claim 3
Hagersten (2003/0097539) teaches:
The computing node of claim 1, wherein the local memory includes a first memory space allocated to be globally shared memory the first memory space being accessible by at least the second computing node of the multi-node computing system that is remotely located from the computing node, and P. 0058 and FIG. 1A processor 32A may access memory 36B via network 38; P. 0091 transaction filter 98 detects an I/O transaction on address bus 58 which identifies another SMP node 12 interface; P. 0098 a CMR space in memory 22 stores shadow copies of data from other nodes; P. 0104 and FIG. 4 CMR space 520 is mapped to node 1 and CMR address space 524 is mapped to node 2
Lyon (2005/0273571) teaches:
the processor is further configured to run a distributed agent process configured to communicate availability of at least part of the first memory space to at least the second computing node. P. 0033 page management responsibility is distributed among the various nodes of the DVM 200; P. 0034 shared memory subsystem 2091 issues a page copy request to the directory node (node 2012), which looks up the requested page (APA) in its page directory 247 to determine which node holds copies of a page, and whether the access is exclusive or shared [availability]
The rationale to combine Hagersten with Lyon for claim 1 equally applies for dependent claim 3.
Claim 4
Lyon (2005/0273571) teaches:
The computing node of claim 3, wherein the access library is responsive to a request received by the computing node to run the application by allocating the first memory space to be globally shared memory that accessible by at least one other computing node of the multi-node computing system. P. 0038 the shared memory subsystem 2011 of node 2011 receives the page copy from node 201N, node 2012 updates the page directory to identify requestor node 2011 as an additional page holder
Claim 7
Hagersten (2003/0097539) teaches:
The computing node of claim 1, wherein the access library is further configured to receive a node identification for the second computing node in response to accessing the global access tuple table. P. 0096 physical address includes a node ID field which indicates the home node to which the physical address is assigned; P. 0113-114 LPA2GA translation table 104 [global access tuple table] translates a local physical address to global address
Claim 8
Lyon (2005/0273571) teaches:
The computing node of claim 1, wherein the computing node is configured to receive a second memory access request from another computing node of the multi-node computing system, the second memory access request comprising a global virtual address, and the access library is further configured to be responsive to the second memory access request by: P. 0026 a virtual address (VA), received in or computed from the memory access instruction; P. 0027 there is a separate virtual address range 255A, 255B, . . . , 255Z allocated to each process executed in the DVM
converting the second memory access request into a second physical address; and accessing the local memory based on the second physical address. P. 0027 and FIG. 4 the operating system maps the memory pages in each virtual address to an APA address, which is subsequently mapped to a physical address in at least one of the DVM nodes (i.e. one of physical address ranges 259 1-259 N)
The rationale to combine Hagersten with Lyon for claim 1 equally applies for dependent claim 8.
Claim 9
Hagersten (2003/0097539) teaches:
A multi-node computing system, comprising: multiple computing nodes communicatively interconnected through a communication network, a first computing node comprising: a local memory; FIG. 1 and P. 0045 Computer system 10 includes multiple SMP nodes 12A-12D, SMP node 12A is configured with a memory 22
at least one processor configured to run an operating system, the operating system being configured to run an application in a virtual address space, and […] comprising a process that generates a first memory access request comprising a first virtual address; and P. 0073 Processors 16 execute instructions in virtual addresses; P. 0062 and FIG. 1B applications execute on architecture 40
an access library comprising a data structure on the first computing node, the access library configured to be responsive to the first memory access request by: converting the first virtual address into a first physical address; P. 0073 MMUs 76 perform a virtual to physical address translation for instructions executed on processors 16, through an address translation mechanism [data structure]
accessing the local memory based on the first physical address including a first indication that the first memory access request is for the local memory; and P. 0099-100 a local physical address includes an address bit, called a CMR bit, which indicates whether the local physical address corresponds to the requesting node or to the CMR address space (i.e, a shadow copy of data from a remote node). If the CMR bit is clear, the requesting node is the home node and the local physical address corresponds to local data (i.e. in memory 22, see 0098)
accessing an entry in a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the first computing node […] P. 0099 If the CMR bit is set, the system interface 24 translates the local physical address to a global address corresponding to a copy of data from a remote node; P. 0092 LPA2GA translation unit 82 (or LPA2GA translation table 104, see 0113-114) translates the local physical address into a corresponding global address
Hagersten does not explicitly teach an application running on multiple nodes generating a memory access.
Lyon (2005/0273571) teaches:
the application being part of a distributed job running on the multiple computing nodes of the multi-node computing system, and the application comprising a process that generates a first memory access request comprising a first virtual address; and P. 0023 and FIG. 2 application programs 215 hosted by the operating system are assigned to the virtual processors of the DVM 200; P. 0026 a processing unit in one of the DVM nodes 201 encounters a memory access instruction including a virtual address (VA)
[…] accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node, wherein the GAT table stores entries identifying the multiple nodes […] P. 0026 virtual machine page table 242_A translates a virtual address (VA) into an apparent physical address (APA) in the unified address range; P. 0030 The page directory field 281 in the APA 267 is used to identify a node of the DVM that hosts a page directory for the APA 267 (also P. 0033); P. 0035 a node which contains the page directory for an APA also contains a shared copy of the page; P. 0027 when two or more nodes hold copies of the same page, an APA may be mapped to physical addresses in two different nodes as shown at 260
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten with the application running on multiple nodes generating a memory access taught by Lyon
The motivation being for distributed concurrent execution of applications (see Lyon P. 0023)
The systems of Hagersten and Lyon do not explicitly teach entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node.
Davis (2023/0131039) teaches:
the entry of the GAT table including a node identifier of the second computing node and a block identifier of a block of memory within the second computing node. P. 0056 Remote Address translation module 305 converts local addresses steered to the RBFPM to [Remote Node, Remote Node Address] using a set of mapping tables from [local address, size] to [Node ID, Remote address]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node taught by Davis.
The motivation being the ability to remote memory, I/O, and interrupt transactions across the fabric (see Davis P. 0044)
The systems of Hagersten, Lyon and Davis are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Davis to obtain the invention as recited in claims 9-16.
Claim 10
Hagersten (2003/0097539) teaches:
The multi-node computing system of claim 9, wherein the first physical address comprises a multi-bit address, and the first indication whether the first memory access request is for the local memory and the second indication whether the first memory access request is for memory located on the second computing node comprises a state of one or more bits of the first physical address. P. 0099-100 a local physical address includes a CMR bit, which when set indicates the local physical address corresponds to a copy of data from a remote node, and when clear indicates the local physical address corresponds to local data in the home node
Claim 11
Hagersten (2003/0097539) teaches:
The multi-node computing system of claim 9, wherein the local memory includes a first memory space allocated to be globally shared memory, the first memory space being accessible by at least the second computing node of the multi-node computing system that is remotely located from the first computing node, and P. 0058 and FIG. 1A processor 32A may access memory 36B via network 38; P. 0091 transaction filter 98 detects an I/O transaction on address bus 58 which identifies another SMP node 12 interface; P. 0098 a CMR space in memory 22 stores shadow copies of data from other nodes; P. 0104 and FIG. 4 CMR space 520 is mapped to node 1 and CMR address space 524 is mapped to node 2
Lyon (2005/0273571) teaches:
the processor is further configured to run a distributed agent process configured to communicate availability of at least part of the first memory space to at least the second computing node. P. 0033 page management responsibility is distributed among the various nodes of the DVM 200; P. 0034 shared memory subsystem 2091 issues a page copy request to the directory node (node 2012), which looks up the requested page (APA) in its page directory 247 to determine which node holds copies of a page, and whether the access is exclusive or shared [availability]
The rationale to combine Hagersten with Lyon for claim 9 equally applies for dependent claim 11.
Claim 12
Lyon (2005/0273571) teaches:
The multi-node computing system of claim 11, wherein the access library is responsive to a request received by the first computing node to run the application by allocating the first memory space to be globally shared memory that accessible by at least one other computing node of the multi-node computing system. P. 0038 the shared memory subsystem 2011 of node 2011 receives the page copy from node 201N, node 2012 updates the page directory to identify requestor node 2011 as an additional page holder
Claim 15
Hagersten (2003/0097539) teaches:
The multi-node computing system of claim 9, wherein the access library is further configured to receive a node identification for the second computing node in response to accessing the global access tuple table. P. 0096 physical address includes a node ID field which indicates the home node to which the physical address is assigned; P. 0113-114 LPA2GA translation table 104 [global access tuple table] translates a local physical address to global address
Claim 16
Lyon (2005/0273571) teaches:
The multi-node computing system of claim 9, wherein the first computing node is configured to receive a second memory access request from another computing node of the multi- node computing system, the second memory access request comprising a global virtual address, and wherein the access library is further configured to be responsive to the second memory access request by: P. 0026 a virtual address (VA), received in or computed from the memory access instruction; P. 0027 there is a separate virtual address range 255A, 255B, . . . , 255Z allocated to each process executed in the DVM
converting the second memory access request into a second physical address; and accessing the local memory based on the second physical address. P. 0027 and FIG. 4 the operating system maps the memory pages in each virtual address to an APA address, which is subsequently mapped to a physical address in at least one of the DVM nodes (i.e. one of physical address ranges 259 1-259 N)
The rationale to combine Hagersten with Lyon for claim 9 equally applies for dependent claim 16.
Claim 17
Hagersten (2003/0097539) teaches:
A method to access globally shared memory in a multi-node computing system, the method comprising: FIG. 1 and P. 0045 Computer system 10 includes multiple SMP nodes 12A-12D, SMP node 12A is configured with a memory 22
running an application in a virtual address space by a processor of a first computing node that is part of a multi-node computing system […] generating, by a process of the application, a first memory access request comprising a first virtual address; P. 0073 Processors 16 execute instructions in virtual addresses; P. 0062 and FIG. 1B applications execute on architecture 40
converting the first virtual address into a first physical address by an access library, the access library comprising a data structure on the first computing node; P. 0073 MMUs 76 perform a virtual to physical address translation for instructions executed on processors 16, through an address translation mechanism [data structure]
accessing a local memory on the first computing node based on the first physical address including a first indication that the first memory access request is for the local memory; and P. 0099-100 a local physical address includes an address bit, called a CMR bit, which indicates whether the local physical address corresponds to the requesting node or to the CMR address space (i.e, a shadow copy of data from a remote node). If the CMR bit is clear, the requesting node is the home node and the local physical address corresponds to local data (i.e. in memory 22, see 0098)
accessing an entry in a global access tuple table on the first computing node based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the first computing node […] P. 0099 If the CMR bit is set, the system interface 24 translates the local physical address to a global address corresponding to a copy of data from a remote node; P. 0092 LPA2GA translation unit 82 (or LPA2GA translation table 104, see 0113-114) translates the local physical address into a corresponding global address
Hagersten does not explicitly teach an application running on multiple nodes generating a memory access.
Lyon (2005/0273571) teaches:
running an application in a virtual address space by a processor of a first computing node that is part of a multi-node computing system, the application being part of a distributed job running on multiple nodes of the multi-node computing system; generating, by a process of the application, a first memory access request comprising a first virtual address; P. 0023 and FIG. 2 application programs 215 hosted by the operating system are assigned to the virtual processors of the DVM 200; P. 0026 a processing unit in one of the DVM nodes 201 encounters a memory access instruction including a virtual address (VA)
[…] accessing a global access tuple table based on the first physical address including a second indication that the first memory access request is for memory located on a second computing node of the multi-node computing system that is remotely located from the computing node, wherein the GAT table stores entries identifying the multiple nodes, P. 0026 virtual machine page table 242_A translates a virtual address (VA) into an apparent physical address (APA) in the unified address range; P. 0030 The page directory field 281 in the APA 267 is used to identify a node of the DVM that hosts a page directory for the APA 267 (also P. 0033); P. 0035 a node which contains the page directory for an APA also contains a shared copy of the page; P. 0027 when two or more nodes hold copies of the same page, an APA may be mapped to physical addresses in two different nodes as shown at 260
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten with the application running on multiple nodes generating a memory access taught by Lyon
The motivation being for distributed concurrent execution of applications (see Lyon P. 0023)
The systems of Hagersten and Lyon do not explicitly teach entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node.
Davis (2023/0131039) teaches:
the entry of the GAT table including a node identifier of the second computing node and a block identifier of a block of memory within the second computing node. P. 0056 Remote Address translation module 305 converts local addresses steered to the RBFPM to [Remote Node, Remote Node Address] using a set of mapping tables from [local address, size] to [Node ID, Remote address]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with entries of the GAT table including a node identifier for a remote node and an identifier of a block in the memory of the remote node taught by Davis.
The motivation being the ability to remote memory, I/O, and interrupt transactions across the fabric (see Davis P. 0044)
The systems of Hagersten, Lyon and Davis are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Davis to obtain the invention as recited in claims 17-20.
Claim 18
Hagersten (2003/0097539) teaches:
The method of claim 17, wherein the first physical address comprises a multi-bit address, and the first indication whether the first memory access request is for the local memory and the second indication whether the first memory access request is for memory located on the second computing node comprises a state of one or more bits of the first physical address. P. 0099-100 a local physical address includes a CMR bit, which when set indicates the local physical address corresponds to a copy of data from a remote node, and when clear indicates the local physical address corresponds to local data in the home node
Claim 20
Lyon (2005/0273571) teaches:
The method of claim 17, further comprising: receiving a second memory access request from another computing node of the multi-node computing system, the second memory access request comprising a global virtual address; P. 0026 a virtual address (VA), received in or computed from the memory access instruction; P. 0027 there is a separate virtual address range 255A, 255B, . . . , 255Z allocated to each process executed in the DVM
converting the second memory access request into a second physical address by the access library; and accessing the local memory by the access library based on the second physical address. P. 0027 and FIG. 4 the operating system maps the memory pages in each virtual address to an APA address, which is subsequently mapped to a physical address in at least one of the DVM nodes (i.e. one of physical address ranges 259 1-259 N)
The rationale to combine Hagersten with Lyon for claim 17 equally applies for dependent claim 20.
Claim(s) 5-6, 13-14 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hagersten et al. (U.S. PGPub No. 2003/0097539) in view of Lyon et al. (U.S. PGPub No. 2005/0273571) in view of Davis et al. (U.S. PGPub No. 2023/0131039) in view of Cypher et al. (U.S. PGPub No. 2004/0260905).
Claim 5
Lyon (2005/0273571) teaches:
The computing node of claim 3, wherein the operating system […] insert entries into the GAT table. P. 0041 and FIG. 6 each page directory 330 stores page state information for a range of pages (identified by APA), as a respective list of page state elements 333. The page state elements 333 may be added to and deleted from the list to reflect the addition and deletion of copies of the memory page in the various nodes of the DVM; P. 0033 page management responsibility is distributed among the various nodes of the DVM 200 so that each node 201 is the directory node for a different range or group of APAs; P. 0038 an agents (which may act as a directory manager) is implemented by execution of program code within the shared memory subsystems 209 1-209 N
The systems of Hagersten and Lyon do not explicitly teach the operating system creating a global access table.
Cypher (2004/0260905) teaches:
The computing node of claim 3, wherein the operating system comprises a kernel configured to create the GAT table and P. 0041 logic 202 to perform a virtual address (VA) to global address (GA) translation; P. 0052 translation information being used to translate a virtual address is stored with page tables. Page tables may be created by an operating system executing on processing subsystem(s) 142; P. 0057 translation information 222 for the nodes may be stored in a table indexed by the global address 212 for each coherency unit
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with the operating system creating a global access table taught by Cypher
The motivation being to provide page tables for translation of global addresses to local physical addresses within a node (See Cypher P. 0051)
The systems of Hagersten, Lyon and Cypher are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Cypher to obtain the invention as recited in claim 5-6.
Claim 6
Cypher (2004/0260905) teaches:
The computing node of claim 5, wherein the distributed agent process is configured to provide GAT table entry information to the kernel related to globally shared memory. P. 0043 Other processing subsystems in that node 140A may use the global address to determine whether their caches are currently storing a copy of the coherency unit specified by that global address.
Claim 13
Lyon (2005/0273571) teaches:
The multi-node computing system of claim 11, wherein the operating system […] insert entries into the GAT table. P. 0041 and FIG. 6 each page directory 330 stores page state information for a range of pages (identified by APA), as a respective list of page state elements 333. The page state elements 333 may be added to and deleted from the list to reflect the addition and deletion of copies of the memory page in the various nodes of the DVM; P. 0033 page management responsibility is distributed among the various nodes of the DVM 200 so that each node 201 is the directory node for a different range or group of APAs; P. 0038 an agents (which may act as a directory manager) is implemented by execution of program code within the shared memory subsystems 209 1-209 N
The systems of Hagersten and Lyon do not explicitly teach the operating system creating a global access table.
Cypher (2004/0260905) teaches:
wherein the operating system comprises a kernel configured to create the GAT table and insert entries into the global access tuple table P. 0041 logic 202 to perform a virtual address (VA) to global address (GA) translation; P. 0052 translation information being used to translate a virtual address is stored with page tables. Page tables may be created by an operating system executing on processing subsystem(s) 142; P. 0057 translation information 222 for the nodes may be stored in a table indexed by the global address 212 for each coherency unit
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with the operating system creating a global access table taught by Cypher
The motivation being to provide page tables for translation of global addresses to local physical addresses within a node (See Cypher P. 0051)
The systems of Hagersten, Lyon and Cypher are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Cypher to obtain the invention as recited in claim 13-14.
Claim 14
Cypher (2004/0260905) teaches:
The multi-node computing system of claim 13, wherein the distributed agent process is configured to provide GAT table entry information to the kernel related to globally shared memory. P. 0043 Other processing subsystems in that node 140A may use the global address to determine whether their caches are currently storing a copy of the coherency unit specified by that global address.
Claim 19
Hagersten (2003/0097539) teaches:
The method of claim 17, wherein the local memory includes a first memory space allocated to be globally shared memory that accessible by at least the second computing node of the multi-node computing system that is remotely located from the first computing node, the method further comprising: P. 0058 and FIG. 1A processor 32A may access memory 36B via network 38; P. 0091 transaction filter 98 detects an I/O transaction on address bus 58 which identifies another SMP node 12 interface; P. 0098 a CMR space in memory 22 stores shadow copies of data from other nodes; P. 0104 and FIG. 4 CMR space 520 is mapped to node 1 and CMR address space 524 is mapped to node 2
Lyon (2005/0273571) teaches:
running a distributed agent process by the processor that is configured to communicate availability of at least part of the first memory space to at least the second computing node; P. 0033 page management responsibility is distributed among the various nodes of the DVM 200; P. 0034 shared memory subsystem 2091 issues a page copy request to the directory node (node 2012), which looks up the requested page (APA) in its page directory 247 to determine which node holds copies of a page, and whether the access is exclusive or shared [availability]
allocating, by the access library, the first memory space to be globally shared memory that accessible by at least one other computing node of the multi-node computing system in response to a request received by the first computing node to run the application; P. 0038 the shared memory subsystem 2011 of node 2011 receives the page copy from node 201N, node 2012 updates the page directory to identify requestor node 2011 as an additional page holder
The systems of Hagersten and Lyon do not explicitly teach the operating system creating a global access table.
Cypher (2004/0260905) teaches:
creating the global access tuple table by a kernel of an operating system of the first computing node; and inserting entries into the GAT table by the kernel based on globally shared memory information from the distributed agent process. P. 0041 logic 202 to perform a virtual address (VA) to global address (GA) translation; P. 0052 translation information being used to translate a virtual address is stored with page tables. Page tables may be created by an operating system executing on processing subsystem(s) 142; P. 0057 translation information 222 for the nodes may be stored in a table indexed by the global address 212 for each coherency unit; P. 0043 Other processing subsystems in that node 140A may use the global address to determine whether their caches are currently storing a copy of the coherency unit specified by that global address.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hagersten and Lyon with the operating system creating a global access table taught by Cypher
The motivation being to provide page tables for translation of global addresses to local physical addresses within a node (See Cypher P. 0051)
The systems of Hagersten, Lyon and Cypher are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hagersten and Lyon with Cypher to obtain the invention as recited in claim 19.
Response to Arguments
Applicant's arguments filed 12/27/2025 have been fully considered but they are not persuasive.
The applicant states on page 10 “However, even if the CMR bit were equivalent to the first indication and the second indication of claim 1, which Applicant does not concede, Hagersten never states that a single physical address includes both a first CMR bit for local memory and a second CMR bit for remote memory. Instead, the CMR bit of Hagersten is an either / or indication (e.g., "Alternatively, if the CMR bit is clear," Id.). Either the CMR bit is set and the local physical address is translated to a global address, or the CMR bit is not set and the local physical address is not translated. Thus, Hagersten does not contemplate that a single physical address could include a first indication for local memory as well as a second indication for remote memory, as required by claim 1.”
The examiner respectfully notes the specification of the current application describes global information in P. 0022 as ignored if the address translates to a local memory address and only considered when it indicates the address is in the global memory and in P. 0033 as one or more bits that “indicates whether a physical address corresponds to a local memory address or a remote memory address”. The specification does not describe the physical address including a first and second indicator, where the same physical address is used to both access the local memory using the first indicator and the GAT table using the second indicator as described in the argument. The CMR bit of Hagersten functions similarly to the global information described in the specification, and as the first indicator or second indicator as claimed. The CMR bit’s value determines if a physical address is used as a local address or translated into a global address, and functions the same as the claimed first and second indicator as claimed.
Applicant's arguments filed 12/27/2025 have been fully considered but they are not persuasive.
The applicant states on page 10-11 “However, Davis does not teach or suggest the GAT table of claim 1 because the Remote Address translation module 305 of Davis converting a local address to [Remote Node, Remote Node Address] only suggests separate one- to-one conversions. The conversions of Davis are done on the fly. Such on-the-fly do not suggest a table. The values [Remote Node, Remote Node Address] from Davis are not entries in a table. The entries of the GAT table are not converted from a local address as the values of Davis are. Davis uses a translation module to convert an address to [Remote Node, Remote Node Address]. There is no translation module that generates the GAT table of claim 1.”
The examiner respectfully notes the claims do not require the GAT table to be generated, merely that the GAT table already exists and is accessed based on the physical address including the second indicator. Additionally, the local address described in P. 0052 and 0056 of Davis does not function as a strictly local address, as the address is steered towards a Remote Bus Personality Module (RBPM) to be converted into a remote address. Additionally, P. 0056 of Davis explicitly states “there is a set of mapping tables from [local address, size] to [Node ID, Remote address]” and “these translation tables are configured so that the resulting physical address encodes the [Remote Node ID, and Remote Address]”, indicating there is at least a set of mapping tables and/or translation tables performing this address conversion. The local address described by Davis is analogous to the first physical address as claimed.
Applicant's arguments filed 12/27/2025 have been fully considered but they are not persuasive.
The applicant states on page 11 “Moreover, even if a reference besides Davis teaches a table, what in Davis suggests that the on-the-fly conversions of Davis would have anything to do with such a table? Davis does not provide any suggestion regarding a table. As shown, the on-the-fly conversions of Davis have nothing to do with tables. Thus, the only motivation to combine a table with the on-the-fly conversions of Davis comes from claim 1, which, besides indicating Davis does not teach or suggest a GAT table or entries of a GAT table, suggest the rejection of claim 1 relies on impermissible hindsight.”
The examiner respectfully notes P. 0056 of Davis explicitly states “there is a set of mapping tables from [local address, size] to [Node ID, Remote address]”, showing that mapping tables exist, and the Remote Address translation module 305 is not just converting addresses “on-the-fly” as argued. The set of mapping tables function similarly to the GAT table as claimed.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Albot et al. (U.S. PGPub No. 2017/0109291) each kernel context providing a global virtual address space and a global segment table that maps effective addresses to the global virtual address space
Vick et al. (U.S. PGPub No. 2009/0089537) teaches a node virtualization table to identify the physical node identifier corresponding to the virtual node identifier, and requesting the memory operation (628) to the remote node (620) using the physical node identifier
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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