DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed April 16, 2026, have been fully considered but they are not persuasive.
On pages 9-11 of Remarks, Applicant argues that the prior art of Park et al. (US Publication 2013/0120898) fails to disclose the limitation “S1-2 > S1-3” and “S2-2 > S2-3” of claim 1. In particular, The Applicant argues that Park does not explicitly disclose that the external electrode layer 32b (See Figure 3) has an area fraction of glass greater than that of external electrode layer 31 that is disposed on the first and second surfaces of the component body 10.
The Examiner respectfully disagrees with the above assertion. As seen in Figure 5A of Park, the glass occupancy (See element 3 in Figure 5A) is far greater in the central region of external electrode layer 32 (which coincides with 32B) than that of external electrode layer 31. Therefore, the limitations “S1-2 > S1-3” and “S2-2 > S2-3” are met as required by claim 1 of the Instant Application. Furthermore, Park discloses the cross-sectional area of glass in the entire external electrode layer 32 with respect to the entire area may be 30 to 80% (¶86).
On page 12 of Remarks, Applicant argues that amended claim 17 overcomes the prior art rejection over Park et al. (US Publication 2013/0120898). In particular, the Applicant asserts that the requirement of the 1-3-th electrode layer being spaced apart from 1-1-th electrode layer, and the 2-3-th electrode layer being spaced apart from the 2-1-th electrode layer overcomes the prior art rejection.
The Examiner respectfully disagrees with the above assertion. In reproduced Figure 2 of Park with Examiner’s Comments below (Figure 2EC), external electrode layer 31 can be arbitrarily divided into multiple layers or regions that are spaced apart from one another. As required by claim 1, these layers are still connected to one another via the regions that are interposed therebetween.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 12-14, and 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US Publication 2013/0120898).
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Figure 2 of Park with Examiner’s Comments (Figure 2EC)
In re claim 1, Park discloses a multilayer electronic component comprising:
a body (10 – Figure 1, Figure 2, ¶44) including a dielectric layer (1 – Figure 2, ¶44) and first and second internal electrodes (21, 22 – Figure 2, ¶44) alternately disposed with the dielectric layer interposed therebetween (Figure 2) and including first and second surfaces (surfaces of 10 facing in the ‘T’ direction – Figure 1, Figure 2) opposing each other in a first direction (‘T’ direction – Figure 1), third and fourth surfaces (surfaces of 10 facing in the ‘L’ direction – Figure 1, Figure 2) connected to the first and second surfaces (Figure 1, Figure 2) and opposing each other in a second direction, and fifth and sixth surfaces (surfaces of 10 facing in the ‘W’ direction – Figure 1) connected to the first to fourth surfaces and opposing each other in a third direction (Figure 1, Figure 2);
a first external electrode (left 30 – Figure 2, ¶44) including a 1-1-th electrode layer (portion of left 31 on third surface – Figure 2, ¶44) disposed on the third surface (Figure 2), a 1-2-th electrode layer (32b – Figure 2, Figure 3, ¶58) disposed on the 1-1-th electrode layer (left 31 – Figure 2; Note that element 32b is indirectly disposed on element 31.) and including glass (¶58), and a 1-3-th electrode layer (portion of left 31 on first and second surfaces) disposed on the first and second surfaces (surfaces of 10 facing in the ‘T’ direction – Figure 1, Figure 2) and connected to the 1-2-th electrode layer (32b – Figure 2);
and a second external electrode (right 30 – Figure 2) including a 2-1-th electrode layer (portion of right 31 on fourth surface – Figure 2) disposed on the fourth surface (Figure 2), a 2-2-th electrode layer (32b’ – Figure 2, Figure 3, ¶58) disposed on the 2-1-th electrode layer (right 31 – Figure 2; Note that element 32b is indirectly disposed on element 31.) and including glass (¶58), and a 2-3-th electrode layer (portion of right 31 on first and second surfaces) disposed on the first and second surfaces (surfaces of 10 facing in the ‘T’ direction – Figure 1, Figure 2) and connected to the 2-2-th electrode layer (32b’ – Figure 2),
wherein in cross sections of the first and second external electrodes in the first and second directions (Figure 3), S1-2 ≥ 15%, S1-2 >S1-3, S2-2 ≥ 15% and S2-2 > S2-3 are satisfied, where an area fraction occupied by glass in the 1-2-th electrode layer is S1-2, an area fraction occupied by glass in the 1-3-th electrode layer is S1-3, an area fraction occupied by glass in the 2-2-th electrode layer is S2-2, and an area fraction occupied by glass in the 2-3-th electrode layer is S2-3 (¶66, ¶68).
In re claim 12, Park discloses the multilayer electronic component of claim 1, as explained above. Park further discloses wherein the first external electrode further includes a 1-4-th electrode (32a – Figure 2, Figure 3, ¶58) layer disposed on the 1-2-th electrode layer (32b – Figure 2, Figure 3) and extending onto the 1-3-th electrode layer (portion of left 31 on top and bottom surfaces of 10 – Figure 2), and the second external electrode further includes a 2-4-th electrode layer (32a’ – Figure 2, Figure 3, ¶58) disposed on the 2-2-th electrode layer (32b’ – Figure 2, Figure 3) and extending onto the 2-3-th electrode layer (portion of right 31 on top and bottom surfaces of 10 – Figure 2).
In re claim 13, Park discloses the multilayer electronic component of claim 1, as explained above. Park further discloses wherein the 1-1-th electrode layer (portion of left 31 on left surface of 10 – Figure 2), the 1-2-th electrode layer (31b – Figure 2), the 1-3-th electrode layer (portion of left 31 on top and bottom surfaces of 10 – Figure 2), the 2-1-th electrode layer (portion of right 31 on right surface of 10 – Figure 2), the 2-2-th electrode layer (31b’ – Figure 2, Figure 3), and the 2-3-th electrode layer (portion of right 31 on top and bottom surfaces of 10 – Figure 2) each contain a metal (¶44). .
In re claim 14, Park discloses the multilayer electronic component of claim 13, as explained above. Park further discloses wherein the 1-2-th electrode layer (31b – Figure 2), the 1-3-th electrode layer (portion of left 31 on top and bottom surfaces of 10 – Figure 2), the 2-2-th electrode layer (31b’ – Figure 2, Figure 3), and the 2-3-th electrode layer (portion of right 31 on top and bottom surfaces of 10 – Figure 2) each include at least one of Cu, Ni, Ag, Sn, Cr, or alloys thereof (¶72), the metal (2 – Figure 3) contained in the 1-2-th electrode layer is the same as the metal contained in the 1-3-th electrode layer, and the metal contained in the 2-2-th electrode layer is the same as the metal contained in the 2-3-th electrode layer (¶72-76).
In re claim 17, Park discloses the multilayer electronic component of claim 1, as explained above. Park further discloses the 1-3-th electrode layer (portion of left 31 on top and bottom surfaces of 10 – Figure 2EC) is spaced apart from the 1-1-th electrode layer (S11 – Figure 2EC), and the 2-3-th electrode layer (portion of right 31 on top and bottom surfaces of 10 – Figure 2EC) is spaced apart from the 2-1-th electrode layer (S21 – Figure 2EC). Note that the Examiner is using element S11 in Figure 2EC to be the 1-1th electrode layer and element 21 in Figure 2EC to be the 2-1th electrode layer in this instance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-6 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Publication 2013/0120898).
In re claim 2, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein the S1-3 and S2-3 satisfy S1-3 ≤ 14% and S2-3 ≤ 14%. However, Park discloses that the area of glass in S1-2 and S2-2 is in the range of 30 to 80% and is correlated to plating solution infiltration and defective plating (¶66-67). Park further discloses the ratio of an area of glass in S1-3 and S2-3 may be 0.5 or less of S1-2 and S2-2 (¶45-¶46) and a difference in the content of glass is correlated to the density of the external electrodes and the prevention of defective plating (¶69). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass in the S1-3 and S2-3 electrode layers to achieve a balance between a desired density of external electrodes, and thus, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 3, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein the S1-3 and S2-3 satisfy 0% < S1-3 ≤ 14% and 0% < S2-3 ≤ 14%. However, Park discloses that the area of glass in S1-2 and S2-2 is in the range of 30 to 80% and is correlated to plating solution infiltration and defective plating (¶66-67). Park further discloses the ratio of an area of glass in S1-3 and S2-3 may be 0.5 or less of S1-2 and S2-2 (¶45-¶46) and a difference in the content of glass is correlated to the density of the external electrodes and the prevention of defective plating (¶69). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass in the S1-3 and S2-3 electrode layers to achieve a balance between a desired density of external electrodes, and thus, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 4, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein the S1-3 and S2-3 satisfy S1-3 = 0% and S2-3 = 0%. However, Park discloses that the area of glass in S1-2 and S2-2 is in the range of 30 to 80% and is correlated to plating solution infiltration and defective plating (¶66-67). Park further discloses the ratio of an area of glass in S1-3 and S2-3 may be 0.5 or less of S1-2 and S2-2 (¶45-¶46) and a difference in the content of glass is correlated to the density of the external electrodes and the prevention of defective plating (¶69). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass in the S1-3 and S2-3 electrode layers to achieve a balance between a desired density of external electrodes, and thus, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 5, Park discloses the multilayer electronic component of claim 1, as explained above. Park further discloses wherein the S1-2 is measured in a central area of the 1-2-th electrode layer (32b – Figure 2, Figure 3; Note that the cross-section is taken at the central point.) in the first-direction (Figure 2), and the S2-2 (32b’ Figure 2, Figure 3; Note that the cross-section is taken at the central point.) is measured in a central region of the 2-2-th electrode layer in the first direction (Figure 2, Figure 3). Park does not explicitly disclose the S1-3 is measured in a central area of the 1-3-th electrode layer in the second direction, and the S2-3 is measured in a central region of the 2-3-th electrode layer in the second direction. However, Park further discloses the ratio of an area of glass in the entirety of S1-3 and S2-3, and therefore, in the central regions, may be 0.5 or less of S1-2 and S2-2 (¶45-¶46) and a difference in the content of glass is correlated to the density of the external electrodes and the prevention of defective plating (¶69). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass in the S1-3 and S2-3 electrode layers to achieve a balance between a desired density of external electrodes, and thus, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 6, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein the 1-1-th electrode layer and the 2-1-th electrode layer do not contain glass. However, Park discloses that the area of glass in S1-2 and S2-2 is in the range of 30 to 80% and is correlated to plating solution infiltration and defective plating (¶66-67). Park further discloses the ratio of an area of glass in the 1-1th electrode layer and 2-1th electrode layer may be 0.5 or less, and thus 0, of S1-2 and S2-2 (¶45-¶46) and a difference in the content of glass is correlated to the density of the external electrodes and the prevention of defective plating (¶69). It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass in the 1-1th and 2-1th electrode layers to achieve a balance between a desired density of external electrodes, and thus, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
In re claim 18, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein the S1-2 and S2-2 satisfy 15% ≤ S1-2 ≤ 40% and 15% ≤ S2-2 ≤ 40%. However, Park discloses that the area of glass in S1-2 and S2-2 is in the range of 30 to 80% and is correlated to a balance between density, and, thus, plating solution infiltration, and plating effectiveness (¶66-67).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the area of glass to achieve a balance between a desired density of external electrodes, and thus, plating infiltration characteristics, plating effectiveness, and manufacturing costs, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Publication 2013/0120898) in view of Onodera et al. (US Publication 2020/0211774).
In re claim 9, Park discloses the multilayer electronic component of claim 1, as explained above. Park further discloses a 1-3-th corner connecting the first and third surfaces (corner connecting top and left surfaces of 10 – Figure 2), a 1-4-th corner connecting the first and fourth surfaces (corner connecting top and right surfaces of 10 – Figure 2), and a 2-3-th corner connecting the second and third surfaces (corner connecting bottom and left surfaces of 10 – Figure 2), and a 2-4-th corner connecting the second and fourth surfaces (corner connecting bottom and right surfaces of 10 – Figure 2), wherein the 1-3-th electrode layer (any portion of left 31 that contacts the top left corner and the top surface and the bottom left corner and the bottom surface ) is in contact with the 1-3-th corner and the 2-3-th corner (Figure 2), and the 2-3-th electrode layer (any portion of right 31 that contacts the top right corner and the top surface and the bottom right corner and the bottom surface ) is in contact with the 1-4-th corner and the 2-4-th corner (Figure 2).
Park does not disclose each of the 1-3-th corner, 1-4-th corner, the 2-3-th corner, and the 2-4-th corner having a round shape.
Onodera discloses the ridges and corners of a multilayer chip are rounded (¶46).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to incorporate the chamfered corners and ridges of Onodera to prevent chipping during a manufacturing process.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Publication 2013/0120898) in view of Yoon et al. (US Patent 9,818,547).
In re claim 11, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not explicitly disclose wherein tc/tm is 0.8 or more and 1.0 or less, where a thickness of the 1-1-th electrode layer measured at a center of the body in the first direction is tm and a thickness of the 1-1-th electrode layer measured on the first or second internal electrode disposed at an outermost portion of the body in the first direction is tc.
Yoon discloses minimizing the deviation of the external electrode layer thickness between the central portion of the body and a position proximate to the outermost internal electrode layer, and thus, Yoon discloses tc/tm is 0.8 or more and 1.0 or less, where a thickness of the 1-1-th electrode layer measured at a center of the body in the first direction is tm and a thickness of the 1-1-th electrode layer measured on the first or second internal electrode disposed at an outermost portion of the body in the first direction is tc (col.6 ll.35-42).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to minimize the thickness deviation of the external electrode layer to improve the reliability of the electronic component and prevent permeation of plating solution (col.6 ll.40-46: Yoon).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Publication 2013/0120898) in view of Kim et al. (US Publication 2021/0217560).
In re claim 16, Park discloses the multilayer electronic component of claim 1, as explained above. Park does not disclose wherein an average thickness of the dielectric layer is 0.4 µm or less.
Kim discloses wherein an average thickness of the dielectric layer is 0.4 µm or less (Claim 8).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the invention to adjust the thickness of the dielectric layer to achieve a device having desired capacitance.
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the 1-2th electrode layer is in contact with the third surface, and the 2-2th electrode is in contact with the fourth surface.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the 1-2-th electrode layer is in contact with the corner connecting the first surface and the third surface and the corner connecting the second surface and the third surface, and the 2-2-th electrode is in contact with the corner connecting the first surface and the fourth surface and the corner connecting the second surface and the fourth surface.
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the average thickness of the 1-2-th electrode layer is greater than the average thickness of the 1-1-th electrode layer.
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art does not teach nor suggest (in combination with other claim limitations) the metal contained in the 1-2-th electrode layer is different than the metal contained in the 1-3-th electrode layer, and the metal contained in the 2-2th electrode layer is different than the metal in the 2-3-th electrode layer.
Claims 19-26 are allowed. The prior art does not teach nor suggest (in combination with other claim limitations) a multilayer capacitor having a first external electrode disposed on one end surface and a second external electrode disposed on an opposing second end surface. The first external electrode includes a 1-1-th plating electrode disposed on the first end surface, a 1-2-th electrode layer disposed on the 1-1-th electrode layer, and a 1-3-th electrode layer connected to the 1-2-th electrode layer and is disposed on first and second main surfaces. The second external electrode includes a 2-1-th plating electrode disposed on the second end surface, a 2-2-th electrode layer disposed on the 2-1-th electrode layer, and a 2-3-th electrode layer connected to the 2-2-th electrode layer and is disposed on first and second main surfaces. The 1-2-th and the 2-2-th electrode layers include a greater content of glass than that of the 1-3-th electrode layer and 2-3-th electrode layer, respectively.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Park et al. (US Publication 2013/0050896) [¶35], [¶43]
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARUN RAMASWAMY whose telephone number is (571)270-1962. The examiner can normally be reached Monday - Friday, 9:00 am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Dole can be reached at (571) 272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ARUN RAMASWAMY/ Primary Examiner, Art Unit 2847
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