Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 2, 11, 12, 21, 22, 29, 30, and 39, is/are rejected under 35 U.S.C. 103 as being unpatentable over to Vijayaraghavan et al. (US 2009/0076753), sited in IDS filed on 09/17/23 and Huang et al., (US 2016/0131708) in IDS filed on 4/23/2024.
As per claim 1, Vijayaraghavan teaches an input/output (I/O) block of a semiconductor integrated circuit (IC) (note the input buffer, 610 is part of an I/O block ([0068]), “..delay characterization module 210 can be used for multi-voltage I/Os (with different pad and core voltages) and single-voltage I/Os), the I/O block comprising: an I/O buffer (receiving buffer, 610) coupled to a remote I/O block via a communication channel defining a signal path (note buffer 610 defines two signal paths, Fig. 7) ; and an I/O sensor (606) configured to generate an output signal ( Fig. 7) indicative of an eye pattern parameter of the signal path (connected to the two signal paths).
However, another related art also discloses a semiconductor integrated circuit; specifically, Huang teaches an I/O sensor (CoWoS) for a multi-IC module (Fig.1, [0021]) a first IC die (101) comprising an I/O
At the time the invention, it would have been obvious to a person of ordinary skill in the art effective filing date of the claimed invention to implement determining the eye width from start to end time ([0058-0059]) and the interconnect quality parameter is an eye pattern parameter taught by Huang with Vijayaraghavan. Doing so would improve performance parameters of the IC therein obtaining optimum device performance. (Huang, [0004, 0051]
As per claim 2, Vijayaraghavan with Huang teaches wherein the least one I/O buffer comprises a transmission buffer, the at least one signal path comprising a first signal path coupled to an output of the transmission buffer that is coupled to the communication channel, the first signal path being further coupled to the remote I/O block via at least one connection bump (Vigayaraghavan teaches special I/O transmission buffer effect that test near end load on the I/O buffer, [0078-0091]), the output signal of the I/O sensor being further indicative of a quality of the at least one connection bump.
As per claim 11, Huang teaches wherein the eye pattern parameter is selected from the group consisting of: eye width; eye height; eye width jitter; and eye height fluctuation. (Huang teaches determining the eye width from start to end time ([0058-0059]) and the interconnect quality parameter is an eye pattern parameter. Fig. 13, [0021])
As per claim 12, Huang teaches wherein the output signal comprises a pulse having a width indicative of the eye pattern parameter. (Huang teaches determining the eye width from start to end time ([0058-0059]) and the interconnect quality parameter is an eye pattern parameter. Fig. 13, [0021])
As per claim 21, see the rejection for claim 1.
As per claim 22, see the rejection for claim 2.
As per claim 29, see the rejection for claim 11.
As per claim 30, see the rejection for claim 12.
note the input buffer, 610 is part of an I/O block ([0068]), “..delay characterization module 210 can be used for multi-voltage I/Os (with different pad and core voltages) and single-voltage I/Os), the I/O block comprising: an I/O buffer (receiving buffer, 610) coupled to a remote I/O block via a communication channel defining a signal path (note buffer 610 defines two signal paths, Fig. 7) ; and an I/O sensor (606) configured to generate an output signal ( Fig. 7) indicative of an eye pattern parameter of the signal path (connected to the two signal paths).
As per claim 39, Vijayaraghavan with Huang teaches a non-transitory computer-readable medium having stored thereon an encoding of a semiconductor integrated circuit (IC), the IC comprising: an I/O buffer coupled to an interconnect that couples the IC to a different IC (Vijayaraghavan, the input buffer, 610 is part of an I/O block ([0068]); a first signal path and a second signal path (note buffer 610 defines two signal paths, Fig. 7), each coupled to the I/O buffer or to the interconnect; and an I/O sensor (606) coupled to the (Huang teaches option b) first and second signal paths and configured to generate an output signal indicative of at least one of:(a) a timing difference between a signal edge of the first signal path and a signal edge of the second signal path, or (b) an eye pattern parameter of the first or second signal paths. See the rejection for claim 1 and Huang teaches option B. Huang teaches an I/O sensor (CoWoS) for a multi-IC module (Fig.1, [0021]) a first IC die (101) comprising an I/O
Allowable Subject Matter
Claims 5-10, 13-20, 23-28, and 31-38 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Related Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Huang (US 9,766,288), teaches a semiconductor testing, and more particularly to eye diagram capture devices, systems, and methods, and even more particularly to an on-chip eye diagram capture device, system and method for a chip-on-wafer-on-substrate (CoWoS) flow. [see entire document].
Conclusion
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R.I .Hi(c). In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAMMARA R PEYTON whose telephone number is (571)272-4157. The examiner can normally be reached on 9am-5pm, EST M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TAMMARA R PEYTON/Primary Examiner, Art Unit 2184 September 30, 2026
