Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner's responses to Applicant's remark
Applicant has amended claim 21 and added new claim 22. Claims 1-12, 14-19, 21, and 22 are currently pending.
Applicant’s arguments, filed 06/20/2025, have been fully considered but they are not persuasive. Specifically, Applicant asserts:.
“Yu discloses integrating an image sensor and an Al engine (for CNN modeling) into a same semiconductor substrate, Yokoyama differs from Yu in that Yokoyama teaches a multi-substrate image sensor compared to Yu's teachings of a single substrate image sensor. FIGS. 6A and 6B of Yu (reproduced below) illustrate the single substrate image sensor.
In view of FIGS. 6A and 6B, and the rest of Yu's teachings, one of ordinary skill in the art would understand that the image sensor (602) and the memory cells (404) with the Al engine should be disposed on the same semiconductor substrate. Therefore, contrary to the Office's assertions, one of ordinary skill in the art would not find it obvious to modify the image sensor of Yokoyama with Yu because Yokoyama teaches that the memory and the image sensor are disposed on different substrates, not the same semiconductor substrate. The knowledge to locate the memory on a substrate that is separate and distinct from a substrate of the image sensor is only found in Applicant's originally-filed disclosure, for example, FIGS. 3-15 and the corresponding description of FIGS. 3- 15. Thus, the Office's obviousness reasoning is deficient and fails to establish a prima facie case of obviousness with respect to claim 1 because Yu teaches co-locating the image sensor and the memory cells with the CNN model on the same semiconductor substrate”.
The Examiner respectfully disagrees. As presented by the Examiner in the previous office action Yokoyama discloses a stacked sensor configuration comprising a first layer (300) with a pixel array (310), a second layer (200) with an ADC/Logic circuit (280A/110) and a third layer (100) with CPU (160) and a memory (150). Examiner conceded particularly that Yokoyama does not teach the memory “that stores therein a neural network computing model” and YU was solely and mainly relied on to disclose a memory cells 406 programmed with full set of trained parameters for a CNN model (Figs. 1-6, [0026], [0035], [0037]&[0048]: CNN logic circuits 404). Examiner point out that empowering Yokoyama’s memory with YU‘s CNN model will accelerate processing and reduce power consumption (YU: [0058]). Additionally, Examiner reiterated that Yokoyama teaches that the memory and the image sensor are disposed on different substrates as recited in claim 1, wherein the memory can embed a CNN computing model as taught by YU prior art. Based on the foregoing analysis, the Examiner respectfully stands behind the teachings of Yokoyama in view of YU, as applied in the 35 U.S.C. rejection to independent claims 1 and 16 (see rejection, infra).
Double Patenting
The no statutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A no statutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longa, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Orne, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Regarding Claims 1-15, are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over respective claims 1-15 of U.S. Patent No. 11,792,551 B2 as depicted in the Table below. Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-15 of the instant application are broader in scope over claims 1-15 of U.S. Patent 11,792,551 B2, in that claims 1-15 of the U.S. Patent contain all the limitations of claims 1-15 of the instant application. Claims 1-15 of the instant application are therefore not patently distinct from the earlier U.S. Patent claim and such are unpatentable for obvious-type double patenting.
Claim 1 is rejected under nonstatutory obviousness-type double patenting as being unpatentable over claim 1 of the US 11792551 B2 patent as applied below (see table below), in view of Yokoyama et al. (US 20180240797 A1, hereinafter “Yokoyama”).
Regarding claim 1, the Claim 1 is rejected under nonstatutory obviousness-type double patenting as being unpatentable over the US 11792551 B2, except thesecond layer is stacked directly on the third layer in a stacking direction, and the first layer is stacked directly on the second layer in the stacking direction.
However, Yokoyama discloses the second layer is stacked directly on the third layer in a stacking direction, and the first layer is stacked directly on the second layer in the stacking direction (as illustrated by Figs. 19: first substrate 100, second substrate 200 and a third substrate 300 are layout out in stacking direction configuration).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to the second layer is stacked directly on the third layer in a stacking direction, and the first layer is stacked directly on the second layer in the stacking direction as taught by Yokoyama into the US 11,792,551. The suggestion/ motivation for doing so would be for easier manufacturing while reducing a mounting area (Yokoyama: [0008]).
Claim 21 is rejected under nonstatutory obviousness-type double patenting as being unpatentable over US 11792551 B2 patent and Yokoyama combination as applied above, in view of Takayanagi et. (US 20170162625 A1, hereinafter “Takayanagi”).
Regarding claim 21, claim 21 has been analyzed and rejected with regard to claim 1 as applied above, except further comprising: an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the processing section in the stacking direction, wherein the processing section has a second surface area, and wherein the first surface area is equal to or greater than the second surface area.
However, Takayanagi discloses an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the memory in the stacking direction, wherein the memory has a second surface area, and wherein the first surface area is equal to or greater than the second surface area (Fig. 4, [0018]-[0019]: an image sensor 1C configuration employing a stacked architecture stacked in which a shielding layer 13 is disposed between a photodiode array substrate 11 and a storage node array area on a substrate 12. The surfaces area for the photodiode array 11 and the storage array 13 are equal, Further in [0092] the shielding layer is made of metal layers. Examiner point out that using metal layers as EMI shield is known to decrease the influence of electromagnetic waves between the layers (see US 20140014813 A1)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the memory in the stacking direction, wherein the memory has a second surface area, and wherein the first surface area is equal to or greater than the second surface area as taught by Takayanagi into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to provide an integrated circuit system having first and second device wafers that are stacked and bonded together including integrated electromagnetic interference (EMI) shielding used to reduce or eliminate fixed pattern noise (see Mao US 20140014813 A1: [0024]).
Instant application
US 11,792,551 B2
1. A stacked light receiving sensor comprising:
a first substrate that forms a first layer;
a second substrate that is joined with the
first substrate and that forms a second layer;
a third substrate that is joined with the
second substrate and that forms a third layer;
a pixel array section that includes a plurality of unit pixels arranged two-dimensionally in a matrix and that outputs a pixel signal;
an analog circuit that reads the pixel signal from the pixel array section and outputs a first image signal;
a logic circuit that is connected to the analog circuit and that executes signal processing on the first image signal and outputs a second image signal;
a memory that stores therein a neural network computing model;
a processing section that executes processing based on the neural network computing model, on data based on the second image signal;
and an output section that outputs a processing result at least based on the neural network computing model to an outside,
wherein the pixel array section is disposed on the first layer, the analog circuit is disposed the first layer, the second layer, the third layer, or a combination thereof, the logic circuit, the processing section, and the memory are disposed on the second layer, the third layer, or a combination thereof,
1. A stacked light receiving sensor comprising:
a first substrate that forms a first layer; a
second substrate that is joined with the first substrate and that forms a second layer;
a third substrate that is joined with the second substrate and that forms a third layer;
a pixel array section that includes a plurality of unit pixels arranged two-dimensionally in a matrix;
an analog circuit that reads a pixel signal from the pixel array section;
a logic circuit that is connected to the analog circuit and that outputs the pixel signal;
a memory that stores therein a neural network computing model;
a processing section that executes processing based on the neural network computing model, on data based on the pixel signal;
and an output section that outputs a processing result at least based on the neural network computing model to an outside,
wherein the pixel array section is disposed on the first layer, the analog circuit is disposed on any one or more of the first to third layers, and the logic circuit, the processing section, and the memory are disposed on any one or more of the second and third layers,
wherein a first area defined by a first perimeter of the first substrate, a second area defined by a second perimeter of the second substrate, and a third area defined by a third perimeter of the third substrate substantially overlap each other from a plan view.
2. The stacked light receiving sensor according to claim 1, wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder.
3. The stacked light receiving sensor according to claim 2, wherein the vertical drive circuit and the vertical decoder are disposed on different layers.
4. The stacked light receiving sensor according to claim 1, wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer.
5. The stacked light receiving sensor according to claim 4, wherein the comparator and the counter are disposed on different layers.
6. The stacked light receiving sensor according to claim 4, wherein the analog circuit further includes a digital to analog converter that is disposed on the second layer or the third layer.
7. The stacked light receiving sensor according to claim 6, wherein the comparator and the digital to analog converter are disposed on a same layer.
8. The stacked light receiving sensor according to claim 4, wherein the logic circuit includes a signal processing section that is disposed on a same layer as the counter.
9. The stacked light receiving sensor according to claim 8, wherein the logic circuit further includes a timing adjustment circuit that is disposed on a same layer as the signal processing section.
10. The stacked light receiving sensor according to claim 8, wherein the processing section is disposed on the same layer as the counter and the signal processing section.
11. The stacked light receiving sensor according to claim 1, wherein the memory and the processing section are disposed on a same layer.
12. The stacked light receiving sensor according to claim 1, wherein the analog circuit is connected to a first power supply, and the logic circuit is connected to a second power supply.
13. The stacked light receiving sensor according to claim 12, wherein the first power supply differs from the second power supply.
14. The stacked light receiving sensor according to claim 1, further comprising: a fourth substrate that forms the third layer by being joined with the second substrate separately from the third substrate, wherein the processing section is disposed on the fourth substrate.
15. The stacked light receiving sensor according to claim 1, wherein the analog circuit is disposed on the first layer.
2. The stacked light receiving sensor according to claim 1, wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder.
3. The stacked light receiving sensor according to claim 2, wherein the vertical drive circuit and the vertical decoder are disposed on different layers.
4. The stacked light receiving sensor according to claim 1, wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer.
5. The stacked light receiving sensor according to claim 4, wherein the comparator and the counter are disposed on different layers.
6. The stacked light receiving sensor according to claim 4, wherein the analog circuit further includes a digital to analog converter that is disposed on the second layer or the third layer.
7. The stacked light receiving sensor according to claim 6, wherein the comparator and the digital to analog converter are disposed on a same layer.
8. The stacked light receiving sensor according to claim 4, wherein the logic circuit includes a signal processing section that is disposed on a same layer as the layer on which the counter is disposed.
9. The stacked light receiving sensor according to claim 8, wherein the logic circuit further includes a timing adjustment circuit that is disposed on a same layer as the layer on which the signal processing section is disposed.
10. The stacked light receiving sensor according to claim 8, wherein the processing section is disposed on a same layer as the layer on which the signal processing section is disposed.
11. The stacked light receiving sensor according to claim 1, wherein the memory and the processing section are disposed on a same layer.
12. The stacked light receiving sensor according to claim 1, wherein the analog circuit is connected to a first power supply, and the logic circuit is connected to a second power supply.
13. The stacked light receiving sensor according to claim 12, wherein the first power supply differs from the second power supply.
14. The stacked light receiving sensor according to claim 1, further comprising: a fourth substrate that forms the third layer by being joined with the second substrate separately from the third substrate, wherein the processing section is disposed on the fourth substrate.
15. The stacked light receiving sensor according to claim 1, wherein the analog circuit is disposed on the first layer.
Claims 16-19 are rejected under nonstatutory obviousness-type double patenting as being unpatentable over claims 1-5 of the US 11792551 B2 patent as applied below (see table below), in view of Yokoyama et al. (US 20180240797 A1, hereinafter “Yokoyama”).
Regarding claim 16, the Claim 16 is rejected under nonstatutory obviousness-type double patenting as being unpatentable over the US 11792551 B2 in view of Yokoyama and same as applied to rejection of claim 1 above (see supra claim 1 rejection) except a conductive material that is disposed between the processing section and the pixel array section.
However, Yokoyama discloses a conductive material that is disposed between the processing section and the pixel array section (Fig. 18: conductive layer 61 between the second substrate 200 and the third substrate 300).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a conductive material that is disposed between the processing section and the pixel array section as taught by Yokoyama into the US 11792551. The suggestion/ motivation for doing so would be to allow electrical contact and transfer of data between the substrates.
16. A stacked light receiving sensor comprising: a first substrate that forms a first layer; a second substrate that is joined with the first substrate and that forms a second layer; a third substrate that is joined with the second substrate and that forms a third layer; a pixel array section that includes a plurality of unit pixels arranged two-dimensionally in a matrix and that outputs a pixel signal; an analog circuit that reads the pixel signal from the pixel array section and outputs a first image signal; a logic circuit that is connected to the analog circuit and that executes signal processing on the first image signal and outputs a second image signal; a memory that stores therein a neural network computing model; a processing section that executes processing based on the neural network computing model, on data based on the second image signal; an output section that outputs a processing result at least based on the neural network computing model; , wherein the pixel array section is disposed on the first layer, the analog circuit is disposed on the first layer, the second layer, the third layer, or a combination thereof, the logic circuit, the processing section, and the memory are disposed on the second layer, the third layer, or a combination thereof,
17. The stacked light receiving sensor according to claim 16, wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder.
18. The stacked light receiving sensor according to claim 17, wherein the vertical drive circuit and the vertical decoder are disposed on different layers.
19. The stacked light receiving sensor according to claim 16, wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer.
1. A stacked light receiving sensor comprising: a first substrate that forms a first layer; a second substrate that is joined with the first substrate and that forms a second layer; a third substrate that is joined with the second substrate and that forms a third layer; a pixel array section that includes a plurality of unit pixels arranged two-dimensionally in a matrix; an analog circuit that reads a pixel signal from the pixel array section; a logic circuit that is connected to the analog circuit and that outputs the pixel signal; a memory that stores therein a neural network computing model; a processing section that executes processing based on the neural network computing model, on data based on the pixel signal; and an output section that outputs a processing result at least based on the neural network computing model to an outside, wherein the pixel array section is disposed on the first layer, the analog circuit is disposed on any one or more of the first to third layers, and the logic circuit, the processing section, and the memory are disposed on any one or more of the second and third layers, wherein a first area defined by a first perimeter of the first substrate, a second area defined by a second perimeter of the second substrate, and a third area defined by a third perimeter of the third substrate substantially overlap each other from a plan view.
2. The stacked light receiving sensor according to claim 1, wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder.
3. The stacked light receiving sensor according to claim 2, wherein the vertical drive circuit and the vertical decoder are disposed on different layers.
4. The stacked light receiving sensor according to claim 1, wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 11, 16 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Yokoyama et al. (US 20180240797 A1, hereinafter “Yokoyama”), in view of YU et al. (US 20200042888 A1, hereinafter “YU”).
Regarding claim 1, Yokoyama teaches a stacked light receiving sensor (Figs. 17&19: semiconductor device 6C) comprising:
a first substrate that forms a first layer (Fig. 19: third substrate 300);
a second substrate that is joined with the first substrate and that forms a second layer (Fig. 19: a second substrate 200);
a third substrate that is joined with the second substrate and that forms a third layer (Fig. 19: a first substrate 100);
a pixel array section that includes a plurality of unit pixels arranged two-dimensionally in a matrix and that outputs a pixel signal (Fig. 19, [0127]: pixel unit 310, unit pixels are two-dimensionally arranged);
an analog circuit (Fig. 19: part of ADC circuit 280A) that reads the pixel signal from the pixel array section and outputs a first image signal; a logic circuit (Fig. 19: part of ADC circuit 280A) that is connected to the analog circuit and that executes signal processing on the first image signal and outputs a second image signal (Fig. 19, [0127]: the ADC circuit 280A (as claimed “analog circuit/ logic circuit”) converts an analog signal outputted from a unit pixel provided in the pixel unit into a digital signal and outputs a digital signal.);
a memory Fig. 19, [0127]: a memory 150);
a processing section that executes processing based on the neural network computing model, on data based on the second image signal; (Fig. 19, [0097]&[0130]: a programmable circuit 160, to enable change or automatization of operations of imaging device on an as-needed basis, includes a FPGA (field-programmable gate array) and a CPU (central processing unit). Examiner notes that FPGAs are a type of hardware that are used to accelerate CNNs);
and an output section that outputs a processing result Fig. 19, [0127]: an external communication function 280B),
wherein the pixel array section is disposed on the first layer (Fig. 19: the pixel unit 310, on the third substrate 300), the analog circuit is disposed on the first layer, the second layer, the third layer, or a combination thereof (Fig. 19: the ADC circuit 280A, on the second substrate 200), and the logic circuit (280A), the processing section (160), and the memory (150) are disposed on the second layer (200), the third layer (100), or a combination thereof (layout as illustrated by Fig. 19),
the second layer is stacked directly on the third layer in a stacking direction, and the first layer is stacked directly on the second layer in the stacking direction (as illustrated by Figs. 19: first substrate 100, second substrate 200 and a third substrate 300 are layout out in stacking direction configuration).
Yokoyama does not teach the memory that stores therein a neural network computing model; processing section that executes processing based on the neural network computing model and the processing result is at least based on the neural network computing model.
However, YU discloses a memory that stores therein a neural network computing model (Fig. 4A&6A, [0048]: Memory cells 406 programmed with full set of trained parameters for a CNN model); processing section (Fig. 4A&6A, [0048]: CNN logic circuits 404) that executes processing based on the neural network computing model and the processing result is at least based on the neural network computing model (Figs. 1-6, [0026], [0035]&[0037]: signal detected by an image sensor 112 (e.g., CCD or CMOS) is converted by an analog to digital converter A/D 114 and processed by a MCU into a form compatible with a data set that is further processed by an AI engine 110 (CNN model trained to produce segmentation of an input image) to be outputted via a network interface 160.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the memory that stores therein a neural network computing model; processing section that executes processing based on the neural network computing model and the processing result is at least based on the neural network computing model as taught by YU into Yokoyama semiconductor device. The suggestion/ motivation for doing so would be to provide a deep learning technique (CNN modeling) within the stacked imaging device to accelerate processing and reduce power consumption (YU: [0058]).
Furthermore, YU discloses integrating image sensor and an AI engine (for CNN modeling) into a same semiconductor substrate. Various implementation of embedding memory cells with a logic circuits of the AI engine 110 in a semiconductor chip, including one layer configuration and multilayer configuration fabrication (Figs 4&6, [0048]&[0052]).
Therefore, considering the teaching of Yokoyama to form a FPGAs (hardware used to accelerate CNNs) in the first substrate 100 (claimed “third layer”), in view of YU’s teaching to integrate image sensor and a single-chip AI engine having CNN logic embedded with memory cells into a same semiconductor substrate (Figs. 4A&6A, [0052]); the resulting combination of which would be predictable by applying the court recognized rational of applying a known technique to a known device (method, or product) ready for improvement to yield predictable results. The suggestion/ motivation for doing so would be to facilitate “efficient reception of light collected by a camera lens assembly from an object field being imaged” (YU: [0052]).
Regarding claim 11, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, in addition YU discloses wherein the memory and the processing section are disposed on a same layer (Figs. 4A&6A, [0048]&[0052]: single-chip AI engine having CNN logic embedded with memory cells into a same layer).
Regarding claim 16, claim 16 has been analyzed and rejected with regard to claim 1 and in accordance with Yokoyama's further teaching on: a conductive material that is disposed between the processing section and the pixel array section (Fig. 18: conductive layer 61 between the second substrate 200 and the third substrate 300. See also YU’s disclosing an interconnection and interface layer 604 included between the CMOS image sensor layers 602 and the memory cells layer 406 and AI logic circuits layer 404 (in FIG. 6A, [0052]).).
Regarding claim 22, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, in addition Yokoyama discloses wherein the memory is disposed only on the third layer (layout as illustrated by Fig. 19A, the memory (150) disposed on the third layer (100), or a combination thereof (layout as illustrated by Fig. 19B)).
Claims 2-3, 15, 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama and YU combination as applied above, in view of Sukegawa et. (US 20120293698 A1, hereinafter “Sukegawa”).
Regarding claim 2, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, except wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder.
However, Sukegawa discloses wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder ( [0173]-[0175] a solid-state image sensor 10D in Figs. 11 and 14-15, the whole of the vertical drive circuit (row scanning circuit) 102 and the vertical decoder 103, and the reference signal supply unit 105 can be mounted on the second chip (lower chip) 12).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the logic circuit includes a vertical decoder that specifies a read row for the plurality of unit pixels, and the analog circuit includes a vertical drive circuit that drives unit pixels in the read row specified by the vertical decoder as taught by Sukegawa into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to reduce the chip size and improve noise reduction (Sukegawa: [0176]).
Regarding claim 3, the Yokoyama, YU and Sukegawa combination teaches the stacked light receiving sensor according to claim 2, in addition Sukegawa discloses wherein the vertical drive circuit and the vertical decoder are disposed on different layers (as illustrated by Fig. 11, the vertical drive circuit 102 and the vertical decoder 103 are mounted on different chips).
Regarding claim 15, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, except wherein the analog circuit is disposed on the first layer.
However, Sukegawa discloses wherein the analog circuit is disposed on the first layer ( [0086]-[0175] a solid-state image sensor 10A, having a stacked structure, in Figs. 4, 5 and 8, a peripheral drive circuits that drive and control the unit pixels of the pixel array unit 101 and analog circuits, which are the vertical drive circuit 102, the comparator 1041 of the column processing unit 104, and the reference signal supply unit 105 are integrated on the same first chip 11 as a pixel array unit 101).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit is disposed on the first layer as taught by Sukegawa into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to reduce the chip size and improve noise reduction (Sukegawa: [0062]&[0176]).
Regarding claim 17, claim 17 has been analyzed with regard to claim 2 and is rejected for the same reasons of obviousness as used above.
Regarding claim 18, claim 18 has been analyzed with regard to claim 3 and is rejected for the same reasons of obviousness as used above.
Claims 4-8, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama and YU combination as applied above, in view of WIPO Patent Publication No. WO 2017209221 A1 to Oka et al. (employing the corresponding US Application US 20210112213 A1 as a translation and hereafter “Oka”).
Regarding claim 4, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, except wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer.
However, Oka discloses wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer (in reference to Fig. 32, and [0417]: comparators 541-1 and 541-2 are formed in a second layer chip 502, and counters 542-1 and 542-2 are formed in a third layer chip 503).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit includes a comparator disposed on the second layer or the third layer, and a counter disposed on the second layer or the third layer as taught by Oka into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to reduce the chip size and improve noise reduction.
Regarding claim 5, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 4, in addition Oka discloses wherein the comparator and the counter are disposed on different layers (In reference to Fig. 32, and [0417]: comparators 541-1 and 541-2 are formed in a second layer chip 502, and counters 542-1 and 542-2 are formed in a third layer chip 503).
Regarding claim 6, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 4, in addition Oka discloses wherein the analog circuit further includes a digital to analog converter that is disposed on the second layer or the third layer (In reference to Fig. 32: comparators 541 and ADC 546 are formed in the third layer chip 503).
Regarding claim 7, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 6, in addition Oka discloses wherein the comparator and the digital to analog converter are disposed on a same layer (In reference to Fig. 32: comparators 541 and ADC 546 are formed in the third layer chip 503).
Regarding claim 8, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 4, in addition Oka discloses wherein the logic circuit includes a signal processing section that is disposed on a same layer as the counter (In reference to Figs. 49-50, [0417]&[0589]: signal processing units 1231 of a third structure 1211, and counters 542 are formed in a third layer chip 852).
Regarding claim 19, claim 19 has been analyzed with regard to claim 4 and is rejected for the same reasons of obviousness as used above.
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama, YU and Oka combination as applied above, in view of Nakajima et. (US 20170155865 A1, hereinafter “Nakajima”).
Regarding claim 9, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 8, except wherein the logic circuit further includes a timing adjustment circuit that is disposed on a same layer as the signal processing section.
However, Nakajima discloses wherein the logic circuit further includes a timing adjustment circuit that is disposed on a same layer as the signal processing section (as illustrated by Figs. 14-16, a timing control circuit 107, and an image signal processing unit 108 are disposed on the third layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the logic circuit further includes a timing adjustment circuit that is disposed on a same layer as the signal processing section as taught by Nakajima into the Yokoyama, YU and Oka combination. The suggestion/ motivation for doing so would be to make the chip of the solid-state image sensor smaller (Nakajima: [0163]).
Regarding claim 10, the Yokoyama, YU and Oka combination teaches the stacked light receiving sensor according to claim 8, except wherein the processing section is disposed on the same layer as the counter and the signal processing section.
However, Nakajima discloses wherein the processing section is disposed on the same layer as the counter and the signal processing section (as illustrated by Figs. 14-16, a column processing unit 104-1, and an image signal processing unit 108 are disposed on the third layer).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the processing section is disposed on the same layer as the counter and the signal processing section as taught by Nakajima into the Yokoyama, YU and Oka combination. The suggestion/ motivation for doing so would be to make the chip of the solid-state image sensor smaller (Nakajima: [0163]).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama and YU combination as applied above, in view of Sato et. (US 20140015600 A1, hereinafter “Sato”).
Regarding claim 12, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, except wherein the analog circuit is connected to a first power supply, and the logic circuit is connected to a second power supply.
However, Sato discloses wherein the analog circuit is connected to a first power supply (Fig. 4, [0030]-[0033]: analog circuits are electrically connected to a power supply source AVSS), and the logic circuit is connected to a second power supply (Fig. 4, [0039]-[0042]: logic circuit region is electrically connected to a power supply source DVSS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the analog circuit is connected to a first power supply, and the logic circuit is connected to a second power supply as taught by Sato into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to provide uniform power can be supplied to the peripheral region (Sato: [0047]).
Regarding claim 13, the Yokoyama, YU and Sato combination teaches the stacked light receiving sensor according to claim 12, in addition Sato discloses wherein the first power supply differs from the second power supply (Fig. 4, [0030]-[0039]: the power supply source AVSS and the power supply source DVSS).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama and YU combination as applied above, in view of Shimauchi et. (US 20190158732 A1, hereinafter “Shimauchi”).
Regarding claim 14, the Yokoyama and YU combination teaches the stacked light receiving sensor according to claim 1, except further comprising: a fourth substrate that forms the third layer by being joined with the second substrate separately from the third substrate, wherein the processing section is disposed on the fourth substrate.
However, Shimauchi discloses a fourth substrate that forms the third layer by being joined with the second substrate separately from the third substrate, wherein the processing section is disposed on the fourth substrate ([0093]: a stacked image sensor can be configured as a stacked substrate of four or more layers in addition to a two-layer substrate or a three-layer substrate)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate a fourth substrate that forms the third layer by being joined with the second substrate separately from the third substrate, wherein the processing section is disposed on the fourth substrate as taught by Shimauchi into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to expand stacked image sensor functionality and operations.
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over the Yokoyama and YU combination as applied above, in view of Takayanagi et. (US 20170162625 A1, hereinafter “Takayanagi”).
Regarding claim 21, claim 21 has been analyzed and rejected with regard to claim 1 as applied above, except an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the memory in the stacking direction, wherein the memory has a second surface area, and wherein the first surface area is equal to or greater than the second surface area.
However, Takayanagi discloses an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the memory in the stacking direction, wherein the memory has a second surface area, and wherein the first surface area is equal to or greater than the second surface area (Fig. 4, [0018]-[0019]: an image sensor 1C configuration employing a stacked architecture stacked in which a shielding layer 13 is disposed between a photodiode array substrate 11 and a storage node array area on a substrate 12. The surfaces area for the photodiode array 11 and the storage array 13 are equal, Further in [0092] the shielding layer is made of metal layers. Examiner point out that using metal layers as EMI shield is known to decrease the influence of electromagnetic waves between the layers (see US 20140014813 A1)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate an electromagnetic shield having a first surface area; the electromagnetic shield is disposed between the pixel array section and the memory in the stacking direction, wherein the memory has a second surface area, and wherein the first surface area is equal to or greater than the second surface area as taught by Takayanagi into the Yokoyama and YU combination. The suggestion/ motivation for doing so would be to provide an integrated circuit system having first and second device wafers that are stacked and bonded together including integrated electromagnetic interference (EMI) shielding used to reduce or eliminate fixed pattern noise (see Mao US 20140014813 A1: [0024]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ye Lin can be reached on 571-272-7372. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638