Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 - 18 in the reply filed on 01/05/2026 is acknowledged.
Claims 19 - 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/05/2026.
Information Disclosure Statement
The information disclosure statements (IDS) were submitted on 09/18/2023, 09/19/2023, and 02/11/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "plurality of integrated circuit elements formed on a semiconductor substrate" must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. The drawings appear to show a substrate 10 and the graphene layer 11, but the plurality of integrated circuit elements formed on the semiconductor substrate as claimed in claims 2 and 9 do not appear in the drawings. The plurality of integrated circuit elements should be shown in the drawings or removed from the claims.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 4 is objected to because of the following informalities:
Claim 4 states “…where the one or more polymer ILD lay comprises one…”. It appears the term “lay” is supposed to be “layers”, referring to the ILD layers introduces in claim 1. The term “lay” should be corrected to “layers”.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4, 7 – 8, 12, 14, and 17 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 10134630 B2 hereinafter Ham.
For claim 1, Ham teaches “A method of making an integrated circuit, comprising: providing an integrated circuit structure (Col. 8 ln 46 – 50) comprising one or more polymer interlayer dielectric (ILD) layers (fig. 3 numeral 10a and 10b; Col. 5 ln 7 – 17; Col. 8 ln 61 – Col. 9 ln 5; Col. 9 ln 43 – Col. 10 ln 11) formed over a first conductive wiring line layer (fig. 3 numeral 30); and selectively processing an exposed portion of the one or more polymer ILD layers by applying irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer (fig. 3 S306 – S316 shows the process of exposing carbon source 30 and catalyst layer 20a, a conductive metal layer, through etching the ILD layers 10a and 10b, and then applying a radiation treatment at step S316; Col. 3 ln 20 – 23; Col. 7 ln 8 – 12).”
For claim 4, Ham teaches “The method of claim 1, where the one or more polymer ILD lay comprises one or more non-photosensitive, carbon-containing polymer layers (Col. 4 ln 64 – Col. 5 ln 6: Col. 5 ln 23 – 53) which respond to irradiation form a laser source (Col. 3 ln 20 – 23; Col. 7 ln 8 – 12) to form the graphene interconnect structure directly from the exposed portion of the one or more non-photosensitive, carbon-containing polymer layers (fig. 3 numeral 40, 40a, and 40b; fig. 1 numeral 40; Col. 8 ln 61 – Col. 9 ln 5).” The lasers and light sources used in Ham include ultraviolet light and figure 3 shows the carbon sources being directly treated by heat source, which include the laser and light sources. As such, Ham appears to teach a non-photosensitive, carbon-containing polymer layer that responds to irradiation from a laser source to form the graphene interconnect structure. Further, Ham teaches the carbon source being a fluorinated polyimide film (Col. 2 ln 55 – Col. 3 ln 9) along with other materials similar to or matching the materials used in the immediate invention as described in the specification as non-photosensitive carbon-containing polymer dielectric material (immediate invention Par. [025]). As Ham teaches the same materials used in the interlayer dielectric layers as the immediate invention, Ham appears to teach a non-photosensitive, carbon-containing polymer layer.
For claim 7, Ham teaches “The method of claim 1, where the graphene interconnect structure comprises a graphene wiring line layer (fig. 3 numeral 40b) connected to the first conductive wiring layer (fig. 3 numeral 40) with a graphene via structure that is position to completely cover a maximized overlapping region between the graphene wiring line layer and first conductive wiring line layer (fig. 3 numeral 40a shows a graphene via connecting graphene wiring line layer 40b and the first conductive wiring line layer 40, and the via 40a fully overlaps both 40 and 40b, and therefore covers the overlapping region between the two structures).”
For claim 8, Ham teaches “A method for forming a graphene interconnect structure, comprising: forming a first conductive layer (fig. 3 numeral 30) over a first dielectric layer (fig. 3 numeral 10); forming one or more polyimide dielectric layers over the first conductive layer (fig. 3 numeral 10a, 10b; ; Col. 5 ln 7 – 17; Col. 8 ln 61 – Col. 9 ln 5; Col. 9 ln 43 – Col. 10 ln 11); selectively applying irradiation (fig. 3 step S316; Col. 3 ln 20 – 23; Col. 7 ln 8 – 12) to convert the one or more polyimide dielectric layers into the graphene interconnect structure comprising a graphene line (fig. 3 numeral 40b) formed in an upper portion of the first polyimide dielectric layer and a graphene via (fig. 3 numeral 40a) structure formed in the first polyimide dielectric layer to directly, electrically connect the graphene wiring line to the first conductive layer (fig. 3 numeral 30 shown as 40 after heat treatment shown in step S316).”
For claim 12, Ham teaches “The method of claim 8, where forming one or more polyimide dielectric layers comprises deposing and planarizing a non-photosensitive, carbon-containing polymer dielectric layer (Col. 4 ln 64 – Col. 5 ln 6: Col. 5 ln 23 – 53; fig. 2 shows carbon source 30 planarized from step S204 to step S206; Col. 8 ln 24 - 31) which responds to irradiation from a laser source to form the graphene interconnect structure directly from the exposed portion of the non-photosensitive, carbon-containing polymer layer (fig. 3 numeral 40, 40a, and 40b; fig. 1 numeral 40; Col. 8 ln 61 – Col. 9 ln 5).” The lasers and light sources used in Ham include ultraviolet light and figure 3 shows the carbon sources being directly treated by heat source, which include the laser and light sources. As such, Ham appears to teach a non-photosensitive, carbon-containing polymer layer that responds to irradiation from a laser source to form the graphene interconnect structure. Further, Ham teaches the carbon source being a fluorinated polyimide film (Col. 2 ln 55 – Col. 3 ln 9) along with other materials similar to or matching the materials used in the immediate invention as described in the specification as non-photosensitive carbon-containing polymer dielectric material (immediate invention Par. [025]). As Ham teaches the same materials used in the interlayer dielectric layers as the immediate invention, Ham appears to teach a non-photosensitive, carbon-containing polymer layer.
For claim 14, Ham teaches “The method of claim 8, where the graphene interconnect structure comprises a graphene wiring line layer (fig. 3 numeral 40b) connected to the first conductive wiring layer (fig. 3 numeral 40) with a graphene via structure that is position to completely cover a maximized overlapping region between the graphene wiring line layer and first conductive wiring line layer (fig. 3 numeral 40a shows a graphene via connecting graphene wiring line layer 40b and the first conductive wiring line layer 40, and the via 40a fully overlaps both 40 and 40b, and therefore covers the overlapping region between the two structures).”
For claim 17, Ham teaches “The method of claim 8, further comprising planarizing the graphene wiring line with a top surface of the one or more polyimide dielectric layers (fig. 1 step 104 to step 106; fig. 2 step 204 to 206; fig. 3 step 305 – 310).”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10134630 B2 hereinafter Ham in further view of US 20240413075 A1 hereinafter Lee.
For claim 2, Ham teaches all of claim 2. Ham is silent regarding the semiconductor substrate including a plurality of integrated circuit elements formed on the substrate and covered by the initial ILD layer and the one or more polymer ILD layers. Ham does teach the first substrate including an integrated circuit element (Ham, fig. 3 numeral 40) and that the process can be repeated (fig. 3 shows continued layers above the last ILD layer 10b). Ham also teaches the interconnect structures being used in integrated circuits and other semiconductor devices (Col. 1 ln 46 – 51).
Lee teaches an integrated circuit device (Lee, fig. 1) with multiple integrated circuit elements (fig. 1 numeral 112) on a substrate (fig. 1 numeral 21) and covered by multiple interlayer dielectric layers (fig. 1 numeral 111, 131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple integrated circuit elements in Lee with the graphene interconnect structures in Ham in order to create devices capable of multiple functions such as sensors, memory, transistors, etc. (Lee, Par. [0014]) while improving the devices electrical conductivity and the interconnect structure’s stability (Ham, Col. 3 ln 51 – 60).
For claim 9, Ham teaches all of claim 8. Ham also teaches forming a first graphene layer on the first dielectric layer (Ham, fig. 3 numeral 40b). Ham is silent regarding the first dielectric layer covering a plurality of integrated circuit elements on a semiconductor substrate. Ham does teach an element (fig. 3 numeral 40) on a substrate (fig. 3 numeral 10) that is covered by a dielectric layer (fig. 3 numeral 10a).
Lee teaches an integrated circuit device (Lee, fig. 1) with multiple integrated circuit elements (fig. 1 numeral 112) on a substrate (fig. 1 numeral 21) and covered by multiple interlayer dielectric layers (fig. 1 numeral 111, 131).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple integrated circuit elements in Lee with the graphene interconnect structures in Ham in order to create devices capable of multiple functions such as sensors, memory, transistors, etc. (Lee, Par. [0014]) while improving the devices electrical conductivity and the interconnect structure’s stability (Ham, Col. 3 ln 51 – 60).
Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10134630 B2 hereinafter Ham in further view of CN 114208405 A hereinafter Kanou.
For claim 16, Ham teaches all of claim 8. Ham does not explicitly state that the laser used is a femto-second UV laser source. However, Ham does teach the radiation source comprising UV light and that the source can be laser (Ham, Col. 3 ln 20 – 23).
Kanou teaches a manufacturing a semiconductor device including etching a dielectric layer (Kanou, fig. 11 numeral 1) to create a via (fig. 11 numeral 2) through the use of a UV laser that may be a femto-second laser (Par. [0087]; “In addition, the laser can be used by the CO2 laser, UV laser, microsecond the femto-second laser. UV laser, CO2 laser is simple, so as to preferably.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the femto-second laser in Kanou with the laser heat treatment in Ham in order to increase the precision of etching the interlayer dielectric layers (Kanou, Par. [0073]).
Allowable Subject Matter
Claims 3, 5 – 6, 10 – 11, 13, 15, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 3, Ham, Lee, and Kanou teach ultra-low-k photosensitive materials including polymers that respond to radiation. Ham, Lee, and Kanou are silent regarding an ion exchange used to impregnate a metal into the exposed portion of the one or more polymer ILD layers.
For claim 5, Ham, Lee, and Kanou are silent regarding forming and patterning a first and second resist material on the one or more polymer ILD layers, and also applying a metal solution soak. Ham, Lee, and Kanou to teach a heat treatment and applying radiation from a light source to the exposed portions of the ILD layers.
For claim 6, Ham, Lee, and Kanou are silent regarding forming and patterning a first and second resist material.
For claim 10, Ham, Lee, and Kanou are silent regarding an ion exchange used to impregnate a metal into the exposed portion of the dielectric layer.
For claim 11, Ham, Lee, and Kanou are silent regarding forming and patterning a first and second resist material on the one or more polymer ILD layers, and also applying a metal solution soak. Ham, Lee, and Kanou to teach a heat treatment and applying radiation from a light source to the exposed portions of the ILD layers.
For claim 13, Ham, Lee, and Kanou are silent regarding an ion exchange used to impregnate a metal into the exposed portion of the dielectric layer.
For claim 15, Ham, Lee, and Kanou are silent regarding the graphene wiring line and the graphene via structure each comprising a laser-induced graphene foam structure.
For claim 18, Ham, Lee, and Kanou are silent regarding the graphene via structure and the graphene wiring layer comprising a mixture of nickel and polyimide which is formed through ion exchange reactions between the nickel and the polyimide.
Conclusion
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815