Prosecution Insights
Last updated: July 17, 2026
Application No. 18/369,757

SEMICONDUCTOR WAFER FABRICATION WITH EXPOSURE DEFINED GRAPHENE FEATURES

Final Rejection §103
Filed
Sep 18, 2023
Examiner
NELSON, JACOB THEODORE
Art Unit
2815
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
NXP Semiconductors N.V.
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allowance Rate
121 granted / 138 resolved
+19.7% vs TC avg
Moderate +8% lift
Without
With
+7.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
22 currently pending
Career history
168
Total Applications
across all art units

Statute-Specific Performance

§101
0.7%
-39.3% vs TC avg
§103
83.9%
+43.9% vs TC avg
§102
5.8%
-34.2% vs TC avg
§112
7.7%
-32.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 138 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s amendment to the drawings is acknowledged. The objection to the drawings is withdrawn. Applicant’s amendment to claim 4 is acknowledged. The objection to claim 4 is withdrawn. The cancellation of claims 19 and 20 are acknowledged. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 4, and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10134630 B2 hereinafter Ham in further view of US 20160349905 A1 hereinafter Momma. For claim 1, Ham teaches a method of making an integrated circuit, comprising: providing an integrated circuit structure (Ham, Col. 8 ln 46 – 50) comprising one or more polymer interlayer dielectric (ILD) layers (fig. 3 numeral 10a; Col. 5 ln 7 – 17; Col. 8 ln 61 – Col. 9 ln 5; Col. 9 ln 43 – Col. 10 ln 11) formed over a first conductive wiring line layer (fig. 3 numeral 30); and selectively processing an exposed portion of the one or more polymer ILD layers by applying irradiation from a laser or light source to form a graphene interconnect structure in the one or more polymer ILD layers which is directly, electrically connected to the first conductive wiring line layer (fig. 3 S306 – S316 shows the process of exposing carbon source 30 and catalyst layer 20a, a conductive metal layer, through etching the ILD layers 10a, and then applying a radiation treatment at step S316; Col. 3 ln 20 – 23; Col. 7 ln 8 – 12). Ham does not explicitly state that the irradiation from a laser or light source is applied through an opening in a layer formed above the one or more polymer ILD layers to a defined first portion of the one or more polymer ILD layers. Ham does state that the irradiation may be applied directly to the graphene structures (Col. 7 ln 12 – 20) and that an opening is formed in a layer that is above the one or more polymer ILD layers (fig. 3 numeral 10b shows a layer over the polymer layer 10a that is etched to form an opening in step S310 with an irradiating step performed in step 316). Momma teaches a method of forming graphene structures (Momma, fig. 1) including forming a graphene containing material (fig. 2B numeral 11 and 12) onto a lower layer (fig. 2B numeral 101), forming a mask layer above the lower layer (fig. 2B numeral 908) and using openings through the layer formed above the lower layer, applying irradiation from a laser or light source (fig. 2B numeral 905) to form a graphene structure (Par. [0117 – 0118]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the mask layer and irradiation through the openings of the mask layer in Momma with the graphene interconnect structures and polymer interlayer dielectric layer in Ham in order to selectively irradiate the graphene layers and not the other layers present in the device (Momma, Par. [0117]) and because Ham teaches applying the irradiation directly to the graphene containing layers (Ham, Col. 7 ln 12 – 20) and providing openings in the above layers (Ham, fig. 3 numeral S310). For claim 4, Ham and Momma teach all of claim 1. Ham also teaches the one or more polymer ILD lay comprises one or more non-photosensitive, carbon-containing polymer layers (Ham, Col. 4 ln 64 – Col. 5 ln 6: Col. 5 ln 23 – 53) which respond to irradiation form a laser source (Col. 3 ln 20 – 23; Col. 7 ln 8 – 12) to form the graphene interconnect structure directly from the exposed portion of the one or more non photosensitive, carbon-containing polymer layers (fig. 3 numeral 40, 40a, and 40b; fig. 1 numeral 40; Col. 8 ln 61 – Col. 9 ln 5). The lasers and light sources used in Ham include ultraviolet light and figure 3 shows the carbon sources being directly treated by heat source, which include the laser and light sources. As such, Ham appears to teach a non-photosensitive, carbon-containing polymer layer that responds to irradiation from a laser source to form the graphene interconnect structure. Further, Ham teaches the carbon source being a fluorinated polyimide film (Col. 2 ln 55 – Col. 3 ln 9) along with other materials similar to or matching the materials used in the immediate invention as described in the specification as non-photosensitive carbon-containing polymer dielectric material (immediate invention Par. [025]). As Ham teaches the same materials used in the interlayer dielectric layers as the immediate invention, Ham appears to teach a non-photosensitive, carbon-containing polymer layer. For claim 7, Ham and Momma teach all of claim 1. Ham also teaches the graphene interconnect structure comprises a graphene wiring line layer (Ham, fig. 3 numeral 40b) connected to the first conductive wiring layer (fig. 3 numeral 40) with a graphene via structure that is position to completely cover a maximized overlapping region between the graphene wiring line layer and first conductive wiring line layer (fig. 3 numeral 40a shows a graphene via connecting graphene wiring line layer 40b and the first conductive wiring line layer 40, and the via 40a fully overlaps both 40 and 40b, and therefore covers the overlapping region between the two structures). Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 10134630 B2 hereinafter Ham in view of US 20160349905 A1 hereinafter Momma and in further view of US 20240413075 A1 hereinafter Lee. For claim 2, Ham and Momma teach all of claim 1. Ham and Momma are silent regarding the semiconductor substrate including a plurality of integrated circuit elements formed on the substrate and covered by the initial ILD layer and the one or more polymer ILD layers. Ham does teach the first substrate including an integrated circuit element (Ham, fig. 3 numeral 40) and that the process can be repeated (fig. 3 shows continued layers above the last ILD layer 10b). Ham also teaches the interconnect structures being used in integrated circuits and other semiconductor devices (Col. 1 ln 46 – 51). Lee teaches an integrated circuit device (Lee, fig. 1) with multiple integrated circuit elements (fig. 1 numeral 112) on a substrate (fig. 1 numeral 21) and covered by multiple interlayer dielectric layers (fig. 1 numeral 111, 131). It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the multiple integrated circuit elements in Lee with the graphene interconnect structures in Ham and Momma in order to create devices capable of multiple functions such as sensors, memory, transistors, etc. (Lee, Par. [0014]) while improving the devices electrical conductivity and the interconnect structure’s stability (Ham, Col. 3 ln 51 – 60). Allowable Subject Matter Claims 3, 5 - 6, 8 - 14, and 16 - 18 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 3’s “…where the one or more polymer ILD lay comprises one or more ultra low-k photosensitive polymer layers which respond to irradiation from a light source with a chemical reaction which may be used for an ion exchange to impregnate a suitable metal into the exposed portion of the one or more polymer ILD layers…”, claim 5’s “…patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask with a via opening… patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask with a metal line opening…”, claim 6’s “…where selectively processing the exposed portion of the one or more polymer ILD layers comprises: patterning a first resist material on one of the one or more polymer ILD layers to form a first resist mask with a via opening; selectively applying irradiation from a laser source to a defined first portion of the one or more polymer ILD layers using the via opening of the first resist mask to directly form a graphene via structure which is directly, electrically connected to the first conductive wiring line layer; patterning a second resist material on one of the one or more polymer ILD layers to form a second resist mask with a metal line opening; and selectively applying irradiation from a laser source to a defined second portion of the one or more polymer ILD layers using the metal line opening of the second resist mask to directly form a graphene wiring line…”; claim 8’s “…where the graphene wiring line and graphene via structure each comprise a laser-induced graphene foam structure”, claim 10’s “…where forming one or more polyimide dielectric layers comprises depositing and planarizing an ultra-low-k photosensitive polymer dielectric layer which responds to irradiation from a light source with a chemical reaction which may be used for an ion exchange to impregnate a suitable metal into the exposed portion of ultra-low-k photosensitive polymer dielectric layer”, claim 13’s “…where selectively applying irradiation comprises: patterning a first resist material over the non-photosensitive, carbon- containing polymer dielectric layer to form a first resist mask with a via opening; selectively applying irradiation from a laser source to a defined first portion of the non-photosensitive, carbon-containing polymer dielectric layer using the via opening of the first resist mask to directly form a graphene via structure which is directly, electrically connected to the first conductive layer; patterning a second resist material over the non-photosensitive, carbon- containing polymer dielectric layer to form a second resist mask with a wiring line opening; and selectively applying irradiation from the laser source to a defined second portion of the non-photosensitive, carbon-containing polymer dielectric layer using the wiring line opening of the second resist mask…”, and claim 18’s “…where the graphene wiring line and graphene via structure each comprise a heat- treated mixture of nickel and polyimide which is formed from a light-induced ion exchange reaction of nickel and polyimide”. Claims 9, 11 – 12, 14, and 16 – 17 are allowable primarily as depending on an allowable base claim. Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance” Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. For claim 15, Ham, Momma, and Lee are silent regarding the graphene wiring line and the graphene via structure each comprising a laser-induced graphene foam structure. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB T NELSON whose telephone number is (571)272-1031. The examiner can normally be reached Monday through Friday 9:00 AM to 5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Joshua Benitez can be reached at 571-270-1435. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /J.T.N./Examiner, Art Unit 2815 /MONICA D HARRISON/Primary Examiner, Art Unit 2815
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Prosecution Timeline

Sep 18, 2023
Application Filed
Feb 24, 2026
Non-Final Rejection mailed — §103
May 18, 2026
Response Filed
Jun 17, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
96%
With Interview (+7.9%)
2y 10m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 138 resolved cases by this examiner. Grant probability derived from career allowance rate.

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