Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. The specification filed on 9/19/23 is objected because it fails to indicates the reissue application serial number [18/369,963] and fails to include the following application data information: Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Liaw (US 20130154027) in view of Ohtsuki et al. (US 7,248,5230) Regarding claim s 21 and 22 , Liaw (e.g. fig. 1 and 2) teaches a device comprising: a plurality of bit cells including a first bit cell, a second bit cell, a third bit cell and a fourth bit cell, arranged in a 2x2 matrix (see fig. 2); in which the first bit cell and the third bit cell are directly adjacent to the second bit cell and the fourth bit cell [i.e. fig. 2 depicts bit cells positioned directly adjacent to one another in both row and column directions] ; the first bit cell and the second bit cell overlap in a first direction and the third bit cell and the fourth bit cell overlap in the first direction ; a first source/drain pattern provided over an intersection of the first bit cell and the second bit cell [Liaw implicitly discloses shared diffusion regions (source/drain) between adjacent SRAM bit cells. These diffusion regions extend across the boundaries of neighboring cells, thereby forming source/drain patterns at the intersection of adjacent cells] ; and a second source/drain pattern provided over an intersection of the third bit cell and the fourth bit cell [Liaw implicitly discloses shared diffusion regions (source/drain) between adjacent SRAM bit cells. These diffusion regions extend across the boundaries of neighboring cells, thereby forming source/drain patterns at the intersection of adjacent cells] ; wherein each of the plurality of bit cells (e.g. fig 1) comprises a first access transistor and a second access transistor [PG1/2] , a first pull-up transistor and a second pull-up transistor [PU1/2] , and a first pull-down transistor and a second pull-down transistor [PD 1/2] ,wherein the first bit cell and the second bit cell have structural contours that are joined together in a coupling arrangement [i.e. the diffusion regions are continuous across adjacent cells, the structural contours of the bit cells are physically joined together at these shared regions] , and wherein the first bit cell and the second bit cell have multiple transistors arranged to store data [fig. 1 is a conventional SRAM cell comprising multiple transistors {8} , including access transistors and cross-coupled inverters transistors which inherently store data] . Liaw implicitly discloses shared diffusion regions (source/drain) between adjacent SRAM bit cells. These diffusion regions extend across the boundaries of neighboring cells, thereby forming source/drain patterns at the intersection of adjacent cells. Although implicitly disclosed it is not explicitly disclosed. Nevertheless, Ohtsuki textually discloses that transistors are arranged such that they share a diffusion layer (col. 4/ll. 8-28). It would have been obvious to one of ordinary skill in the art at the time of the invention to implement SRAM bit cells with shared diffusion regions between adjacent cells as suggested by Ohtsuki , in order to reduce layout area, improve pack aging density, and enhance circuit performance. Such shared diffusion layouts inherently result in overlapping structural regions between adjacent cells. It is respectfully noted that combining prior art elements according to known methods will yield predictable results. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007) [MPEP 2143] Allowable Subject Matter Original claims 1-20 are allowed. The following is a statement of reasons for the indication of allowable subject matter: Regarding independent claim 1, the prior art made of record does not teach the claimed limitation of: “a first via under the first conductive pattern, the first via electrically connecting the first conductive pattern to first and second source/drain patterns of the source/drain patterns; and a second via under the second conductive pattern, the second via electrically connecting the second conductive pattern to a first gate electrode of the gate electrodes, wherein a width of the first via is different from a width of the second via” . Regarding independent claim 8, the prior art made of record does not teach the claimed limitation of: “a first via interposed between and electrically connecting the fifth line and the first conductive pattern; and a second via interposed between and electrically connecting the third line and the second conductive pattern, wherein a width in the second direction of the first via is greater than a width in the second direction of the second via” . Regarding independent claim 13, the prior art made of record does not teach the claimed limitation of: “a first via interposed between and electrically connecting the fifth line and the first conductive pattern; and a second via under the first conductive pattern, the second via electrically connecting the first conductive pattern to first and second source/drain patterns of the source/drain patterns, wherein a width of the first via is different from a width of the second via”. Dependent claims 2-7, 9-12 and 14-20 are allowed for being dependent on one of the allowable independent claims discussed above. They include all of the limitations of the allowable independent claim on which they depend on. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT LEONARDO ANDUJAR whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)272-1912 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday to Thursday 10 AM to 8 PM . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Patricia L Engle can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571)272-6660 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT /Leonardo Andujar/ Primary Examiner Art Unit 3991 CRU Conferees: /LEE E SANDERSON/ Reexamination Specialist, Art Unit 3991 /Patricia L Engle/ SPRS, Art Unit 3991