Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-13, 17, 18, and 20-24 are rejected under 35 U.S.C. 101 because the claimed invention is directed to a judicial exception (i.e., a law of nature, a natural phenomenon, or an abstract idea) without significantly more.
Specifically, representative Claim 1 recites:
“A device comprising: a memory storing instructions for performing a method of sorting semiconductor chips with potential failure risk from a wafer of which inspection is completed; and a processor configured to execute the instructions to cause the processor to at least: acquire a test result map including test result values for each semiconductor chip of a plurality of semiconductor chips included in the wafer from an inspection result of the wafer, generate a distance map including a distance value between a target semiconductor chip determined as an inspection pass among the plurality of semiconductor chips and one or more peripheral semiconductor chips of the target semiconductor chip in at least one coordinate system, calculate a potential failure risk value of the target semiconductor chip based on the test result map and the distance map, and determine whether the target semiconductor chip has the potential failure risk based on the potential failure risk value.”
The claim limitations in the abstract idea have been highlighted in bold above; the remaining limitations are “additional elements”.
Under the Step 1 of the eligibility analysis, we determine whether the claims are to a statutory category by considering whether the claimed subject matter falls within the four statutory categories of patentable subject matter identified by 35 U.S.C. 101: Process, machine, manufacture, or composition of matter. The above claim is considered to be in a statutory category (process).
Under the Step 2A, Prong One, we consider whether the claim recites a judicial exception (abstract idea). In the above claim, the highlighted portion constitutes an abstract idea because, under a broadest reasonable interpretation, it recites limitations that fall into/recite an abstract idea exceptions. Specifically, under the 2019 Revised Patent Subject matter Eligibility Guidance, it falls into the groupings of subject matter that covers mathematical concepts - mathematical relationships, mathematical formulas or equations, mathematical calculations and mental processes – concepts performed in the human mind including an observation, evaluation, judgement, and/or opinion.
For example, steps of “generate a distance map including a distance value between a target semiconductor chip determined as an inspection pass among the plurality of semiconductor chips and one or more peripheral semiconductor chips of the target semiconductor chip in at least one coordinate system, calculate a potential failure risk value of the target semiconductor chip based on the test result map and the distance map” are treated as belonging to the mathematical concepts grouping while the steps of “method of sorting semiconductor chips with potential failure risk from a wafer of which inspection is completed” and “determine whether the target semiconductor chip has the potential failure risk based on the potential failure risk value” are treated as belonging to mental process grouping. This mental step represents a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind. In the context of this claim, it encompasses a user sorting the chips (“evaluation) and eventually making a “judgement” regarding a potential failure risk based on the calculated a potential risk value and appropriate/known criteria. These steps, under the BRI, alternatively/additionally are treated as mathematical relationship steps (MPEP 2106.04.II: “construing the claims in accordance with their broadest reasonable interpretation”) when the processor sorting using patterns [0168, 0175, 0205] and determines a potential failure risk as discussed in [0255-0256], as published.
Similar limitations comprise the abstract ideas of Claims 13 and 24.
Next, under the Step 2A, Prong Two, we consider whether the above claims that recites a judicial exception are integrated into a practical application.
The above claims comprise the following additional elements:
In Claim 1: A device comprising: a memory storing instructions for performing a method of sorting semiconductor chips with potential failure risk from a wafer of which inspection is completed; and a processor configured to execute the instructions to cause the processor to at least: acquire a test result map including test result values for each semiconductor chip of a plurality of semiconductor chips included in the wafer from an inspection result of the wafer;
In Claim 13: A method comprising: inspecting a wafer including a plurality of semiconductor chips by performing a test according to each of a plurality of test items;
In Claim 24: A method comprising: inspecting a wafer including a plurality of semiconductor chips by performing a test according to each of a plurality of test items.
The additional elements in the preambles are recited in generality and represent insignificant extra-solution activity (field-of-use limitations) that is not meaningful to indicate a practical application.
The additional elements in the claims such as a memory and a processor (Claim 1) are examples of generic computer equipment (components) that are generally recited and not meaningful and, therefore, are not qualified as particular machines to indicate a practical application. The limitations that generically recite acquire a test result map including test result values for each semiconductor chip of a plurality of semiconductor chips included in the wafer from an inspection result of the wafer (Claim 1), performing a test according to each of a plurality of test items (Claim 13), and inspecting a wafer including a plurality of semiconductor chips by performing a test according to each of a plurality of test items (Claim 24) represent insignificant extra-solution activity of mere data gathering. According to the October update on 2019 SME Guidance such steps are “performed in order to gather data for the mental analysis step, and is a necessary precursor for all uses of the recited exception. It is thus extra-solution activity, and does not integrate the judicial exception into a practical application”.
Therefore, the claims are directed to a judicial exception and require further analysis under the Step 2B.
However, the above claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception (Step 2B analysis) because these additional elements/steps are well-understood and conventional in the relevant art based on the prior art of record.
The independent claims, therefore, are not patent eligible.
With regards to the dependent claims, claims 2-12, 17, 18, and 20-24 provide additional features/steps which are part of an expanded abstract idea of the independent claims (additionally comprising abstract idea steps) and, therefore, these claims are not eligible without meaningful additional elements that reflect a practical application and/or additional elements that qualify for significantly more for substantially similar reasons as discussed with regards to Claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 13, and 24 are rejected under 35 U.S.C. 103 as being unpatentable over He-jie Cui et al. (CN 201410191097), hereinafter ‘Cui’ in view of Russell B. Miller et al., “Unit Level Predicted Yield: a Method of Identifying High Defect Density Die at Wafer Sort”, ITC International Test Conference, 2001, pp. 2118-2127, submitted in the IDS dated 9/19/23, hereinafter ‘Miller’.
With regards to Claim 1, Cui discloses
A device comprising: a memory storing instructions for performing a method of sorting semiconductor chips with potential failure risk from a wafer of which inspection is completed; and a processor configured to execute the instructions (a chip screening device, comprising: a memory for storing instructions; a processor for executing instructions stored in the memory, p.3) to cause the processor to at least: acquire a test result map including test result values for each semiconductor chip of a plurality of semiconductor chips included in the wafer from an inspection result of the wafer (The embodiment of the invention claims a chip screening method, which is a statistical method for statistical and probability data, is WaferMap (wafer map) data obtained by reflecting the condition of good product chip according to the wafer test (WaferCP test), the peripheral area of the chip good product chip (PassDie) for counting, in the obtained wafer test to evaluate the good product chip there is a possibility of potential failure, p.4; prior to calculating the first influence factor of the chip, it should firstly judging whether the chip is effective chip, mainly is judging whether the chip position is effective in this step, for example, the position of the chip is empty, whether the position overlapped with the chip D1 to be judged the position and current position whether there is a normal test result and so on, p.5; FIG. 4 is a test result graph of chip screening method embodiment of the present invention, p.6), generate a distance value between a target semiconductor chip determined as an inspection pass among the plurality of semiconductor chips and one or more peripheral semiconductor chips of the target semiconductor chip in at least one coordinate system (the distance-related quantity can be the distance between each chip and the chip to be determined, p.4), calculate a potential failure risk value of the target semiconductor chip based on the test result map (WaferMap, above) and the distance value structure (wafer structure in Fig.2, X1, X2, and D1; if the present chip such as X1 is judged as the good product chip, bad product chip in the wafer test, shows test result of the current position is normal, and the test result is not empty, and the current chip and the D1 position is not overlapped, then determining the current chip is effective chip, then it can calculate the first contribution factor of the current chip, and the subsequent calculating first influence factor is introduced to the influence factors and calculation, p.5), and determine whether the target semiconductor chip has the potential failure risk based on the potential failure risk value (calculating the NDCF at 103, will be judged to be judged whether the chip is chip of large potential failure rate according to the NDCF and the preset screening condition. Optionally, the screening conditions can be set as the NDCF chip to be judged is greater than or equal to a preset threshold value. For example, it is assumed a predetermined selection condition is NDCF> 30%, and the chip X1 in FIG. 2 NDCF 50%, X2 NDCF is 23%, then determining that X1 is a potential failure rate of the chip, there is probability of early failure larger; and X2 early failure probability is small, the X1 can be screened out, thereby improving EFR, p.6).
However, Cui does not specifically disclose generating a distance value map and, correspondingly, calculating a potential failure risk value of the target semiconductor chip based on the test result map and the distance value map.
Miller discloses generating a distance value map (Since ULPY is just a number ranging from 0 to 1, and since it varies for every die on a wafer, it can be mapped and interpreted graphically. The next set of graphs traces good and bad die on a particular wafer through the generation of ULPY values, p.1123).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cui in view of Miller to calculate a potential failure risk values using the test result map and the distance value map ( ULPY is a number bounded by 0 and 1, and can be interpreted as the approximate probability that a particular die will yield at sort given the yield results of other die in the lot, Miller, p.1118).
With regards to Claim 2, Miller additionally discloses the processor acquires any one map, as the test result map, among: a first bit map including single-bit values indicating a test pass or a test failure of each semiconductor chip included in the wafer (each die in the lot is assigned a score. A value of 1 is assigned to non-defective die, while a value of 0 is assigned to defective die, Abstract) and a defective count map including integer values indicating a number of failed components included in each semiconductor chip included in the wafer (Graphs 5-7; finding the fraction of die that failed sort, p.1124; Calculate the cumulative number of total die, and the cumulative number of good die, at each point, p.1123).
With regards to Claims 13 and 24, Cui in view of Miller disclose the claim limitations as discussed above in Claim 1 and 2.
With regards to Claim 13, Miller discloses a binary scenarios of a bit map (Section 6.2).
Claims 4, 8, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Cui in view of Miller, in further view of Il Suk Park et al. (US 20170076435), hereinafter ‘Park’.
With regards to Claim 4, Cui discloses calculating the distance value for each of the one or more peripheral semiconductor chips (calculating the first influence factor of each chip peripheral area judging chip in, optionally, the first influence factor may be, for example, the product of one distance-related quantity and the influence parameter and distance-related quantity is one chip to be distance between the correlation values and determining chip value related to, for instance, the distance-related quantity can be the distance between each chip and the chip to be determined, or according to the distance, and the influence parameter for correcting the distance-related quantity. such as in the peripheral range of the set, chips with different position of the influencing parameters are different, p.4)..
Cui is silent on wherein the processor further executes the instructions to cause the processor to calculate the distance value for each of the one or more peripheral semiconductor chips based on first coordinate values and second coordinate values indicating positions of the plurality of semiconductor chips in at least one two-dimensional coordinate system among a Cartesian coordinate system, a polar coordinate system, and a photo shot coordinate system indicating a position of a photo shot in a photomask.
Park discloses first coordinate values and second coordinate values indicating positions of the plurality of semiconductor chips in at least one two-dimensional coordinate system among a Cartesian coordinate system (the inspection position and the conversion position may be expressed in a Cartesian coordinate system and the imaging error may include x and y components [0104]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cui in view of Miller, and Park to calculate the distance value for each of the one or more peripheral semiconductor chips based on first coordinate values and second coordinate values indicating positions of the plurality of semiconductor chips in at least one two-dimensional coordinate system among a Cartesian coordinate system, as known in the art (Park).
With regards to Claim 8, Cui is silent on generat(ing) a two-dimensional distance map according to any one of a Cartesian coordinate system, a polar coordinate system, and a photo shot coordinate system indicating a position of a photo shot in a photomask, and calculate a weighted average value corresponding to the potential failure risk value based on distance values of the two-dimensional distance map and test result values of the test result map.
Park discloses generat(ing) a two-dimensional distance map according to any one of a Cartesian coordinate system (the inspection position and the conversion position may be expressed in a Cartesian coordinate system and the imaging error may include x and y components [0104]).
Miller discloses calculating a weighted average value corresponding to the potential failure risk value (All die were weighted equally when attempting to predict whether a particular die would yield, p.1119; Graph 3; A weighted arithmetic mean was used to calculate local yield, p.1122).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cui in view of Miller, and Park to calculate a potential failure risk values using the test result map and the two-dimensional distance value map using corresponding data based on distance values of the two-dimensional distance map and test result values of the test result map and similarly to Claim 1.
With regards to Claim 12, Cui in view of Miller discloses the invention as discussed in Claim 1.
However, Cui is silent on generating two-dimensional distance maps according to each of at least two two-dimensional coordinate systems among a Cartesian coordinate system, a polar coordinate system, and a photo shot coordinate system indicating a position of a photo shot in a photomask, calculate a weighted average value for each of the two-dimensional distance maps based on distance values of each of the two-dimensional distance maps and test result values of the test result map, and extract a greatest value of the weighted average values as the potential failure risk value.
Cui in view of Miller, and Park discloses generating two-dimensional distance maps according to each of at least two two-dimensional coordinate systems among a Cartesian coordinate system, a polar coordinate system, and a photo shot coordinate system indicating a position of a photo shot in a photomask, calculate a weighted average value for each of the two-dimensional distance maps based on distance values of each of the two-dimensional distance maps and test result values of the test result map as discussed in Claim 8.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Cui in view of Miller, and Park to extract the greatest value of the weighted average values as the potential failure risk value because the greatest value would represent the worst case risk scenario.
Examiner Note with Regards to Prior Art of Record
Claims 5, 6, 7, 9-11, 17, 18, and 20-23 are distinguished over prior art of record based on the reasons below.
In regards to Claim 5, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious calculating a first correction coordinate value based on a ratio of a first coordinate value to a first integer value indicating a greatest number of semiconductor chips arranged in the wafer in a first direction, calculate a second correction coordinate value based on a ratio of a second coordinate value to a second integer value indicating a greatest number of semiconductor chips arranged in the wafer in a second direction perpendicular to the first direction, and calculate the distance value based on the first correction coordinate value and the second correction coordinate value, in combination with all other limitations in the claim as claimed and defined by applicant.
In regards to Claim 6, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious calculating a first correction difference value based on a first difference value between a first coordinate value of the target semiconductor chip and a first coordinate value of the peripheral semiconductor chip and based on a correction coefficient in the polar coordinate system, calculate a second correction difference value based on a second difference value between a second coordinate value of the target semiconductor chip and a second coordinate value of the peripheral semiconductor chip and based on the correction coefficient in the polar coordinate system, and calculate the distance value based on the first correction difference value and the second correction difference value., in combination with all other limitations in the claim as claimed and defined by applicant.
In regards to Claim 7, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious calculating a first correction distance value based on a first distance value between a position of a first photomask corresponding to the target semiconductor chip and a position of a second photomask corresponding to the peripheral semiconductor chip and based on a correction coefficient in the photo shot coordinate system, calculate a second correction distance value based on a second distance value between a photo shot position of the target semiconductor chip in the first photomask and a photo shot position of the peripheral semiconductor chip in the second photomask and based on the correction coefficient in the photo shot coordinate system, and calculate the distance value based on the first correction distance value and the second correction distance value, in combination with all other limitations in the claim as claimed and defined by applicant.
In regards to Claim 9, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious the weighted average value is calculated by Equation 1, in combination with all other limitations in the claim as claimed and defined by applicant.
In regards to Claim 17, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious calculating the potential failure risk value comprises calculating a weighted average value corresponding to the potential failure risk value according to Equation 4, in combination with all other limitations in the claim as claimed and defined by applicant.
In regards to Claim 20, the claim the claim differs from the closest prior art, Cui, Miller, and Park, either singularly or in combination, because the references fail to anticipate or render obvious generating a second distance map according to a polar coordinate system; generating a third distance map according to a photo shot coordinate system indicating a position of a photo shot in a photomask, and wherein calculating the potential failure risk value comprises: calculating a first weighted average value based on distance values of the first distance map and bit values of the bit map; calculating a second weighted average value based on distance values of the second distance map and the bit values; calculating a third weighted average value based on distance values of the third distance map and the bit values; and extracting a greatest value among the first weighted average value, the second weighted average value, and the third weighted average value as the potential failure risk value, in combination with all other limitations in the claim as claimed and defined by applicant.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jaehoon Koo et al., “A Unified Defect Pattern Analysis of Wafer Maps Using Density-Based Clustering”, IEEE Access, 2021, Vol.9,pp. 78873-78882, Digital Object Identifier 10.1109/ACCESS.2021.3084221, discloses a defect pattern analysis method that conducts a statistical test to detect abnormal defects on a wafer map and clustering the defect patterns.
Joong-Wuk Kang et al. (US 7514949) discloses calculating a defect index value of a defective wafer based on a spatially related group of filtered failed semiconductor chips on the wafer using a wafer map, where the spatially related group corresponds to a localized failure on the wafer.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER SATANOVSKY whose telephone number is (571)270-5819. The examiner can normally be reached on M-F: 9 am-5 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Catherine Rastovski can be reached on (571) 270-0349. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALEXANDER SATANOVSKY/
Primary Examiner, Art Unit 2857
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