Prosecution Insights
Last updated: April 19, 2026
Application No. 18/370,346

PARALLELIZED RECOVERY OF LOGICAL BLOCK ADDRESS (LBA) TABLES

Final Rejection §103
Filed
Sep 19, 2023
Examiner
GOLDSCHMIDT, CRAIG S
Art Unit
2132
Tech Center
2100 — Computer Architecture & Software
Assignee
VMware, Inc.
OA Round
2 (Final)
73%
Grant Probability
Favorable
3-4
OA Rounds
2y 10m
To Grant
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
293 granted / 401 resolved
+18.1% vs TC avg
Strong +32% interview lift
Without
With
+32.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
21 currently pending
Career history
422
Total Applications
across all art units

Statute-Specific Performance

§101
6.9%
-33.1% vs TC avg
§103
46.4%
+6.4% vs TC avg
§102
9.4%
-30.6% vs TC avg
§112
29.4%
-10.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 401 resolved cases

Office Action

§103
DETAILED ACTION Re Application No. 18/370346, this action responds to the amended claims dated 10/29/2025. At this point, claims 1-3, 8-9, and 15 have been amended. Claims 1-20 are presented for examination. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 1-4, 8-10, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuji (US 2018/0067680 A1) in view of Wang et al (US 2021/0382825 A1). Re claim 1, Ohtsuji discloses the following: A method for data storage (¶ 67). The method controls data storage; the method comprising: receiving, at a […] component […] a first input/output operation indicating a first logical block address (LBA) (Fig. 1, step S11; ¶ 83-84). The server receives a read/write (input/output) operation indicating an LBA; of a single address space, wherein the single address space corresponds to a plurality of first storage devices (Figs. 2 and 4; ¶ 76-77). In the example given, the single address space spans from LBA0000 to LBAzzzz, managed by servers 100a-100c (Fig. 4; ¶ 76-77), wherein each server 100a-100c manages a corresponding storage 200a-200c as part of respective nodes N0-N2 (Fig. 2); determining, by the […] component, that a first LBA table of a plurality of LBA tables is associated with the first LBA (¶ 90). The server specifies which server is in charge of mapping the specified LBA, wherein the LBA management table of that server is used; wherein each of the plurality of LBA tables is associated with a different corresponding portion of the single address space (¶ Figs. 2 and 4). Each respective LBA table is associated with a portion of the single address space – LBA management table 122a spans LBA0000->xxxx, 122b spans LBAxxxx+1->yyyy, and 122c spans LBAyyyy+1->zzzz; storing, by the […] component data corresponding to the first I/O operation at a first physical address of a first storage device of a second plurality of storage devices; and (¶ 88). The data is stored in the created cache page, and associates the entry with a page number (first physical address) of the created cache page. It is noted that Applicant’s specification discloses that the “second plurality of storage devices” may be a plurality of cache-tier disks of the local storage (¶ 34); adding, by the […] component, a first entry into the first LBA table, the first entry mapping the first LBA to the first physical address (Fig. 6; ¶ 81 and 91). Server 100c registers an entry’s address in the pointer field of the entry in which the received LBA is registered (adding a first entry) to LBA management table 122c (first LBA table), to associated the block indicated by the LBA to the physical storage area (¶ 91). The LBA management table entries include a page number of the cache storing the data, if the data has been registered in the cache (Fig. 6; ¶ 81). Ohtsuji discloses the above functionality, but does not explicitly claim that it is performed by a VSAN. Wang discloses the following: receiving, at a virtual storage area network (VSAN) component of a hypervisor running on a physical host in a cluster of hosts managed by a virtualization management platform, a first input/output (I/O) operation (Fig. 2; ¶ 64-69). The vSAN is implemented by virtualization layers spread across a plurality of storage node, which may be implemented as hosts, and a given virtualization layer contains a hypervisor running on the storage node (physical host); [performing I/O management tasks] by the VSAN component (¶ 39). The vSAN receives I/O requests from a vSAN client, and manages I/O. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the I/O management of Ohtsuji to be performed by a VSAN, as in Wang, because it would be applying a known technique to a known method ready for improvement, to yield predictable results. Ohtsuji discloses a method of I/O management, which is ready for the improvement of virtualization. Wang discloses a VSAN which manages I/O, which is applicable to the I/O management of Ohtsuji. It would have been obvious to modify the component handling the I/O management in Ohtsuji to utilize a VSAN, as in Wang, because it would yield the predictable result of allowing the VSAN to be flexibly implemented in software running on standard computing hardware, rather than requiring specialized SAN hardware. Re claim 2, Ohtsuji and Wang disclose the method of claim 1, and Ohtsuji further discloses that each of the plurality of LBA tables is associated with a different storage device of the first plurality of storage devices and one or more bits of the first LBA identify one of the first plurality of storage devices (Figs. 2 and 4; ¶ 77-78). Each server has an LBA table associated with the storage disk on the same respective node. Each LBA management table contains a respective range of addresses – 112a is associated with 0000 to xxxx, 112b is associated with xxxx+1->yyyy, and 112c is associated with yyyy+1->zzzz. Accordingly, the 4 bits in the LBA indicate which of these ranges the LBA belongs to, and accordingly, which node (and associated disk) it is associated with. Re claim 3, Ohtsuji and Wang disclose the method of claim 2, and Ohtsuji further discloses that the […] component receives the first I/O […], stores the data corresponding to the first I/O, and adds the first entry to the LBA table (¶ 81 and 88). The server (component) receives the I/O, and, if the data is not already in the storage, it creates a hash, stores it in an LBA entry (adds the first entry to the LBA table), and stores the data in memory. Wang further discloses that a local storage object manager (LSOM) of the VSAN component receives the first I/O from a distributed object manager (DOM) of the VSAN component (¶ 10 and 26-27). Wang discloses a vSAN which is organized into a hierarchy of local object manager/log structured object manager (LOM/LSOM) and distributed object managers (DOM). I/O requests are translated through the layers in the hierarchy, including being passed from a DOM to a LSOM layer, when the LSOM is at a lower layer than the DOM. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Ohtsuji and Wang, for the reasons note in claim 1 above. Re claim 4, Ohtsuji and Wang disclose the method of claim 1, and Ohtsuji further discloses that the first entry further maps the first LBA to a second physical address of a second storage device of the first plurality of storage devices (¶ 229-230). The data is later destaged from the cache (second plurality of storage devices) to one of the disks (a second storage device of the first plurality of storage devices), and the corresponding entry (first entry) is updated to map the LBA to a physical block address (second physical address) on the disk. Re claim 8, Ohsuji and Wang disclose the method of claim 1, and Wang further discloses that the VSAN component is a device driver within the hypervisor (¶ 65-66). The virtualization layer is implemented as a hypervisor, which implements its various functionality, including VSAN functionality, with various software components and/or drivers (device drivers). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Ohtsuji and Wang, for the reasons note in claim 1 above. Re claims 9-10, Ohtsuji and Wang disclose the methods of claims 1 and 4 above, respectively. Accordingly, they also discloses systems implementing those methods, as in claims 9-10, respectively (Ohtsuji, ¶ 2). Re claims 15-16, Ohtsuji and Wang disclose the methods of claims 1 and 4 above, respectively. Accordingly, they also discloses non-transitory storage media configured to control operation of those methods, as in claims 15-16, respectively (Ohtsuji, claim 14). Claims 5, 11, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuji in view of Wang, further in view of Lamberts et al (US 2004/0017629 A1). Re claim 5, Ohtsuji and Wang disclose the method of claim 1, and Ohtsuji further discloses that the LBA tables contain LBAs which are assigned to blocks (sets of LBAs) (¶ 76-77). Furthermore, while a block may be contiguous with the blocks immediately before and after it, it is obviously not contiguous with any blocks other than the blocks immediately before and after it (not contiguous with other sets). However, it does not explicitly disclose whether the blocks themselves are contiguous. Lamberts discloses that each of the plurality of LBA tables is associated with a corresponding plurality of sets of LBAs, each set of the corresponding plurality of sets of LBAs including a plurality of contiguous LBAs, and each set of the corresponding plurality of sets of LBAS not being contiguous with other sets of the corresponding plurality of sets of LBAs (¶ 32). Storage is divided up into zones and potentially sub-zones comprising addresses, tracks, sectors, etc. The zones and subzones may be organized into any possible grouping of contiguous or non-contiguous addresses, which includes a grouping in which individual zones/subzones (blocks) are contiguous, but not contiguous relative to other blocks. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the LBA tables of Ojtsuji (combined with Wang) to have each set of addresses be contiguous, as in Lamberts, because it would be obvious to try – making the sets of addresses contiguous would be choosing from a finite number of identified, predictable solutions (sets of addresses could all be contiguous, all be non-contiguous, or be a mix of contiguous and non-contiguous) with reasonable chance of success (logical addresses may be grouped together contiguously or non-contiguously). In fact, Lamberts suggests that the addresses may be grouped into any possible grouping of contiguous or non-contiguous addresses (¶ 32). Re claim 11, Ohtsuji, Wang, and Lamberts disclose the method of claim 5 above; accordingly, they also disclose a system implementing that method, as in claim 11 (Ohtsuji ¶ 2). Re claim 17, Ohtsuji, Wang, and Lamberts disclose the method of claim 5 above; accordingly, they also disclose a non-transitory storage medium configured to control operation of that method, as in claim 17 (Ohtsuji, claim 14). Claims 6-7, 12-14, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Ohtsuji in view of Wang, further in view of Gurajada et al (US 2018/0253468 A1). Re claim 6, Ohtsuji and Wang disclose the method of claim 1, but do not specifically disclose a log. Gurajada et al discloses storing a first log entry corresponding to the first I/O operation in a log stored in the second plurality of storage devices, the log storing a plurality of entries corresponding to a plurality of I/O operations (Figs. 3-4; transaction log 380). The transaction log is a log storing a plurality of entries related to store (I/O) operations. It is stored separately from storage devices 360 (first plurality of storage devices), so it is a second plurality of storage devices. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to modify the LBA mapping method of Ohtsuji (combined with Wang) to implement I/O logging, as in Gurajada, because Gurajada suggests that it would improve crash recovery performance by allowing a plurality of recovery threads to recover in parallel, without having all threads read an entire log multiple times (¶ 159). Re claim 7, Ohtsuji, Wang, and Gurajada disclose the method of claim 6, and Ohtsuji discloses metadata including a plurality of LBA tables, and a single address space (Fig. 4). Gurajada further discloses the following: recovering the plurality of […] tables, the recovering comprising: assigning the plurality of entries to a plurality of threads, each thread of the plurality of threads associated with a different […] table of the plurality of […] tables (¶ 159). The first recovery thread reads its log records (plurality of entries) and assigns them to N recovery threads, such that each recovery thread can recover entries in a corresponding tables and object partitions; adding, by each of the plurality of threads, an entry to the associated […] table of the thread for each entry of the plurality of entries corresponding to a[ block] associated with the corresponding portion of the […] address space associated with the […] table of the thread (¶ 76, 163, 168). Each recovery thread is provided with corresponding log records (entries) to be recovered to the respective tables (¶ 163, 168). Part of the recoverable data is a space map (address space) for the database (¶ 76). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Ohtsuji, Wang, and Gurajada, for the reasons noted in claim 6 above. Re claims 12-13, Ohtsuji, Wang, and Gurajada disclose the methods of claims 6-7 above, respectively. Accordingly, they also disclose systems implementing those methods, as in claims 12-13, respectively (Ohtsuji ¶ 2). Re claim 14, Ohtsuji, Wang, and Gurajada disclose the system of claim 13, and Gurajada further discloses that the log is stored in a plurality of sets of contiguous log blocks (¶ 76 and 142). The log can appear in contiguous sequences of pages (a plurality of sets of contiguous log blocks (¶ 142). Furthermore, a mapping table may map contiguous chunks of pages in a database’s space map (¶ 76). It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention (AIA ) to combine Ohtsuji, Wang, and Gurajada, for the reasons noted in claim 6 above. Re claims 18-19, Ohtsuji, Wang, and Gurajada disclose the methods of claims 6-7 above, respectively. Accordingly, they also disclose non-transitory storage media configured to control operation of those methods, as in claims 18-19, (Ohtsuji, claim 14). Re claim 20, Ohtsuji, Wang, and Gurajada disclose the system of claim 14; accordingly, they also disclose a non-transitory storage medium configured to implement similar functionality, as in claim 20 (Ohtsuji, claim 14). ACKNOWLEDGEMENT OF ISSUES RAISED BY THE APPLICANT Response to Amendment Applicant’s arguments with respect to claims 1-20 filed on 10/29/2025 have been fully considered, but are either not deemed persuasive, or are rendered moot in view of new grounds for rejection. As required by M.P.E.P. § 707.07(f), a response to these arguments appears below. ARGUMENTS CONCERNING PRIOR ART REJECTIONS Claims must be given the broadest reasonable interpretation during examination and limitations appearing in the specification but not recited in the claim are not read into the claim (See M.P.E.P. 2111 [R-1]). Re claims 1, 9, and 15, Applicant argues that Ohtsuji does not disclose a VSAN component of a hypervisor running on a physical host in a cluster of hosts managed by a virtualization management platform. In response, Applicant’s argument has been fully considered, but is moot in view of new grounds for rejection. Examiner has added the Wang reference, which discloses a VSAN running in a hypervisor/virtualization layer on a storage node (physical host) in a cluster of hosts (Fig. 2; ¶ 64-69). Re claims 3 and 8, Applicant argues that the claims are allowable as they “further define the VSAN component and its subcomponents”. Accordingly, Applicant is directed to Examiner’s rejections of claims 3 and 8 above. Re claims 2-8, 10-14, and 16-20, Applicant argues that the claims are allowable by virtue of their dependence on claims 1, 9, and 15, respectively. As this is the sole argument made for allowability, Applicant is directed to Examiner’s comments regarding claims 1, 9, and 15 above, respectively. All arguments by the Applicant are believed to be covered in the body of the office action; thus, this action constitutes a complete response to the issues raised in the remarks dated 10/29/2025. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Per the instant office action, claims 1-20 have received an action on the merits and are subject to a final rejection. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRAIG S GOLDSCHMIDT whose telephone number is (571)270-3489. The examiner can normally be reached M-F 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at 571-272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRAIG S GOLDSCHMIDT/Primary Examiner, Art Unit 2132
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Prosecution Timeline

Sep 19, 2023
Application Filed
Jul 26, 2025
Non-Final Rejection — §103
Oct 29, 2025
Response Filed
Nov 14, 2025
Final Rejection — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+32.1%)
2y 10m
Median Time to Grant
Moderate
PTA Risk
Based on 401 resolved cases by this examiner. Grant probability derived from career allow rate.

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