DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-8, 10, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by [Huang (Fig. 2); 6,696,894].
Regarding claim 1, Huang discloses an amplifier circuit comprising a first differential pair (MN1, MN2) connected to a first (the terminal receiving the input signal V+) and a second (the terminal receiving the input signal V-) input terminals, the first differential pair (MN1, MN2) comprising a pair of transistors that are mismatched, and a second differential pair (MP1, MP2) connected to the first (V+) and second (V-) input terminals in parallel with the first differential pair (MN1, MN2) and wherein the second differential pair (MP1, MP2) comprising a pair of transistors which are mismatched and wherein the first differential pair (MN1, MN2) is biased with a first current (the current source connecting to the node 22) and the second differential pair (MP1, MP2) is biased with a second current (the current source connecting to the node 20) and the first (the current source connecting to the node 22) and second (the current source connecting to the node 20) currents being unequal.
Regarding claim 2, wherein the mismatching of the pair of transistors (MN1, MN2, MP1, MP2) in each of the first (MN1, MN2) and second (MP1, MP2) differential pairs creates a pre-trim input offset voltage for the input stage circuit (MN1, MN2, MP1, MP2, V+, V-, the current source connecting to the node 22, the current source connecting to the node 20).
Regarding claim 3, wherein at least one (the current source connecting to the node 22) of the first (the current source connecting to the node 22) and second (the current source connecting to the node 20) currents is adjustable relative to the other.
Regarding claim 4, wherein at least one (the current source connecting to the node 22) of the first (the current source connecting to the node 22) and second (the current source connecting to the node 20) currents is adjustable relative to the other to reduce the pre-trim input offset voltage created by the input stage circuit (MN1, MN2, MP1, MP2, V+, V-, the current source connecting to the node 22, the current source connecting to the node 20).
Regarding claim 5, wherein at least one (the current source connecting to the node 22) of the first (the current source connecting to the node 22) and second (the current source connecting to the node 20) currents is adjustable relative to the other to create a composite input offset voltage which is combined with the pre-trim input offset voltage to create a final input offset voltage of zero.
Regarding claim 6, wherein mismatching of the pair of transistors (MN1, MN2, MP1, MP2) in each of the first (MN1, MN2) and second (MP1, MP2) differential pairs creates a pre-trim temperature coefficient of the input offset voltage (input offset voltage of V+ and V-).
Regarding claim 7, wherein at least one (the current source connecting to the node 22) of the first (the current source connecting to the node 22) and second (the current source connecting to the node 20) currents is adjustable relative to the other to reduce the pre-trim temperature coefficient of the input offset voltage (input offset voltage of V+ and V-) to zero.
Regarding claim 8, wherein the pair of transistors (MN1, MN2, MP1, MP2) in each of the first (MN1, MN2) and second (MP1, MP2) differential pairs is mismatched in value.
Regarding claim 10, wherein the pair of transistors (MN1, MN2, MP1, MP2) in each of the first (MN1, MN2) and second (MP1, MP2) differential pairs has a mismatch ratio of n:n+1.
Regarding claim 12, wherein each transistor (MN1 or MN2 or MP1 or MP2) in the first (MN1, MN2) and second (MP1, MP2) differential pairs is a metal oxide semiconductor field effect transistor.
Regarding claim 13, wherein each of the first (MN1, MN2) and second (MP1, MP2) differential pairs has an output (first pair: the signals going out of the transistors MN1 and MN2; 2nd pair: the signals going out of the transistors MP1 and MP2), and the outputs (the signals going out of the transistors MN1 and MN2 and the signals going out of the transistors MP1 and MP2) from the first (MN1, MN2) and second (MP1, MP2) differential pairs being combined (18) to form at least one output terminal (the terminal producing the output signal I out).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over [Huang (Fig. 2); 6,696,894].
Regarding claim 9, wherein the pair of transistors (MN1, MN2, MP1, MP2) in each of the first (MN1, MN2) and second (MP1, MP2) differential pairs is mismatched in value with respect to source area. As described above, Huang discloses all the limitations in claim 9 except for that the transistors being bipolar transistors. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have substituted well known art-recognized equivalent transistors such as bipolar transistors in place of the FETs in the circuit of the Huang because such a modification would have been considered a mere substitution of art-recognized equivalent transistors. Furthermore, it only requires routine skill in the art to replace the FETs with the bipolar transistors (it does not require the special skill to replace the FETs with the bipolar transistors).
Regarding claim 11, Huang discloses all the limitations in claim 11 except for that the transistors being bipolar transistors. It would have been obvious to one of ordinary skill in the art at the time the invention was made to have substituted well known art-recognized equivalent transistors such as the bipolar transistors in place of the FETs in the circuit of the Huang because such a modification would have been considered a mere substitution of art-recognized equivalent transistors. Furthermore, it only requires routine skill in the art to replace the FETs with the bipolar transistors (it does not require the special skill to replace the FETs with the bipolar transistors).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over [Huang (Fig. 2); 6,696,894] in view of [Motoroiu et al (Fig. 4); 2018/0323748].
Huang discloses all the limitations in claim 14 except for that the outputs from the first and second differential pairs are combined by an amplifier. Young discloses a differential amplifier circuit comprising the outputs (the signals going out of the drain terminals of the transistors M1a, M1b, M1c, and M1d) from the first (M1a, M1b) and second (M1c, M1d) differential pairs are combined by an amplifier (AR). It would have been obvious to one of ordinary skill in the art at the time the invention was made would have found it obvious to have employed the combined amplifier at the output terminal (the terminal generating the output signal I out) of the differential amplifier circuit of Huang (Fig. 2), such as taught by Young (Fig. 4) in order to provide the advantageous benefit of stabilizing the variation of the gain of the amplifier.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Henry Choe whose telephone number is (571)272-1760. The examiner can normally be reached Mon-Fri 6:00 AM- 6:00 PM EST. Examiner interviews are available via telephone, in person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interview practice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea J Lindgren Baltzell can be reached on (571)272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HENRY CHOE/ Primary Examiner, Art Unit 2843
#2940