DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. (US 20140077366 A1).
Regarding claim 1, FIG. 1E of Kim et al. teaches a semiconductor package (paragraph 0012) comprising:
a lower redistribution structure (32; FIG 1E; paragraph 0017);
an internal semiconductor chip (10; FIG 1E; paragraph 0017) on an upper surface of the lower redistribution structure;
an upper redistribution structure (34, 38, 20; FIG. 1E; paragraph 0022) electrically connected to the lower redistribution structure through a conductive post (28; FIG. 1E; paragraph 0021); and
a molding layer (30; FIG. 1E; paragraph 0022) between the upper redistribution structure and the lower redistribution structure, the molding layer surrounding the internal semiconductor chip,
wherein the upper redistribution structure comprises:
an insulating layer (38; FIG. 1E; paragraph 0046) comprising a redistribution pattern (34; FIG. 1E; paragraph 0022) and a first material (21; FIG. 1E; paragraph 0038) configured to transmit light (paragraph 0038); and
a fiducial mark formed of the first material (20, 21; FIG. 1E; paragraph 0038); and
wherein a lower surface (side surface of the 20 as lower surface; FIG. 1E; paragraph 0038) of the fiducial mark being in contact with an upper surface of the molding layer (30; FIG. 1E; paragraph 0015).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al..
Regarding claim 15, Kim et al. teaches the semiconductor package of claim 1. Kim et al. teaches a shape of the upper redistribution structure (34; FIG. 1E; paragraph 0022) is a rectangle. Kim et al. does not teach a horizontal width and a vertical width of a shape of the fiducial mark being less than 1/10 of a horizontal width or a vertical width of the upper redistribution structure.
However, the ordinary artisan would have recognized the vertical width or horizontal width of the fiducial mark and upper redistribution structure to be to be a result effective variable affecting the size of the semiconductor package (paragraph 0003). Thus, it would have been obvious to set the vertical width or horizontal width of the fiducial mark as within the claimed range, since optimum or workable ranges of such variables are discoverable through routine experimentation. see MPEP 2144.05 II.B.
Claims 6-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. in view of Hwang (US 20190206796 A1).
Regarding claim 6, Kim et al. teaches the semiconductor package of claim 1. Kim et al. does not teach the structure further comprising an upper semiconductor package on an upper surface of the upper redistribution structure.
FIG. 9 of Hwang teaches a semiconductor chip (120; FIG. 9; paragraph 0084) on top of the highest redistribution structure (142a; FIG. 9; paragraph 0084).
Kim et al. and Hwang are both analogous to the claimed invention in that they involve semiconductor devices with redistribution layers. Therefore, it would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to have modified Kim et al. to have the structure further comprising an upper semiconductor package on an upper surface of the upper redistribution structure. This allows for the semiconductor package to be electrically connected to the redistribution layers.
Regarding claim 7, Kim et al. teaches the semiconductor package of claim 1. Kim et al. does not teach two or more fiducial marks being provided.
FIG. 10A of Hwang teaches the number of each of first fiducial marks (115; FIG. 10A; paragraph 0072) and second fiducial marks (125; FIG. 10A; paragraph 0072) may be four, but is not limited thereto.
Kim et al. and Hwang are both analogous to the claimed invention in that they involve semiconductor devices with redistribution layers. Therefore, it would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to have two or more fiducial marks being provided. In this way, the pairs of fiducial marks may be positioned symmetrically (paragraph 0072).
Regrading claim 8, the combination of Kim et al. in view of Hwang teaches the semiconductor package of claim 7. Kim et al does not teach the two or more fiducial marks having two different shapes.
FIG. 10A and FIG. 11A of Hwang shows he first fiducial marks (115; FIG. 10A; paragraph 0076) may have a circular shape on the plane while the second fiducial mark (125; FIG. 11A; paragraph 0080) may have a cross shape on the plane.
It would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to have the two or more fiducial marks having two different shapes. The differing shapes can allow the side lengths to be more easily measured (paragraph 0082).
Regarding claim 9, the combination of Kim et al. in view of Hwang teaches the semiconductor package of claim 7. Kim et al. does not teach N fiducial marks having N types of shapes, where N is a natural number greater than or equal to 2.
FIG. 10A and FIG. 11A of Hwang shows the first fiducial marks (115; FIG. 10A; paragraph 0076) may have a circular shape on the plane while the second fiducial mark (125; FIG. 11A; paragraph 0080) may have a cross shape on the plane.
It would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to have N fiducial marks having N types of shapes, where N is a natural number greater than or equal to 2. The differing shapes can allow the side lengths to be more easily measured (paragraph 0082).
Regarding claim 10, the combination of Kim et al. in view of Hwang teaches the semiconductor package of claim 7. Kim et al. does not teach shapes of the two or more fiducial marks being the same.
FIG. 10A and FIG. 11C of Hwang teaches each of the first fiducial marks (115; FIG. 10A; paragraph 0076) may have a circular shape on the plane and the second fiducial marks (125a, 12b; FIG. 11C; paragraph 0081) may have a circle shape.
It would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to have the shapes of the two or more fiducial marks being the same. This modification comes as the result of consideration of the size and a degree of integration of the wiring patterns (paragraph 0081).
Regarding claim 11, the combination of Kim et al. in view of Hwang teaches the semiconductor package of claim 10. Kim et al. does not teach, based on two imaginary axes that pass through a center of a rectangular semiconductor package being orthogonal to each other and being positioned parallel to a width or length of the semiconductor package, at least one of the two or more fiducial marks being not symmetrical with the other of the two or more fiducial marks.
FIG. 10A and FIG. 11 of Hwang demonstrate the first fiducial marks (115; FIG. 10A; paragraph 0071) and the second fiducial marks (125; FIG. 10A; FIG. 11A; paragraph 071) as not symmetrical to each other across an axis.
It would have been obvious to someone with ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al. to have the at least one of the two or more fiducial marks being not symmetrical with the other of the two or more fiducial marks. This way, the fiducial marks can serve as alignment marks for different portions (paragraph 0070).
Allowable Subject Matter
Claims 2-5 and 12-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 2 would be allowable as it discloses a semiconductor package wherein the upper redistribution structure comprises a wiring region and a metal layer region electrically spaced apart from the wiring region, and wherein the fiducial mark is in the metal layer region.
Kim et al. teaches the semiconductor package of claim 1. Kim et al. does not teach the upper redistribution structure comprising a wiring region and a metal layer region electrically spaced apart from the wiring region, and wherein the fiducial mark is in the metal layer region.
Hwang et al. does not apply any relevant alteration to the subject matter.
FIG. 5J of Park et al. (20160338202 A1) teaches the redistribution part wiring layer (142; FIG. 5J; paragraph 0127) and the redistribution part vias (143; FIG. 5J; paragraph 0127) may be formed to form the redistribution part (140; FIG. 5J; paragraph 0127). Park et al. does not teach the fiducial marks being within the vias. Based on the configuration of Park et al., it would be inappropriate in hindsight to modify Kim et al. so that the fiducial mark is in the metal layer region.
Claims 3, 4, and 5 would be allowable because they depend on claim 2.
Claim 12 would be allowable as it discloses a semiconductor package wherein each of the two or more fiducial marks has a shape including an asymmetric protrusion angle formed by meeting edges forming a circumference of each of the two or more fiducial marks.
Kim et al. teaches the semiconductor package of claim 10. Kim et al. does not teach each of the two or more fiducial marks having a shape including an asymmetric protrusion angle formed by meeting edges forming a circumference of each of the two or more fiducial marks.
Hwang et al. and Park et al. do not apply any relevant alteration to the subject matter. Based on this configuration, it would be improper in hindsight to modify Kim et al. so that each of the two or more fiducial marks has a shape including an asymmetric protrusion angle formed by meeting edges forming a circumference of each of the two or more fiducial marks.
Claims 13 and 14 would be allowable because they depend on claim 12.
Claims 16-20 are allowed.
Claim 16 would be allowable as it discloses a semiconductor package comprising:
A lower redistribution structure;
an internal semiconductor chip on an upper surface of the lower redistribution structure;
an upper redistribution structure electrically connected to the lower redistribution structure through a conductive post; and
a molding layer between the upper redistribution structure and the lower redistribution structure, the molding layer surrounding the internal semiconductor chip,
wherein the upper redistribution structure comprises:
an insulating layer comprising a redistribution pattern and a first material configured to transmit light; and
a fiducial mark formed of the first material,
wherein a lower surface of the fiducial mark is in contact with an upper surface of the molding layer,
wherein the upper redistribution structure comprises a wiring region and a metal layer region electrically spaced apart from the wiring region, and
wherein the fiducial mark is in the metal layer region.
FIG. 1E of Kim et al. teaches a semiconductor package (paragraph 0012) comprising:
a lower redistribution structure (32; FIG 1E; paragraph 0017);
an internal semiconductor chip (10; FIG 1E; paragraph 0017) on an upper surface of the lower redistribution structure;
an upper redistribution structure (34, 38, 20; FIG. 1E; paragraph 0022) electrically connected to the lower redistribution structure through a conductive post (28; FIG. 1E; paragraph 0021); and
a molding layer (30; FIG. 1E; paragraph 0022) between the upper redistribution structure and the lower redistribution structure, the molding layer surrounding the internal semiconductor chip,
wherein the upper redistribution structure comprises:
an insulating layer (38; FIG. 1E; paragraph 0046) comprising a redistribution pattern (34; FIG. 1E; paragraph 0022) and a first material (21; FIG. 1E; paragraph 0038) configured to transmit light (paragraph 0038); and
a fiducial mark formed of the first material (20, 21; FIG. 1E; paragraph 0038); and
wherein a lower surface (side surface of the 20 as lower surface; FIG. 1E; paragraph 0038) of the fiducial mark being in contact with an upper surface of the molding layer (30; FIG. 1E; paragraph 0015).
Kim et al. does not teach the upper redistribution structure comprising a wiring region and a metal layer region electrically spaced apart from the wiring region, and the fiducial mark being in the metal layer region.
FIG. 5J of Park et al. (20160338202 A1) teaches the redistribution part wiring layer (142; FIG. 5J; paragraph 0127) and the redistribution part vias (143; FIG. 5J; paragraph 0127) may be formed to form the redistribution part (140; FIG. 5J; paragraph 0127). Hur et al. does not teach the fiducial marks being within the vias. Based on the configuration of Park et al., it would be inappropriate in hindsight to modify Kim et al. so that the fiducial mark is in the metal layer region.
Claims 17 and 18 would be allowable as they depend on claim 16.
Claim 19 would be allowable as it discloses a semiconductor package comprising:
A lower redistribution structure;
an internal semiconductor chip on an upper surface of the lower redistribution structure;
an upper redistribution structure electrically connected to the lower redistribution structure through a conductive post; and
a molding layer between the upper redistribution structure and the lower redistribution structure, the molding layer surrounding the internal semiconductor chip,
wherein the upper redistribution structure comprises:
an insulating layer comprising a redistribution pattern and a first material configured to transmit light; and
a fiducial mark formed of the first material,
wherein a lower surface of the fiducial mark is in contact with an upper surface of the molding layer,
wherein the upper redistribution structure comprises a wiring region and a metal layer region electrically spaced apart from the wiring region, and
wherein the fiducial mark is in a part of the metal layer region that does not include a metal layer.
FIG. 1E of Kim et al. teaches a semiconductor package (paragraph 0012) comprising:
a lower redistribution structure (32; FIG 1E; paragraph 0017);
an internal semiconductor chip (10; FIG 1E; paragraph 0017) on an upper surface of the lower redistribution structure;
an upper redistribution structure (34, 38, 20; FIG. 1E; paragraph 0022) electrically connected to the lower redistribution structure through a conductive post (28; FIG. 1E; paragraph 0021); and
a molding layer (30; FIG. 1E; paragraph 0022) between the upper redistribution structure and the lower redistribution structure, the molding layer surrounding the internal semiconductor chip,
wherein the upper redistribution structure comprises:
an insulating layer (38; FIG. 1E; paragraph 0046) comprising a redistribution pattern (34; FIG. 1E; paragraph 0022) and a first material (21; FIG. 1E; paragraph 0038) configured to transmit light (paragraph 0038); and
a fiducial mark formed of the first material (20, 21; FIG. 1E; paragraph 0038); and
wherein a lower surface (side surface of the 20 as lower surface; FIG. 1E; paragraph 0038) of the fiducial mark being in contact with an upper surface of the molding layer (30; FIG. 1E; paragraph 0015).
Kim et al. does not teach the upper redistribution structure comprising a wiring region and a metal layer region electrically spaced apart from the wiring region, and the fiducial mark being in a part of the metal layer region that does not include a metal layer.
FIG. 5J of Park et al. (20160338202 A1) teaches the redistribution part wiring layer (142; FIG. 5J; paragraph 0127) and the redistribution part vias (143; FIG. 5J; paragraph 0127) may be formed to form the redistribution part (140; FIG. 5J; paragraph 0127). Hur et al. does not teach the fiducial marks being within the vias or even in their region. Based on the configuration of Park et al., it would be inappropriate in hindsight to modify Kim et al. so that the fiducial mark is in a part of the metal layer region that does not include a metal layer.
Claim 20 would be allowable as it depends on claim 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Oh et al. (US 20170133293 A1) concerns an electrical component package with insulating layers and a redistribution pattern. Brusberg et al. (US 20210271037 A1) concerns an optical-electrical substrate with a glass body that can support redistribution layers..
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A VLCEK whose telephone number is (571)272-9665. The examiner can normally be reached Mon-Fri, 9:00 AM -5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached at (571) 272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.A.V./Examiner, Art Unit 2817
/RATISHA MEHTA/Primary Examiner, Art Unit 2817