Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1, 4, 5 and 10 are objected to because of the following informalities:
Claim 1, line 2, “the pair” should correctly be “the input pair”.
Claim 4, line 2, “the input pair” should correctly be “the transistors in the input pair”.
Claim 5, line 1, “the resistor circuit includes” should correctly be “the resistor circuit further includes”.
Claim 10, line 2, “the pair” should correctly be “the input pair”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5-7 recite the limitation "the first mentioned transistor”. There is insufficient antecedent basis for this limitation in the claim. For consistency purpose, it is suggested "first mentioned transistor” to be replaced with “transistor”. Alternatively, replacing “a transistor” claimed in claim 1 with “a first transistor” and replacing “the transistor” and “the first mentioned transistor” claimed in dependent claims 3 and 5-7 with “the first transistor”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 4 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Desai et al. (20220065901), hereinafter called DESAI.
Regarding claims 1 and 19, DESAI (Fig. 6) discloses an amplifier circuit comprising: an input pair of transistors (MNa4/MNa2 and MNa3/MNa1), the transistors in the input pair having respective source, drain, gate and bulk terminals; and source degeneration resistors (602) read as a resistor circuit connected to the sources of the transistors in the input pair, the resistor circuit including a transistor (MNa5-MNa8).
Regarding claim 3, wherein the transistor in the resistor circuit has source, drain, gate and bulk terminals, and wherein the bulk terminal of the transistor and the bulk terminal of the transistors in the input pair are connected together.
Regarding claim 4, including a current source (MNa9) connected to provide current through the resistor circuit (602) to the input pair.
Claim(s) 1, 2, 8, 9 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cosentino (20230402980).
Regarding claims 1 and 19, Cosentino (Fig. 2) discloses an amplifier circuit comprising: an input pair of transistors (204 and 206), the transistors in the input pair having respective source, drain, gate and bulk (Vbulk) terminals; and transistors (210 and 212) read as a resistor circuit connected to the sources of the transistors in the input pair, the resistor circuit including a transistor (210 and 212).
Regarding claim 2, a circuit (224 and 214) configured to bias the transistors (210/212) in the resistor circuit in triode region, see para. [0074].
Regarding claim 8, including a capacitor circuit (240, 242) connected to the source of at least one of the transistors (204 and 206) in the input pair.
Regarding claim 9, wherein claimed subject matters are inherently seen in the operation of the reference circuit, see para. [0027]-[0030].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over PRIOR ART(s), above.
Regarding claim 20, only specify intended uses of the invention which are not given any patentable weight as they do not materially effect to the final product claimed. the limitation “applying an output of the circuit/equalizer to a receiver” is seen to define intended use of the invention, wherein the PRIOR ART(s) circuit can be configured/used in communication circuit having a receiver, see para. [0073] of Cosentino.
Allowable Subject Matter
Claims 10-18 are allowed.
Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claims 5-7, prior art(s) does not disclose the resistor circuit further includes a second transistor, and wherein the first transistor in the resistor circuit and the second transistor have gates connected to a bias node, sources connected to the current source and drains connected to respective sources of the transistors in the input pair.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 10-18, prior art(s) does not disclose the resistor circuit including: a first MOS transistor having a first channel terminal connected to the source of a first transistor in the input pair, and a second channel terminal connected to the bulk terminal of the first transistor in the input pair; and a second MOS transistor having a first channel terminal connected to the source of a second transistor in the input pair, and a second channel terminal connected to the bulk terminal of the second transistor in the input pair; circuits to bias the first MOS transistor and the second MOS transistor in a triode region; and a current source connected to provide current through the resistor circuit to the input pair.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The additional reference(s) cited in PTO-892 show further analogous prior art circuitry.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Khanh V. Nguyen whose telephone number is (571) 272-1767. The examiner can normally be reached from 8:30 AM – 5:00 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, LINDGREN BALTZELL ANDREA can be reached on (571) 272-5918. The fax phone numbers for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHANH V NGUYEN/ Primary Examiner, Art Unit 2843
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