DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . 2. Claims 1– 17 are presented for examination in a non-provisional application filed on 09/22 /2023 . Drawings 3. The drawings were received on 09/22/2023 (in the filings). These drawings are acceptable. Double Patenting 4. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the claims at issue are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the reference application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The USPTO internet Web site contains terminal disclaimer forms which may be used. Please visit http://www.uspto.gov/forms/. The filing date of the application will determine what form should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to http://www.uspto.gov/patents/process/file/efs/guidance/eTD-info-I.jsp. 5. Claims 1– 17 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1– 17 of Copending Application No. 18/371,527. 6. Although the claims at issue are not identical, they are not patentably distinct (nonobvious) from each other, because at least some of the subject matter claimed in the instant application is already fully disclosed in the copending applications. This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented. For purposes of illustration, a table has been constructed below to compare the two independent claims and exemplary dependent claims. Instant Application No. 18/ 371,543 Copending Application No. 18 / 371 , 527 1. A system for achieving hard real-time by a non-real-time system in a hardware-in-loop simulation , comprising: a computer device, and the computer device being configured to execute a task creating module and a task thread setting module, wherein, the task creating module is configured to create a real-time model task and form a task program; the task thread setting module is configured to: enable the task program to automatically read computer configuration and determine a number Z of kernels of a processor of a current computer device; when the number Z of the kernels is less than or equal to X, set a thread number to n=1 to execute the real-time model task, and when the number Z of the kernels is greater than X, set the thread number to n=(Z−X)/Y to execute the real-time model task, wherein Y represents a thread number of one physical core of the processor. 1. A method of achieving hard real-time by a non-real-time system in a hardware-in-loop simulation, comprising: creating a real-time model task and forming a task program; automatically reading, by the task program, computer configuration and determining a number Z of kernels of a processor of a current computer device; when the number Z of the kernels is less than or equal to X, setting a thread number to n=1 to execute the real-time model task, and when the number Z of the kernels is greater than X, setting the thread number to n=(Z−X)/Y to execute the real-time model task, wherein Y represents a thread number of one physical core of the processor 2. The system of claim 1, wherein, setting the thread number to n=1 to execute the real-time model task comprises: defining a real-time time interval m for execution of the real-time model task; obtaining a current time t by the thread in real time, and determining, in real time, whether the current time t is greater than a next execution time t_next, when t>t_next, determining t_next=t_next+m and executing the real-time model task at the same time. 2. The method of claim 1, wherein, setting the thread number to n=1 to execute the real-time model task comprises: defining a real-time time interval m for execution of the real-time model task; obtaining a current time t by the thread in real time, and determining, in real time, whether the current time t is greater than a next execution time t_next, when t>t_next, determining t_next=t_next+m and executing the real-time model task at the same time. … … 8 . The system of claim 1, wherein, each set thread occupies one processor physical core, comprising: an index of the processor physical core occupied by each thread being equal to a value obtained by performing Modulo Operation on the corresponding thread index and a total number of processor physical cores. 8 . The method of claim 1, wherein, each set thread occupies one processor physical core, comprising: an index of the processor physical core occupied by each thread being equal to a value obtained by performing Modulo Operation on the corresponding thread index and a total number of processor physical cores. 9. A computer device , applied to a system for achieving hard real-time by a non-real-time system in a hardware-in-loop simulation, and comprising a processor configured to execute a task creating module and a task thread setting module. 10. The computer device of claim 9, wherein, the task creating module is configured to create a real-time model task and form a task program; the task thread setting module is configured to: enable the task program to automatically read computer configuration and determine a number Z of kernels of a processor of the current computer device; when the number Z of the kernels is less than or equal to X, set a thread number to n=1 to execute the real-time model task, and when the number Z of the kernels is greater than X, set the thread number to n=(Z−X)/Y to execute the real-time model task, wherein Y represents a thread number of one physical core of the processor. 10. An electronic device , comprising a processor, a readable storage medium, a communication bus and a communication interface, wherein the processor, the readable storage medium and the communication interface communicate with each other via the communication bus; the readable storage medium is configured to store programs of performing the method of achieving hard real-time by the non-real-time system in the hardware-in-loop simulation according to claim 1; and the programs cause the processor to perform the operations corresponding to the method of achieving hard real-time by the non-real-time system in the hardware-in-loop simulation. … … 17. The computer device of claim 16, wherein, each set thread occupies one processor physical core, comprising: an index of the processor physical core occupied by each thread being equal to a value obtained by performing Modulo Operation on the corresponding thread index and a total number of processor physical cores. 17. The electronic device of claim 10, wherein, each set thread occupies one processor physical core, comprising: an index of the processor physical core occupied by each thread being equal to a value obtained by performing Modulo Operation on the corresponding thread index and a total number of processor physical cores. The Examiner notes that one or more claims in the instant application are directed to a system and claims 1– 8 of Copending Application No. 18/371,527 are directed to a method . However, it would have been obvious to one of ordinary skill in the art to implement a system having a computer and storage devices storing program instructions implementing one or more modules , which when executed by the computer, perform s the method of Copending Application No. 18/371,527 , thus rendering obvious having and using a system to implement the method. Claim Interpretation Under 35 USC § 112 The following is a quotation of 35 U.S.C. 112(f) : (f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof. 7 . The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked. As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f): (A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function; (B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and (C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function. Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function. Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f), is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function . Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action. 8 . This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f), because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: a. “ task creating module ,” and b. “ task thread setting module ,” recited in claim 1 , each configured to or capable of being configured to perform respective claimed functions . Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f), it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f). Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b) : (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. A. 9 . Claim limitations: a. “ task creating module ,” and b. “ task thread setting module ,” recited in claim 1 , invoke 35 U.S.C. 112(f). However, the written description fails to disclose the corresponding structure, material, or acts for performing the entire claimed function and to clearly link the structure, material, or acts to the function. In this instance, and as filed, the disclosure is either devoid of any STRUCTURE that performs the function in the claims, (Here, the disclosure simply does not describe or limit the claimed “data eraser apparatus” or “processing resource” to a known structure or class of structure (e.g. a CPU) capable of performing the claimed function (method) referred in claim 1), or (to the extent that a structure is sufficiently disclosed) that the structure described in the specification does not perform the entire function in the claim. 10 . Therefore, claims 1–8 are indefinite and rejected under 35 U.S.C. 112(b). Applicant may: (a) Amend the claim so that the claim limitation will no longer be interpreted as a limitation under 35 U.S.C. 112(f); (b) Amend the written description of the specification such that it expressly recites what structure, material, or acts perform the entire claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (c) Amend the written description of the specification such that it clearly links the structure, material, or acts disclosed therein to the function recited in the claim, without introducing any new matter (35 U.S.C. 132(a)). If applicant is of the opinion that the written description of the specification already implicitly or inherently discloses the corresponding structure, material, or acts and clearly links them to the function so that one of ordinary skill in the art would recognize what structure, material, or acts perform the claimed function, applicant should clarify the record by either: (a) Amending the written description of the specification such that it expressly recites the corresponding structure, material, or acts for performing the claimed function and clearly links or associates the structure, material, or acts to the claimed function, without introducing any new matter (35 U.S.C. 132(a)); or (b) Stating on the record what the corresponding structure, material, or acts, which are implicitly or inherently set forth in the written description of the specification, perform the claimed function. For more information, see 37 CFR 1.75(d) and MPEP §§ 608.01(o) and 2181. B. 11 . Claim 9 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention and as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. See MPEP § 2172.01. a. Specifically, the following term(s) and/or phrase(s) in the claim language is/are indefinite owing to one or more omitted elements of the claimed steps. i. As to claims 9, the expression: “ A computer device, applied to a system for achieving hard real-time by a non-real-time system in a hardware-in - loop simulation, and comprising a processor configured to execute a task creating module and a task thread setting module ” fails to interrelate essential elements of the invention as defined by applicant in the specification and thus is indefinite. Per the applicant’s specification, the claimed a task creating module and a task thread setting module performs one or more means, functions, or steps “ for achieving hard real-time by a non-real-time system in a hardware-in-loop simulation ,” which are NOT recited in the claim. b. Appropriate corrections are therefore required . Examiner’s Remarks 12 . Examiner refers to and explicitly cites particular pages, sections, figures, paragraphs or columns and lines in the references as applied to Applicant’s claims to the extent practicable to streamline prosecution. Although the cited portions of the references are representative of the best teachings in the art and are applied to meet the specific limitations of the claims, other uncited but related teachings of the references may be equally applicable as well. It is respectfully requested that, in preparing responses to the rejections, the Applicant fully considers not only the cited portions of the references, but also the references in their entirety, as potentially teaching, suggesting or rendering obvious all or one or more aspects of the claimed invention. Abbreviations 13 . Where appropriate, the following abbreviations will be used when referencing Applicant’s submissions and specific teachings of the reference(s): i. figure / figures: Fig. / Figs. ii. column / columns: Col. / Cols. iii. page / pages: p. / pp. References Cited ( A ) Applicant’s Specification, construed as Applicant Admitted Prior Art (“AAPA”). (B) Matz et al. , US 7,401,112 B 1 (“ Matz ”). Notice re prior art available under both pre-AIA and AIA 1 4 . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. A. 1 5 . Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over (A) AAPA in view of (B) Matz . See “References Cited” section, above, for full citations of references. 1 6 . Regarding claim 9 , (A) AAPA teaches/suggests the invention substantially as claimed, including: “ A computer device, applied to a system for achieving hard real-time by a non- real-time system in a hardware-in-loop simulation ” ( ¶ 2: execute a hardware-in-loop simulation task, it is usually required to rely on a real-time system and deploy the execution of the task in the real-time system ); AAPA do not teach “ comprising a processor configured to execute a task creating module and a task thread setting module ” (B) Matz , in the context of AAPA’s teachings, however teaches or suggests implementing “ comprising a processor configured to execute a task creating module and a task thread setting module .” ( Col. 8, lines 40–44: executing a task 250 within a multiprocessor system, such as for example a Symmetrical Multiprocessor (SMP) system ; Col. 8, lines 30–35: the task dispatcher 200 creates a task 250 ( and dispatches the task to queue 128) by creating an instantiation of the workflow identified as being associated with the relevant event. The task 250 may be attributed a priority ; Col. 8, lines 50–55: a “ dispatcher ” within the kernel of an operating system, such as the Windows NT ( operating system, assigns a thread to which the task is assigned to a processor within the multiprocessor system ; Col. 7, lines 52–63: the task queue 128 may intelligently determined a “ BestMatch ” between an available thread and the tasks that are queued within the task queue 128. This “ BestMatch ” determination may be based on any number of parameters, such as a dynamically assigned priority or processor affinity. In identifying a task to be attributed to an available worker thread, the scheduler 204 may identify a “ real-time ” priority associated with a task. Specifically, a task identified as having a “real-time” priority will be regarded as having a highest priority, and assigned to an available thread ahead of any other tasks ; Claim 1: creating a respective task object for each of the transaction events and identified workflows; assigning a task priority to each respective task object … distributing a task object of the task objects, which at least partially executes the workflow, from the task object queue to an available thread within a pool of available threads ). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of (B) Matz with those of (A) AAPA to schedule and assign real-time priority tasks to processor threads/cores . The motivation or advantage to do so is to implement and execute AAPA’s hardware-in-loop simulation task in a muti-processor environment. Allowable Subject Matter 17. Claims 1– 8 would be allowable if rewritten to overcome the indefinite ness reject ion under 35 U.S.C. 112(b). Claims 10–17 are objected to as being dependent upon a rejected base claim, but would be allowable if 1) rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is the Examiner’s statement of reasons for allowance: The prior art of record, when viewed individually or in combination, does not expressly teach nor render obvious the features of dependent claims 6 and 7 when viewed as a whole, specific to the limitation(s) of: “ the task creating module is configured to create a real-time model task and form a task program ; the task thread setting module is configured to: enable the task program to automatically read computer configuration and determine a number Z of kernels of a processor of the current computer device; when the number Z of the kernels is less than or equal to X, set a thread number to n=l to execute the real-time model task, and when the number Z of the kernels is greater than X, set the thread number to n=(Z-X)/Y to execute the real-time model task, wherein Y represents a thread number of one physical core of the processor .” Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN C WU whose telephone number is (571)270-5906. The examiner can normally be reached Monday through Friday, 8:30 A.M. to 5:00 P.M.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Aimee J. Li can be reached on (571)272-4169. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BENJAMIN C WU/ Primary Examiner, Art Unit 2195 March 7, 2026