DETAILED ACTION
Status of Claims
As of the amendment filed 3/3/26, no claims have been added, claim 4 has been canceled, and claims 1, 8, 13, 15, 16, and 20 have been amended. Therefore, claims 1-3 and 5-20 remain pending, with claims 1, 15, and 20 being independent.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3, 5-9, 12, 13, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0262743) in view of Brun (US 2023/0317546)
As to claim 1, Chang teaches a method of splitting a semiconductor chip, the method comprising:
performing a back-end-of-line (BEOL) process comprising:
forming a plurality of chip areas (CR) on a semiconductor substrate (110, fig. 2, [0027] – [0028]);
forming a splitting area (SR), which separates the plurality of chip areas (CR), on the semiconductor substrate (110, fig. 2, [0028]); and
forming a wire on a first surface (110s) of the semiconductor substrate ([0031] “The circuit 120 may include elements having various functions for operating the semiconductor chip.” Lines/wires are known elements needed for operating the chip);
forming a cutout auxiliary layer (160 or 170) in the splitting area (SR) of the first surface (110s) of the semiconductor substrate ([0035]); and
wherein the cutout auxiliary layer (160 or 170) is adjacent to the plurality of chip areas (fig. 1),
wherein the forming the cutout auxiliary layer comprises forming a trench (172) between the plurality of chip areas (CR) and the cutout auxiliary layer (160 or 170) in a horizontal direction (fig. 2, trench 172 is formed in both the x-axis and y-axis direction).
Chang does not explicitly teach the trench is formed using a mechanical machining process by bringing a mechanical machining device into contact with the cutout auxiliary layer. However, using a saw to form a trench within a scribe area is known in the art (Brun, fig. 7A, [0093]). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the sawing method of Brun to form the trench so as to use an industrially tested and accepted method of forming a trench in a scribe region.
As to claim 2, Chang further teaches the cutout auxiliary layer comprises silicon ([0035], layer 170 may include an oxide. Silicon oxide is obvious)
As to claim 3, Chang further teaches the cutout auxiliary layer comprises tetraethoxysilane (TEOS) ([0036], layer 160).
As to claims 5 and 6, Chang does not teach forming a test element group (TEG) structure and an alignment key below the cutout auxiliary layer, wherein the cutout auxiliary layer has an opening portion exposing at least a part of the alignment key. However, alignment keys in scribe areas are very well-known in the art and would have been obvious so as to help with alignment of the saw to the scribe line.
Chang does not teach the cutout auxiliary layer has an opening portion exposing at least a part of the alignment key. However, in order for the alignment key to function as an alignment device, it would need to be "visible" to the detector. If that requires removing the material above it, then that is an obvious modification.
As to claim 7, Chang further teaches forming an interlayer insulating film (170) and a gap-filling insulating film (190) at least partially above the plurality of chip areas (CR) and the splitting area (SR) of the semiconductor substrate (fig. 7, [0050]), and wherein the forming the cutout auxiliary layer further comprises forming an upper surface of the cutout auxiliary layer (160) to be lower than an upper surface of an uppermost layer of the gap-filling insulating film (190) in a vertical direction (fig. 7).
As to claims 8 and 9, Chang further teaches forming the trench between the gap-filling insulating film (the part of 170 to the left of the trench 172) and the cutout auxiliary layer (the part of 160 to the right of trench 172, fig. 1, the trench is between the two portions of the layers. Both sides of each layer are formed at the same time, respectively.).
As to claim 12, Brun further teaches the mechanical machining comprises at least one of sawing based on a blade and scribing based on a scriber ([0093]).
As to claim 13, Chang further teaches a width of the cutout auxiliary layer is larger than a width of a cutting area with which a tip of the blade or the scriber comes into contact (Chang, fig. 1).
As to claim 15, Chang teaches a semiconductor chip comprising:
a semiconductor substrate (110, fig. 1, [0027] – [0028]);
a plurality of chip areas (CR) on the semiconductor substrate (110, fig. 2, [0028]);
a splitting area (SR) between the plurality of chip areas (CR, fig. 2, [0028]);
a plurality of wiring layers (metallization layers within 110 for circuit 120) on the semiconductor substrate (fig. 1, [0031]);
a plurality of interlayer insulating films between the plurality of wiring layers (fig. 1, all the vias and lines within 110 are separated by insulating layers);
a plurality of gap-filling insulating films (182 and 190) on the plurality of interlayer insulating films (fig. 1, [0045] and [0059]); and
a cutout auxiliary layer residual portion (portion of 160 or 170 to the right of trench 172 in fig. 1) on the plurality of interlayer insulating films in the splitting area ([0035] – [0036]); and
a trench (172) between the plurality of chip areas (CR) and the cutout auxiliary layer residual portion (portion of 160 or 170 to the right of trench 172 in fig. 1) in a horizontal direction (fig. 2, trench 172 extends in both the x-axis direction and the y-axis direction, [0039]),
wherein the cutout auxiliary layer residual portion extends along an outer periphery of the semiconductor substrate (fig. 1) and surrounds the plurality of gap-filling insulating films (184 and 190).
As to claim 16, Chang further teaches the trench is between the gap-filling insulating film (the part of 170 to the left of the trench 172) and the cutout auxiliary layer (the part of 160 to the right of trench 172, fig. 1, the trench is between the two portions of the layers. Both sides of each layer are formed at the same time, respectively.).
As to claim 17, Chang further teaches the cutout auxiliary layer comprises tetraethoxysilane (TEOS) ([0036], layer 160).
As to claims 18 and 19, Chang does not teach forming a test element group (TEG) structure and an alignment key below the cutout auxiliary layer, wherein the cutout auxiliary layer has an opening portion exposing at least a part of the alignment key. However, alignment keys in scribe areas are very well-known in the art and would have been obvious so as to help with alignment of the saw to the scribe line.
Chang does not teach the cutout auxiliary layer has an opening portion exposing at least a part of the alignment key. However, in order for the alignment key to function as an alignment device, it would need to be "visible" to the detector. If that requires removing the material above it, then that is an obvious modification.
As to claim 20, Chang teaches a semiconductor chip comprising:
A semiconductor substrate (110);
an active chip area (CR) comprising a plurality of wiring layers and a plurality of circuit elements (120) on the semiconductor substrate (110, [0031], fig. 1);
a moistureproof structure (any of the insulting films between the trench 172 and the circuit areas 120) adjacent to the active chip area (fig. 1, [0032]);
a chip dam (130) adjacent to the moistureproof structure (fig. 1, [0032]);
a plurality of interlayer insulating films between the plurality of wiring layers (fig. 1, all the vias and lines within 110 are separated by insulating layers);
a plurality of gap-filling insulating films (182 and 190) on the plurality of interlayer insulating films (fig. 1, [0045] and [0059]);
a cutout auxiliary layer residual portion (portion of 160 or 170 to the right of trench 172 in fig. 1) on the plurality of interlayer insulating films ([0035] – [0036]); and
a trench (172) between the plurality of gap-filling insulating films (182 and 190) and the cutout auxiliary layer residual portion (portion of 160 or 170 to the right of trench 172 in fig. 1), the trench (172) being between the active chip area and the cutout auxiliary layer residual portion in a horizontal direction (fig. 2, trench 172 extends in both the x-axis direction and the y-axis direction, [0039]),
wherein the cutout auxiliary layer residual portion extends along an outer periphery of the semiconductor substrate (fig. 1) and surrounds the plurality of gap-filling insulating films (184 and 190).
Claim(s) 14 is rejected under 35 U.S.C. 103 as being unpatentable over Chang in view of Tseng (US 2022/0016768).
As to claim 14, Chang does not teach between the forming the cutout auxiliary layer and the performing the mechanical machining, further comprising: attaching an auxiliary substrate on a front surface of the semiconductor substrate; performing a backside process on a back surface of the semiconductor substrate; attaching an expanding tape on a back surface of the auxiliary substrate; and separating the auxiliary substrate.
However, attaching the front side of a substrate to a temporary carrier and grinding the backside of the substrate is very well-known in the art so as to prepare the backside for backside processing.
Furthermore, using an expanding tape in conjunction with a partial dicing process (i.e. a two step-process) is known in the art (see [0024] of Tseng).
Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use the two-step process of Tseng to singulate the dies from the wafer so as to reduce stresses and cracking damage.
Allowable Subject Matter
Claims 10 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 10, the prior art fails to teach forming an interlayer insulating film and a gap-filling insulating film at least partially above the plurality of chip areas and the splitting area of the semiconductor substrate, and wherein the forming the cutout auxiliary layer further comprises forming an upper surface of the cutout auxiliary layer and an upper surface of an uppermost layer of the gap-filling insulating film at a same level in a vertical direction.
All of the layers of Chang are stacked; thus they would not ever be at the same level in the vertical direction.
Claim 11 is allowable at least because it depends from allowable claim 10.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3 and 5-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/30/26