Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07/29/2026 have been fully considered but they are not persuasive.
Applicant submitted that Portolan in view of Pillin does not teach or suggest "the communication engine is configured to receive the test service requirement from the central scheduling apparatus" and "the hardware management engine is configured to manage running of a test device in the test apparatus, wherein the test device is configured to provide test signals for the vehicle simulation apparatus or collect data of the vehicle simulation apparatus" as recited in claim 1. The Examiner respectfully disagrees.
The Examiner notes that a “communication engine and a hardware management engine” have been interpreted as a software application, module, process, interface, and the like.
Portolan ([0040, 0052-0054]) discloses that the test controller receives test vectors from the TGT 116 to apply for testing the DUT 102. Communication of the test code and vectors is generated by the TGT and supplied to the test controller 106 by the intermediary of a specialized API interface. Thus, the test controller uses its specialized API interface (i.e. communication engine) to receive testing codes and vectors from the TGT (i.e. scheduler).
Furthermore, Portolan ([0036, 0055, 0062]) discloses that the test controller 106 executes a test sequence in the DUT 102 based on test patterns by the intermediary of a test interface (INTERFACE) 108. The execution of the test code 308 entails the application of test patterns and test algorithms to the DUT 102 via the test controller 106. The test code includes test patterns and test algorithms wrapped in code which can be executed by the processors of a test device used to execute the test code, e.g. Test controller 106. Therefore, in order to run the test on the DUT 102, the test controller employs at least a processor and a test interface to execute the test sequences and test codes/algorithms/patterns for a certain test on the DUT.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Portolan (US 20200150177) in view of Pillin et al. (US 20070118319).
Regarding claim 1, Portolan discloses a test system (test system 100 of FIG. 1; [0034]), comprising:
a central scheduling apparatus (test generation tool (TGT) 116; [0037]);
a test apparatus (test controller 106 of FIG. 1; [0036]); and
a simulation apparatus (integrated circuit 101 includes a device being tested (DUT) 102 of FIG. 1. FIG. 5C shows the DUT is simulated; [0035, 0068]),
wherein the test apparatus establishes communication with the central scheduling apparatus (Fig. 1; TGT 116 communicates with the test controller 106; [0038]);
the central scheduling apparatus is configured to send a test service requirement to the test apparatus (in order to apply tests to each test instrument 202 to 216, PDL (Procedural Definition Language) is for example used by the TGT 116 to wrap the test vectors and allow for the application thereof by the test controller 106; [0040]);
the test apparatus is configured to test the simulation apparatus based on the test service requirement (test controller implements the test based on the PDL file by applying the test patterns to the DUT by the intermediary of the test controller 106; [0042]);
the simulation apparatus comprises a controller and a second terminal block (FIG. 2; Integrated circuit 101 includes the TAP 104, and three circuit blocks 102A, 102B, 102C formant the DUT 102; [0039]),
wherein the controller and the test apparatus are connected to the second terminal block to establish communication (Figs. 1-2; TAP 104 communicates with test controller 106 by a test interface 108. circuit blocks 102A-Care connected to the TAP 104; [0036, 0039]), and
the controller is configured to respond to the test performed by the test apparatus (execution of the test code 308 by the TGT 302 causes for example the application of test patterns and of test algorithms to the DUT 102 via the interface controller 310 and the test controller 106, and data returned by the DUT 102 is for example supplied in return to the TGT 302 so that it can be interpreted; [0055]);
the test apparatus comprises a communication engine and a hardware management engine (Fig. 3B, interface controller 310 is coupled to the test controller 106 by the intermediary of a specialised API interface, the specialised interface in the example of FIG. 3B being for example a JTAG interface. The test controller 106 is coupled to the integrated circuit 101 by the intermediary of the interface 108; [0054].
the test code includes test patterns and test algorithms wrapped in code which can be executed by the processors of any test device used to execute the test code; [0062]);
the communication engine is configured to receive the test service requirement from the central scheduling apparatus (TGT 116 to wrap the test vectors and allow for the application thereof by the test controller 106; [0040].
communications to the DUT 102 generated by the execution of the test code 308 are for example supplied by the intermediary of an abstract API (application programming interface) to an interface controller (INTERFACE DRIVER) 310. Interface controller 310 is coupled to the test controller 106 by the intermediary of a specialized API interface; [0052-0054]); and
the hardware management engine is configured to manage running of a test device in the test apparatus, wherein the test device is configured to provide test signals for the simulation apparatus or collect data of the simulation apparatus (TAP 104 communicates for example with a test controller (TEST CONTROLLER) 106 by the intermediary of a test interface (INTERFACE) 108. The test controller 106 executes a test sequence in the DUT 102 based on test patterns (INPUT PATTERNS) 110; [0036].
Execution of the test code 308 by the TGT 302 causes the application of test patterns and test algorithms to the DUT 102 via the test controller 106. The test code includes test patterns and test algorithms wrapped in code which can be executed by the processors of any test device used to execute the test code; [0055, 0062].
FIG. 5C, the interface between the TGT 302 and the DUT 102 is done by the intermediary of a DPI (Direct Programming Interface), that implements the interface controller 310, and by DPI calls 518, and the DUT 102 is accessed by using a DPI-enabled simulator (DPI-ENABLE SIMULATOR) 520 including the testbench SV (SV TESTBENCH) 516.; [0068]).
Portolan does not expressly disclose a vehicle simulation apparatus comprising a vehicle controller connected to a second terminal block; test the vehicle simulation apparatus based on test service requirement; and the vehicle controller configured to respond to the test.
In an analogous art, Pillin discloses a vehicle simulation apparatus comprising a vehicle controller connected to a second terminal block (system for testing control processes in a vehicle must be able to simulate all units shown in FIG. 1, except for the controller itself; [0023]);
test the vehicle simulation apparatus based on test service requirement (the test system is equipped with software enabling the user to place the controller into operation. the controller switches to an emergency operating mode which causes a test carried out using the test system to be no longer unconditionally relevant; [0023]); and
the vehicle controller configured to respond to the test (control unit signals SGS, which correspond to electronic control unit (ECU) pins, or ECUL through ECU3 in FIG. 4, are obtained. Multiple hardware signals are provided for different signal patterns in the case of real-time I/O 302 or downstream from the open-loop configuration, represented here as hardware signals HWS, RTI/O1 through RTI/04. Model signals MS, designated M1 through M5 in this example, are likewise used at intervention point 312. The number of individual signals in the signal groups is selected at random and largely depends on the signal patterns according to the test in question; [0037]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Pillin into the system of Portolan in order to improve test systems with regard to control processes in a vehicle, in particular in the case of hardware-in-the-loop test systems (Pillin; [0004]).
Regarding claim 2, the combination of Portolan and Pillin, particularly Pillin discloses wherein the vehicle simulation apparatus further comprises: an electrical load; and a first terminal block, wherein the vehicle controller and the electrical load are connected to the first terminal block to establish communication (The diagram shown in FIG. 2 is viewed in a clockwise direction, starting with controller 200. The output signals of the controller are detected by an optional signal detector. If the controller is provided as a physical object, signal detector 201 is, for example, a hardware component. It is followed by a further optional unit which converts the electrical signals to physical units, e.g., a voltage to a temperature. The dynamic behavior of the actuator in the test system is subsequently simulated in block 203. This is followed by a simulation of the driver, environment, and the rest of the vehicle before the signal pattern is supplied back to controller 200 via units for generating signals, i.e., a dynamic sensor model 205, a static sensor model 206, and a signal generator 207; [0024]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Pillin into the system of Portolan in order to improve test systems with regard to control processes in a vehicle, in particular in the case of hardware-in-the-loop test systems (Pillin; [0004]).
Regarding claim 3, the combination of Portolan and Pillin, particularly Pillin discloses wherein the first terminal block is further connected to the second terminal block (Component 300 to be tested, triggering the control processes, for example the control unit or regulator (hardware- or software-implemented), is connected to a block 301 of the hardware and a block 302 of the real-time input/output (real-time i/o). Corresponding to each signal direction, an open loop configuration OLC is optionally provided between block 302 and experiment software 306; blocks 303 and 304, depending on the signal direction; [0031]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Pillin into the system of Portolan in order to improve test systems with regard to control processes in a vehicle, in particular in the case of hardware-in-the-loop test systems (Pillin; [0004]).
Regarding claim 4, the combination of Portolan and Pillin, particularly Portolan discloses wherein an interface of the second terminal block configured to establish the communication comprises a digital channel interface, an analog channel interface, and/or a bus channel interface (FIG. 5A diagrammatically shows the portion 300B according to an embodiment wherein the interface between the TGT 302 and the DUT 102 is provided by an FTDI chip (Future Technology Devices International Ltd) (FTDI CHIP) 502, which converts for example a USB (universal serial bus) interface into the JTAG interface (JTAG) 504. In this embodiment, the interface controller 310 includes for example a LibFTDI drivers (LIB FTDI DRIVER), which is for example low-level code used to control the FTDI chip 502, and the configuration information 314 identifies for example this LibFTDI driver so that it can be selected for the conversion; [0066]).
Regarding claim 5, the combination of Portolan and Pillin, particularly Pillin discloses wherein the test apparatus is further configured to communicate between at least two vehicle controllers included in the vehicle simulation apparatus (assigning identifiers is a logic operations graph 500, as shown in FIG. 5. This graph shows the signals according to the table in FIG. 4, ECU1 through ECU3, RTI/O1 through RTI/O4, and M1 through M5, once again by way of example. To simplify the representation, the directional arrows in this graph are selected in both directions; [0040]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Pillin into the system of Portolan in order to improve test systems with regard to control processes in a vehicle, in particular in the case of hardware-in-the-loop test systems (Pillin; [0004]).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Portolan (US 20200150177) in view of Pillin et al. (US 20070118319), and in view of Mihaltan et al. (US 20190244444).
Regarding claim 6 the combination of Portolan and Pillin does not expressly disclose at least two test apparatuses, comprising the test apparatus; at least two vehicle simulation apparatuses, comprising the vehicle simulation apparatus, wherein the at least two vehicle simulation apparatuses establish the communication with the at least two test apparatuses in a one-to-one correspondence manner; and the central scheduling apparatus is further configured to implement the communication between the at least two test apparatuses.
In an analogous art, Mihaltan discloses at least two test apparatuses, comprising the test apparatus; at least two vehicle simulation apparatuses, comprising the vehicle simulation apparatus (While this embodiment illustrates two remote servers, in other embodiments, the data server 120 and the voice server 140 may be implemented by a single remote server. The data server 120 may be a remote test server that is configured to receive a hypertext transfer protocol (HTTP) request or HTTP secure (HTTPS) request from the VVSA 100 with data corresponding to the operational characteristics and/or identifying information of the DCM 20; [0042]),
wherein the at least two vehicle simulation apparatuses establish the communication with the at least two test apparatuses in a one-to-one correspondence manner; and the central scheduling apparatus is further configured to implement the communication between the at least two test apparatuses (the external communication API 104 may provide an interface for a central command module 150 to control the FPGA and relay module 105, the RF module 106, the audio module 108, the logging module 110, the USB module 112, and/or the flash enable module 114. The central command module 150 may be configured to selectively activate various modules of a plurality of DCM test bench systems 72. As an example, using the central command module 150, an operator may simultaneously and remotely activate the RF module 106 of five DCM test bench systems 72; [0051]).
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to add the features taught by Mihaltan into the system of Portolan and Pillin in order to improve the testing of automotive electronic control units (Mihaltan; [0002]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Acharya et al. (US 20190265965), “SYSTEM AND METHOD FOR UPDATING SOFTWARE IN AN ELECTRONIC DEVICE.”
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to OUSSAMA ROUDANI whose telephone number is (571)272-4727. The examiner can normally be reached 8:30 AM - 5:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, UN C CHO can be reached at (571) 272 7919. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/OUSSAMA ROUDANI/Primary Examiner, Art Unit 2413
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