DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . The amendment filed 12/02/2025 has been received and considered. Claims 21-40 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 29, 30, 39, and 40 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
Claim 29 recites the limitation "wherein mapping the second finite element model to one or more finite elements of the first finite element model" in line(s) 2-3. There is insufficient antecedent basis for this limitation in the claim. There is no "mapping the second finite element model to one or more finite elements of the first finite element model" anteceding this limitation in the claim.
As to claims 30, 39, and 40, the same deficiency applies.
Dependent claims inherit the defect of the claim from which they depend.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Examiner would like to point out that any reference to specific figures, columns and lines should not be considered limiting in any way, the entire reference is considered to provide disclosure relating to the claimed invention.
Claims 21-24, 26-34, and 36-40 are rejected under 35 U.S.C. 103(a) as being unpatentable over Zeki Celik, (Celik hereinafter), U.S. Pre–Grant publication 20090030660, taken in view of Shinichi Yamane, (Yamane hereinafter), International Pub. No. JP 2005115859, and further in view of Rajiv Lochan Rath, (Rath hereinafter), U.S. Patent 9715571.
As to claim 21, Celik discloses a non-transitory machine-readable medium storing executable instructions which when executed by a data processing system cause the data processing system to perform a machine implemented method (see "[0055]… computer-readable medium… executed by a computing device perform… a process"), the method comprising… generating a first finite element model of the dielectric board (see "[0025]… process 100 for generating a fully-detailed finite element model of an electronic structure, such as an electronic package and/or a printed circuit board (PCB)"; "[0039]… finite elements corresponding to dielectric material are assigned a dielectric material property") and a second finite element model of the electronic component (see "electronic component" as " vias… traces", "[0030]… converts the geometrical information from each table to a two-dimensional array, for example. The data for individual layers are used to generate two-dimensional footprints for the geometry of each layer, which include all of the layer attributes, such as locations of vias, via plating, individual traces, etc")… and generating a final finite element model for the circuit board design (see "[0041]… steps 108 through 111 are repeated for each layer of the package and/or PCB board being modeled")…
While Celik discloses generating a first finite element model of the dielectric board and a second finite element model of the electronic component and generating a final finite element model for the circuit board design, Celik fails to disclose receiving a printed circuit board design comprising an electronic component and a dielectric board…
Yamane discloses receiving a printed circuit board design for an electronic component embedded in a dielectric board (see "input function for inputting design information of a printed circuit board and each mounted component mounted on the printed circuit board" in page 4, 12th paragraph)…(see "when creating the three-dimensional finite element model… a condition for fixed contact is given as an analysis condition in order to separately model the printed circuit board and the mounted component" in page 7, 1st paragraph)…
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Yamane with Celik, because Yamane "creates a reference surface of the board based on the outer shape information of the printed board, and also based on the two-dimensional model information of each mounted part and the arrangement information of each mounted part on the printed board...", and as a result, Yamane reports that "… after a two-dimensional finite element model is created by performing element division on each reference surface created… with an element division size that can create a quadrilateral element, this two-dimensional finite element model is created. Since the three-dimensional finite element model is created by extending the element model in the height direction, it is possible to create a three-dimensional finite element model composed of hexahedral elements and having high analysis accuracy" (see page 3, 10th paragraph).
While Celik and Yamane disclose generating a first finite element model of the dielectric board and a second finite element model of the electronic component, Celik and Yamane fail to disclose wherein the second finite element model includes a plurality of geometric domains… mapping each of the plurality of geometric domains of the second finite element model to one or more finite elements of the first finite element model using interactions between the electronic component and the dielectric board in the circuit board.
Rath discloses wherein the second finite element model includes a plurality of geometric domains (see “geometry of the PCB, including but not limited to, the board outline and any holes, and the conductor (e.g., metal) geometry are read in from electronic computer-aided design (CAD) layout data of the PCB. At 504, a finite element mesh is generated based at least in part on the geometry data related to the PCB. The finite element mesh includes… mesh components (elements). For example, the PCB geometry is discretized into the finite element mesh, and the mesh components can be of any polygonal shapes, such as triangular shapes, rectangular shapes, etc.” in col. 3, lines 21-34)… mapping each of the plurality of geometric domains of the second finite element model to one or more finite elements of the first finite element model (see "first finite element model" as "PCB" – "A finite element mesh is generated based at least in part on the geometry data related to the PCB, the finite element mesh including… mesh components… conductors passing through the… mesh components are identified" in col. 2, lines 9-12 or "PCB simulation system 104 implements a conductor (e.g., metal) fraction algorithm to simplify a finite element analysis (FEA) model and provide accurate displacement calculations… the PCB simulation system 104 constructs a finite element mesh for a PCB and interpolates trace data onto the mesh" in col. 2, lines 53-59 and "second finite element model" as "conductor (e.g., copper) fraction" – "the geometry of the PCB, including but not limited to, the board outline and any holes, and the conductor (e.g., metal) geometry" in col. 3, lines 24-26;“PCB simulation system 104 generates a mesh based on the conductor fractions distribution information and maps physical properties (e.g., mechanical properties, structural properties, thermal properties, etc.) of the PCB to the mesh… conductor (e.g., copper) fraction data of a PCB is imported for generating a finite element mesh, and physical properties are mapped to the mesh" in col. 4, lines 2-17) using interactions between the electronic component and the dielectric board in the circuit board (see "interactions" as "physical properties (e.g., mechanical properties, structural properties, thermal properties, etc.)", “PCB simulation system 104 generates a mesh based on the conductor fractions distribution information and maps physical properties (e.g., mechanical properties, structural properties, thermal properties, etc.) of the PCB to the mesh… physical properties are mapped to the mesh" in col. 4, lines 2-17).
About Examiner's interpretation of "wherein the second finite element model includes a plurality of geometric domains", Examiner notes that as per dependent claim 29, "wherein mapping the second finite element model to one or more finite elements of the first finite element model comprises: dividing the second finite element model into a plurality of geometric domains corresponding to a finite element of the first finite element model". The Application Description also reads: "[0041] The discretized component representations 422A-N may be divided into smaller geometric domains 426 so that each of the domains corresponds directly to a finite element of the matrix of finite elements of the modeled dielectric board 412".
About Examiner's interpretation of "mapping each of the plurality of geometric domains of the second finite element model to one or more finite elements of the first finite element model", Examiner notes that as per the Application Description ('[0005]… physical properties associated with PCB component model may then be mapped to the component finite elements embedded in the model of dielectric board'), Rath discloses the same mapping than the Application Description.
About Examiner's interpretation of "using interactions between the electronic component and the dielectric board in the circuit board", Examiner notes that as per the Application Description ('[0029] interactions (e.g., thermal interactions, mechanical interactions, etc.) between surfaces'), Rath discloses the same surface interactions than the Application Description.
Examiner notes that Rath's mesh is a finite element model (see "A finite element mesh is generated based at least in part on the geometry data related to the PCB, the finite element mesh including… mesh components… conductors passing through the… mesh components are identified" in col. 2, lines 9-12 and "PCB simulation system 104 can model PCBs… PCB simulation system 104 can perform board level simulations based on the determined mesh model" in col. 4, lines 30-44).
Celik, Yamane, and Rath are analogous art because they are related to PCB modeling.
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Rath with Celik and Yamane, because Rath discloses that his "PCB simulation system 104 can assist the users 102 for accurate reliability analysis of PCBs. Specifically, the PCB simulation system 104 implements a conductor (e.g., metal) fraction algorithm to simplify a finite element analysis (FEA) model and provide accurate displacement calculations" (see col. 2, lines 51-56), and as a result, Rath reports that "the features of the mapped physical properties are captured more accurately if the mesh density is increased… the PCB simulation system 104 can adjust the mesh density to optimize between accuracy required and computational time" (see col. 4, lines 22-26).
As to claim 22, Rath discloses wherein the interactions are surface interactions (see "surface interactions" as "physical properties (e.g., mechanical properties, structural properties, thermal properties, etc.)", “PCB simulation system 104 generates a mesh based on the conductor fractions distribution information and maps physical properties (e.g., mechanical properties, structural properties, thermal properties, etc.) of the PCB to the mesh… physical properties are mapped to the mesh" in col. 4, lines 2-17).
About Examiner's interpretation of "surface interactions", Examiner notes that as per the Application Description ('[0029] interactions (e.g., thermal interactions, mechanical interactions, etc.) between surfaces'), Rath discloses the same surface interactions than the Application Description.
As to claim 23, Rath discloses wherein the second finite element model comprises a discretized representation of the electronic component (see “electronic component “ as “any holes, and the conductor“, “the geometry of the PCB, including… any holes, and the conductor (e.g., metal) geometry”, “The finite element mesh includes… mesh components (elements). For example, the PCB geometry is discretized into the finite element mesh, and the mesh components can be of any polygonal shapes, such as triangular shapes, rectangular shapes, etc.” in col. 3, lines 21-34).
As to claim 24, Rath discloses wherein the discretized representation comprises one or more physical properties of the electronic component (see “conductor (e.g., copper) fraction data of a PCB is imported for generating a finite element mesh, and physical properties are mapped to the mesh” in col. 4, lines 13-17).
As to claim 26, Celik discloses wherein the first finite element model is generated based on a geometry of the dielectric board (see "[0054]… an exact replica of the electronic package as designed can be created for numerical analysis. Since the model includes all geometrical information regarding the package and/or board design") independent of the electronic component (see "independent" as "individual", "[0025]… generating a fully-detailed finite element model of an electronic structure, such as an electronic package and/or a…PCB"; "[0039]… finite elements corresponding to dielectric material are assigned a dielectric material property"; "[0030]… converts the geometrical information from each table to a two-dimensional array, for example. The data for individual layers are used to generate two-dimensional footprints for the geometry of each layer, which include all of the layer attributes, such as locations of vias, via plating, individual traces, etc. along x and y axes").
As to claim 27, Celik discloses simulating, based on the final finite element model, operation of the circuit board (see "[0049]… solution phase for analyzing the resulting numerical geometric model of the electronic structure (e.g., electronic package and/or PCB board). Typical numerical analysis tools have a solution module with which thermal, mechanical, electrical, CFD and coupled physical simulations, for example, can be performed on each meshed element and the nodes attached to the meshed elements"); and Yamane discloses identifying, based on the simulation, thermal stresses associated with operation of the circuit board (see "analysis condition database storing dedicated analysis conditions according to the type of analysis model and the type of analysis solver, and may define necessary analysis conditions for each model to be analyzed. For example, if you want to perform structural analysis on the created 3D finite element model, use the data stored in advance in the analysis condition database to define the analysis conditions for the model's structural analysis and perform thermal analysis… a result determination reference database that stores evaluation reference values including strain values and stress values that cause damage to the printed circuit board and components" in page 4, 5th & 7th paragraphs).
As to claim 28, Yamane discloses wherein the second finite element model of the electronic component comprises (see "two-dimensional finite element model is created" in page 3, 10th paragraph).
As to claim 29, Rath discloses wherein mapping the second finite element model to one or more finite elements of the first finite element model (see "physical properties are mapped to the mesh" in col. 4, lines 16-17) comprises: dividing the second finite element model into a plurality of geometric domains corresponding to a finite element of the first finite element model (see “the geometry of the PCB, including but not limited to, the board outline and any holes, and the conductor (e.g., metal) geometry are read in from electronic computer-aided design (CAD) layout data of the PCB. At 504, a finite element mesh is generated based at least in part on the geometry data related to the PCB. The finite element mesh includes… mesh components (elements). For example, the PCB geometry is discretized into the finite element mesh, and the mesh components can be of any polygonal shapes, such as triangular shapes, rectangular shapes, etc.” in col. 3, lines 21-34); and mapping properties of each geometric domain of the second finite element model to the corresponding finite element of the first finite element model (see “conductor (e.g., copper) fraction data of a PCB is imported for generating a finite element mesh, and physical properties are mapped to the mesh” in col. 4, lines 13-17).
As to claim 30, Celik discloses wherein mapping the second finite element model to one or more finite elements of the first finite element model comprises: copying properties of each geometric domain to the corresponding finite element of the first finite element model (see “[0035]… Beginning at step 108, the two-dimensional information in each layer is then processed to create a three-dimensional geometric model for that layer… [0036] At step 109, process 100 assigns individual geometry to components of each layer… [0039] … the finite elements corresponding to dielectric material are assigned a dielectric material property… [0041] … steps 108 through 111 are repeated for each layer of the package and/or PCB board being modeled”).
As to claims 31-34 and 36-40 these claims recite a method performed by the medium storing executable instructions of claims 21-24 and 26-30. Celik discloses "[0055]… computer-readable medium… executed… perform… a process" that teaches claims 21-24 and 26-30. Therefore, claims 31-34 and 36-40 are rejected for the same reasons given above.
Claims 25 and 35 are rejected under 35 U.S.C. 103(a) as being unpatentable over Celik taken in view of Yamane in view of Rath as applied to claims 24 and 34 above, and further in view of Dogruoz and Nagulapally, (Dogruoz hereinafter), "Effects of trace layers and joule heating on the temperature distribution of printed circuit boards: a computational study".
As to claims 25 and 35, while Celik, Yamane, and Rath disclose physical properties, Celik, Yamane, and Rath fail to disclose wherein the one or more physical properties comprise one or more non-linear properties.
Dogruoz discloses wherein the first set and the second set of physical properties comprise one or more non-linear properties of a corresponding finite element (see "governing equations are nonlinear" in page 2, next to last paragraph).
Celik, Yamane, Rath, and Dogruoz are analogous art because they are related to PCB modeling.
Therefore, it would have been obvious to one of ordinary skill in this art before the effective filing date of the claimed invention to use Dogruoz with Celik, Yamane, and Rath, because Dogruoz discloses that "effects of the trace and via geometry are accurately modeled in the physical model by importing electronics computer aided-design data consisting of the trace and via layout of the board and computing locally varying orthotropic conductivity (kx, ky, and kz) on the printed circuit board using a background mesh" (see page 1, 1st paragraph), and as a result, Dogruoz reports that "the spatially varying orthotropic conductivity is then mapped from the background mesh to the CFD mesh and used in a system-level simulation of the PCB with a minimal increase in the overall computational cost" (see page 1, 1st paragraph).
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 21, 22, 25-28, 31, 32, and 35-38 are rejected on the ground of nonstatutory double patenting as being unpatentable over claim 1, 6, 7, 10, 11, 16, 17, and 20 of U.S. Patent No. 11797731. Although the claims at issue are not identical, they are not patentably distinct from each other because at the time of the invention, it would have been obvious, to an artisan of ordinary skill to have derived the instant claims using the patented claims in the issued patent.
Instant Claims
11797731 Claims
21. A non-transitory machine readable medium storing executable instructions which when executed by a data processing system cause the data processing system to perform a machine implemented method, the method comprising: receiving a circuit board design for a circuit board comprising an electronic component and a dielectric board;
1. A non-transitory machine readable medium storing executable instructions which when executed by a data processing system cause the data processing system to perform a machine implemented method, the method comprising: receiving a printed circuit board design for an electronic component embedded in a dielectric board;
generating a first finite element model of the dielectric board and a second finite element model of the electronic component separate from the first finite element model,
26. The non-transitory machine readable medium of claim 21, wherein the first finite element model is generated based on a geometry of the dielectric board independent of the electronic component
generating a first finite element model to represent the dielectric board independent of the electronic component; generating a second finite element model for the electronic component separate from the first finite element model of the dielectric board…
wherein the second finite element model includes a plurality of geometric domains;
and generating a final finite element model for the circuit board design, by mapping each of the plurality of geometric domains of the second finite element model to one or more finite elements of the first finite element model using interactions between the electronic component and the dielectric board in the circuit board
22. The non-transitory machine readable medium of claim 21, wherein the interactions are surface interactions
identifying surface interactions between the dielectric board and the electronic component in the printed circuit board design; dividing the second finite element model into a plurality of geometric domains based on the surface interactions, each geometric domain corresponding to a finite element of the first finite element model of the dielectric board; and combining the first finite element model with the second finite element model to obtain a final finite element model for the printed circuit board design by mapping each geometric domain of the second finite element into a corresponding finite element of the first finite element model based on the surface interactions between the dielectric board and the electronic component in the printed circuit board design
25. The non-transitory machine readable medium of claim 24, wherein the one or more physical properties comprise one or more non-linear properties
6. The medium as in claim 5, wherein the first set and the second set of physical properties comprise one or more non-linear properties of a corresponding finite element
27. The non-transitory machine readable medium of claim 21, further comprising: simulating, based on the final finite element model, operation of the circuit board; and identifying, based on the simulation, thermal stresses associated with operation of the circuit board
7. The medium as in claim 1, further comprising: simulating, based on the final finite element model, operation of the printed circuit board design; and identifying, based on the simulation, thermal stresses associated with operation of the printed circuit board design
28. The non-transitory machine readable medium of claim 21, wherein the second finite element model of the electronic component comprises a one-dimensional or two-dimensional representation of the electronic component
10. The medium as in claim 1, wherein the second finite element model of the electronic component comprises a one-dimensional or two-dimensional representation of the electronic component
31. A machine implemented method, the method comprising: receiving a circuit board design for a circuit board comprising an electronic component and a dielectric board
11. A machine implemented method, the method comprising: receiving a printed circuit board design for an electronic component embedded in a dielectric board
generating a first finite element model of the dielectric board and a second finite element model of the electronic component separate from the first finite element model
36. The method of claim 31, wherein the first finite element model is generated based on a geometry of the dielectric board independent of the electronic component
generating a first finite element model to represent the dielectric board independent of the electronic component; generating a second finite element model for the electronic component separate from the first finite element model of the dielectric board
wherein the second finite element model includes a plurality of geometric domains; and generating a final finite element model for the circuit board design, by mapping each of the plurality of geometric domains of the second finite element model to one or more finite elements of the first finite element model using interactions between the electronic component and the dielectric board in the circuit board
32. The method of claim 31, wherein the interactions are surface interactions
identifying surface interactions between the dielectric board and the electronic component in the printed circuit board design; dividing the second finite element model into a plurality of geometric domains based on the surface interactions, each geometric domain corresponding to a finite element of the first finite element model of the dielectric board; and combining the first finite element model with the second finite element model to obtain a final finite element model for the printed circuit board design by mapping each geometric domain of the second finite element into a corresponding finite element of the first finite element model based on the surface interactions between the dielectric board and the electronic component in the printed circuit board design
35. The method of claim 34, wherein the one or more physical properties comprise one or more non-linear properties
16. The method as in claim 15, wherein the first set and the second set of physical properties comprise one or more non-linear properties of a corresponding finite element
37. The method of claim 31, further comprising: simulating, based on the final finite element model, operation of the circuit board; and identifying, based on the simulation, thermal stresses associated with operation of the circuit board
17. The method as in claim 11, further comprising: simulating, based on the final finite element model, operation of the printed circuit board design; and identifying, based on the simulation, thermal stresses associated with operation of the printed circuit board design
38. The method of claim 31, wherein the second finite element model of the electronic component comprises a one-dimensional or two-dimensional representation of the electronic component.
20. The method as in claim 11, wherein the second finite element model for the electronic component comprises a one-dimensional or two-dimensional representation of the electronic component.
As to the differences in wording, claims are patentably indistinct, since both claims express the same features.
Response to Arguments
Regarding the rejections under 112(a), the amendment corrected the deficiencies pointed out, and those objections are withdrawn. See paragraphs [0029] and [0041] of the original Specification.
Regarding the rejections under 112(b), no Applicant's arguments were presented for consideration. Claim rejections remain.
Regarding the rejection under 103, Applicant's arguments have been considered, but they are not persuasive. Applicant argues, (see page 6, 2nd paragraph to page 9, 1st paragraph) – underline emphasis added:
'… Rath discloses mapping physical properties of the PCB to a mesh, not mapping to a as claim. In particular, Applicant recites mapping one finite element model (the second model that is a finite element model of the electronic component) to another finite element model (the first model that is finite element model of a dielectric board) using interactions between the electronic component and the dielectric board in the circuit board. Because Rath discloses mapping physical properties to a mesh and not one finite element model to another finite element model as claimed, Applicant respectfully submits that Rath does not teach or suggest the claim element…'
Examiner's response: Applicant's argument is not persuasive, because contrary to Applicant's argument, Rath's mesh is a finite element model (see "A finite element mesh is generated based at least in part on the geometry data related to the PCB, the finite element mesh including… mesh components… conductors passing through the… mesh components are identified" in col. 2, lines 9-12 and "PCB simulation system 104 can model PCBs… PCB simulation system 104 can perform board level simulations based on the determined mesh model" in col. 4, lines 30-44).
As to Applicant’s arguments directed to amended claim language which has changed the scope of the claims, the amended claim language has been rejected as set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JUAN C OCHOA/Primary Examiner, Art Unit 2186