DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Reply Under 37 CFR 1.111
The submission of the reply filed on 7/17/2026 to the non-final Office action of 4/17/2026 is acknowledged. Claims 1-12, 14-16, and 21-22 are currently pending.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 22 is rejected under 35 U.S.C. 102(a) as being anticipated by US 2020/0203301 to Yu et al. (hereafter “Yu”, cited in IDS).
Regarding claim 22, Yu discloses: a circuit board arrangement (Fig. 7) comprising: a circuit board (110) having an upper side (110-TS) and an underside (108-TS); at least one electrical module (106A) having an upper side and an underside (Fig. 7), the upper side of the at least one electrical module (106A) being arranged on the underside (108-TS) of the circuit board (110); a heat sink (TM); means for providing a pressure (301, 302), with which the underside of the at least one electrical module (106A) is pressed against the heat sink (TM); and a heat- conducting material (104B) that is arranged between the underside of the at least one electrical module (106A) and the heat sink (TM), wherein the at least one electrical module (106A) is embedded in an encapsulating material (108', 106a-5) that terminates with the underside of the at least one electrical module (106A) without covering the underside of the at least one electrical module (106A), wherein the encapsulating material (108') is provided such that the encapsulating material presses the heat- conducting material (104B) against the heat sink (TM) in a region adjacent to the at least one electrical module (106A), and wherein the encapsulating material (106a-5) is disposed within a gap that extends between the upper side of the at least one electrical module (106A) and the underside (108-TS) of the circuit board (110), (Fig. 7).
Claim Rejections - 35 USC § 102/103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 21 is rejected under 35 U.S.C. 102(a) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over US 2020/0203301 to Yu et al. (hereafter “Yu”, cited in IDS).
Regarding claim 21, Yu discloses a circuit board arrangement (Figs. 7) comprising: a circuit board (110) having an upper side (110-TS) and an underside (108-TS); at least two electrical modules (106A) (Fig. 7; pars. [0013]-[0014], specifically, see “plurality of semiconductor dies” in par. [0014]), each electrical module (106A) of the at least two electrical modules having an upper side and an underside (Fig. 7), the upper side of the respective electrical module (106A) being arranged on the underside (108-TS) of the circuit board (110); a heat sink (TM); means for providing a pressure (301, 302), with which the underside of the at least one electrical module (106A) is pressed against the heat sink (TM); and a heat-conducting material (104B) that is arranged between the underside of the at least one electrical module (106A) and the heat sink (TM), wherein the at least two electrical modules (106A) are embedded in an encapsulating material (108’, 106a-5) that terminates with the underside of the at least two electrical modules (106A) without covering the underside of the at least two electrical modules (106A), and wherein the encapsulating material (108’, 106a-5) is provided and configured to press the heat- conducting material (104B) against the heat sink (TM) in a region adjacent to the at least two electrical modules (106A).
Alternative interpretation.
Regarding claim 1, Yu discloses a circuit board arrangement (Fig. 8) comprising: a circuit board (SB) having an upper side and an underside (Fig. 8); at least two electrical module (106A) (Fig. 8; pars. [0013]-[0014], specifically, see “plurality of semiconductor dies” in par. [0014]), each electrical module (106A) of the at least two electrical modules having an upper side and an underside (Fig. 8), the upper side of the respective electrical module (106A) being arranged on the underside of the circuit board (SB); a heat sink (TM); means for providing a pressure (301, 302), with which the underside of the at least one electrical module (106A) is pressed against the heat sink (TM); and a heat-conducting material (104B) that is arranged between the underside of the at least one electrical module (106A) and the heat sink (TM), wherein the at least two electrical modules (106A) are embedded in an encapsulating material (108’, 106a-6) that terminates with the underside of the at least two electrical modules (106A) without covering the underside of the at least two electrical modules (106A), and wherein the encapsulating material (108’, 106a-5) is provided such that the encapsulating material (108’) presses the heat-conducting material (104B) against the heat sink (TM) in a region adjacent to the at least two electrical modules (106A).
Alternatively, it would have been obvious to a person of the ordinary skill in related arts before the effective filing date of the claimed invention to have provided at least two electrical modules in Yu instead of the at least one, in order to adapt the circuit board arrangement of Yu for a particular application, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. See In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960) and St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
Allowable Subject Matter
Claims 1-12 and 14-16 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Applicants amended independent claim 1 to incorporate the subject matter of allowable dependent claim 13. Therefore, amended independent claim 1 is allowable over the cited prior art references. Claims 2-12 and 14-16 depend, either directly or indirectly, from allowable independent claim 1 and are allowable for at least this reason.
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive.
Regarding claim 21, Applicant contends that, allegedly, “Yu et al. do not teach or disclose at least two electrical modules that "are embedded in an encapsulating material that terminates with the undersides of the at least two electrical modules without covering the undersides of the at least two electrical modules," as recited by new independent claim 21. As shown in Figure 2, Yu et al. disclose an insulating material 108 formed on a buffer layer 104 and over a single semiconductor die 106A. Yu et al. do not teach or disclose at least two semiconductor dies 106A being embedded in the insulating material 108, as required by new independent claim 21. Therefore, new independent claim 21 is allowable over the cited prior art reference.”
As shown by the rejection above, the aforementioned Applicant’s conclusion is in error. Yu clearly teaches a plurality of the semiconductor modules (i.e., pars. [0013]-[0014], specifically, see “plurality of semiconductor dies” in par. [0014]).
Regarding claim 22, Applicant contends that, allegedly “Yu et al. do not teach or disclose a gap between the redistribution layer 110 and the semiconductor die 106A and, more specifically, do not teach or disclose that the insulating material 108 is disposed within such a gap. Accordingly, Yu et al. do not teach or disclose that "the encapsulating material is disposed within a gap that extends””.
As shown by the rejection above, the aforementioned Applicant’s conclusion is in error. Yu clearly teaches the encapsulating material (106a-5) is disposed within a gap that extends between the upper side of the at least one electrical module (106A) and the underside (108-TS) of the circuit board (110), (Fig. 7).
In view of the above the rejection is hereby maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Anatoly Vortman whose telephone number is (571)272-2047. The examiner can normally be reached Monday-Thursday, between 10 am and 8:30 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jayprakash N. Gandhi can be reached at 571-272-3740. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Anatoly Vortman/
Primary Examiner
Art Unit 2841
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