DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1, 3-9 and 11-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Petrov et al. (US20180128873A1, 2018-05-10), herein referred to as Petrov.
Regarding Claim 1, Petrov teaches a system level test system, comprising: a rack integrated computer (RIC) coupled to a network switch to provide a remote network connection to a plurality of single board computers (SBCs) ([0034]; Fig. 2; Examiner interprets the Central Computing system as the (RIC), the mictortesters as the (SBCs). Petrov further discloses all equipment may be included in a common enclosure. Examiner interprets this enclosure as a rack mounted enclosure); and the network switch coupled to the plurality of SBCs [0030; 0032], wherein the plurality of SBCs are operable to perform system level testing on a plurality of devices under test (DUTs)(Fig. 2-Fig. 3; [0020-0028]), wherein the plurality of SBCs are operable to be coupled to the plurality of DUTs )(Fig. 2-Fig. 3; [0020-0028], and wherein the system level testing comprises testing a plurality of components of the plurality of DUTs according to a test program executed by the plurality of SBCs over the remote network connection ([0020-0030]; Fig. 2-3).
Regarding Claim 3, Petrov teaches the system level test system of Claim 1, further comprising a lookup table stored in a memory of the RIC, wherein the lookup table comprises a designated IP address for accessing a first SBC of the plurality of SBCs, wherein further the first SBC is configured using the IP address, and wherein the first SBC is operable to be remotely accessed using the IP address to perform the system level testing [0030; 0034; 0035; 0049] (Examiner’s Note: All devices on a network are assigned IP addresses. Petrov discloses using a remote computing device to define/administer various testing procedures and routines either individually or at the same time, making this limitation inherent).
Regarding Claim 4, Petrov fails to specifically teach the system level test system of Claim 3, wherein the first SBC is accessed using a license file that enables a development mode that allows connection to the first SBC from any IP address. However, Petrov does teach controlling devices remotely via network. He further discloses the computer using operating systems and the ability to carry out operations in a variety of programming languages [0049; 0027-0030]. It is also inherent and obvious to one of ordinary skill in the art that in order to access remote systems, a license is required.
Regarding Claim 5, Petrov teaches The test system of Claim 1, wherein the network switch comprises an ethernet switch [0030].
Regarding Claim 6, Petrov teaches wherein the plurality of SBCs comprise 6 SBCs ([0027-0033]; fig. 2), and wherein the plurality of DUTs comprise 24 DUTs ([0027-0033]; fig. 2) and wherein each SBC of the plurality of SBCs is respectively coupled to 4 DUTs of the plurality of DUTs for performing the system level testing via the remote network connection ([0027-0033]; fig. 2).
Regarding Claim 7, Petrov teaches the test system of Claim 1, wherein the remote network connection provides communication between the plurality of SBCs and a remote computer system using at least one of: VNC; Remote Desktop Connection; and an integrated development environment (IDE) ([0049; 0037)].
Regarding claim 8, Petrov teaches wherein the plurality of SBCs are operable to install a custom IDE via the remote network connection ([0030; 0034; 0035; 0049]]; Examiner’s Note: All devices on a network are assigned IP addresses. The microtester can be controlled via network remotely. Microtesters have memory, processor and OS (custom) ([0027-0030]). Examiner interprets this as being operable to install a custom IDE, remotely. Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the teachings of Petrov by including: the limitations above in order to more efficiently test a high volume of a plurality of devices, remotely.
Regarding Claim 9, Petrov teaches wherein the plurality of SBCs are operable to install a custom software library via the remote network ([0030]; Examiner’s Note: All devices on a network are assigned IP addresses. The microtester can be controlled via network remotely. Microtesters have memory, processor and OS ([0027-0030]). Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to incorporate the teachings of Petrov by including: the limitations above in order to more efficiently test a high volume of a plurality of devices, remotely.
Regarding Claim 11, Petrov teaches a single board computer (SBC) for performing system level testing (microtester (10); [0028]), the SBC comprising: a processor[ [0030]; a memory [0029]; and a network interface [0030], wherein the processor is operable to perform system level testing on a plurality of DUTs operable to be coupled to the processor [0004; 0017], wherein the network interface is coupled to a network switch [0030], and wherein the network switch is coupled to a rack integrated computer (RIC) that coordinates remote access between the networking interface and a remote computer system ([0034]; Fig. 2; Examiner’s Note: Says all equipment may be included in a common enclosure. Examiner interprets this enclosure as a rack mounted enclosure).
Regarding Claim 12, Petrov teaches the SBC of Claim 11, wherein the plurality of DUTs are operable to be coupled to the processor using a USB interface [0026].
Regarding Claim 13, Petrov teaches the SBC of Claim 11, wherein the plurality of DUTs comprise 4 DUTs, and wherein the processor is operable to perform the system level testing on the 4 DUTs in parallel [0004; 0032].
Regarding Claim 14, Petrov teaches the SBC of Claim 11, wherein the processor is operable to assign a designated IP address to the network interface for connecting to the remote network, and wherein the designated IP address is stored in a lookup table in a memory of the RIC [0030; 0034; 0035; 0049] (Examiner’s Note: All devices on a network are assigned IP addresses. Petrov discloses using a remote computing device to define/administer various testing procedures and routines either individually or at the same time, making this limitation inherent).
Regarding Claim 15, Petrov teaches the SBC of Claim 11, wherein the network switch comprises an ethernet switch [0030; 0037].
Regarding Claim 16, Petrov teaches a method of system level testing (microtester (10); [0028]), comprising: associating a single board computer (SBC) with a designated IP address the SBC comprising: a processor[ [0030] (Examiner’s Note: Petrov discloses it is connected to a network and can be controlled remotely implying it has an IP address); storing the designated IP address in a lookup table in a memory of a rack integrated computer (RIC), wherein RIC and the SBC are coupled to a network switch, and wherein further the SBC is accessible by a remote computer system at the designated IP address via the RIC; and the remote computer system causing the SBC to perform system level testing on a plurality of devices under test (DUTs) operable to be coupled to the SBC [0030; 0034; 0035; 0049] (Examiner’s Note: All devices on a network are assigned IP addresses. Petrov discloses using a remote computing device to define/administer various testing procedures and routines either individually or at the same time, making this limitation inherent).
Regarding Claim 17, Petrov teaches the method of Claim 16, wherein the plurality of DUTs comprise 4 DUTs, and wherein the SBC is operable to perform the system level testing on the 4 DUTs in parallel [0004; 0032].
Regarding Claim 18, Petrov teaches the method of Claim 16, wherein the system level testing comprises: the SBC receiving test commands and data from the remote computer system (Abstract; [0030]); and the SBC returning test results to the remote computer system (Abstract; 0030]).
Regarding Claim 19, Petrov teaches the method of Claim 16, wherein the SBC executes an integrated development environment (IDE) controlled by the remote computer system [0049].
Regarding Claim 20, Petrov teaches the limitations of Claim 16. Petrov fails to specifically teach storing port forwarding rules at the RIC in the lookup table, wherein the SBC is further accessible via the IP address in combination with a port number according to the port forwarding rules defined in the lookup table. However, the examiner believes this limitation to be inherent due to the RIC having remote access. If the RIC has remote access to control the SBCs, IP address have to assigned to the network switch coupled devices (via ports of the switch via ethernet) and further the RIC can see each device via IP address and its assigned port (lookup table). It is therefore, inherent and obvious to a person of ordinary skill in the art to conclude this rationale.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Petrov as applied to claim 1, 3-9 and 11-20 above, and further in view of Ranganathan et al. (US20220284982A1, 2022-09-08) herein referred to as Ranganathan.
Regarding Claim 2, the combination teaches the system level test system of Claim 1, further comprising: a tester rack, wherein the RIC is disposed in the tester rack (Col. 3, Lines 29-52). The combination fails to specifically teach a power distribution board (PBD) disposed in a slot of the tester rack and coupled to the plurality of SBCs; and a test interface board (TIB) disposed in the slot of the tester rack and operable to be coupled to the plurality of DUTs. However, in a related field, Ranganathan teaches a power distribution board (PBD) disposed in a slot of the tester rack and coupled to the plurality of SBCs; and a test interface board (TIB) disposed in the slot of the tester rack and operable to be coupled to the plurality of DUTs (Fig. 2C; [0054-0056]). Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Chang and Lundquist to incorporate the teachings of Ranganathan by including: the limitations above in order to reduce the amount of time spent on testing devices to ensure that the device functions as designed and serve as a diagnostic tool to determine the presence of faulty components within a given device before it reaches the consumer.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Petrov, further in view of Lundquist et al. (US9179573, 2015-11-03) herein referred to as Lundquist.
Regarding Claim 10, Petrov teaches the test system of Claim 1. Petrov further teaches a plurality of SBCs operable to be coupled to another plurality of DUTs [0020-0030; Fig. 2]. Petrov fails to teach a plurality of network switches coupled to a plurality of tester racks, wherein each tester rack comprises another plurality of SBCs, and wherein the plurality of network switches are coupled to the RIC to coordinate remote access to another plurality of SBCs for performing the system level testing on another plurality of DUTs. However, in a related field, Lindquist teaches a plurality of network switches coupled to a plurality of tester racks (Lindquist: Col. 6, Lines 26-61). Lindquist further teaches wherein each tester rack comprises another plurality of SBCs (Lindquist: Col. 6, Lines 26-61), and wherein the plurality of network switches are coupled to the RIC to coordinate remote access to another plurality of SBCs for performing the system level testing on another plurality of DUTs (Col. 6, Lines 26-61; Col. 3, lines 29-52) (Examiner’s Note: Lindquist teaches each SBC is independently operating and capable of operating a s a host computer or some other computer independent of the others. The examiner interprets this as RIC. Further, Lindquist teaches 2U and 3U configurations). Therefore, it would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to have modified Petrov to incorporate the teachings of Lindquist by including: the limitations above in order to more efficiently test a high volume of a plurality of devices, remotely.
Conclusion
The prior art made record and not relied upon is considered pertinent to applicant’s disclosure.
Malisic et al. (MULTIPLE-NAME-SPACE TEST SYSTEMS AND METHODS, 2023-08-17) teaches embodiments that facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a multiple-name-space testing system comprises a load board, testing electronics, and a namespace testing tracker. The load board is configured to couple with a plurality of devices under test (DUTs). The testing electronics are configured to test the plurality of DUTs, wherein the testing electronics are coupled to the load board. The controller is configured to direct testing of multiple-name-spaces across the plurality of DUTs at least in part in parallel. The controller can be coupled to the testing electronics. The namespace testing tracker is configured to track testing of the plurality of DUTs, including the testing of the multiple-name-spaces across the plurality of DUTs at least in part in parallel. In one embodiment, the DUTs are NVMe SSD devices;
Sinsheimer et al. (Automated Test Equipment With Fiber Optic Connection To Remote Server, 2023-08-11) teaches an exemplary test system includes a test head and a device interface board (DIB) configured to connect to the test head. The DIB is for holding the device under test (DUT). The DIB contains electrical conductors for transmitting electrical signals between the DUT and the test head. The server is programmed to act as a test device. The server is external to and remote from the test head and is configured to communicate signals with the test head via a fiber optic cable. Signals include serial signals;
Campbell et al. (SYSTEMS, APPARATUS AND METHODS FOR AUTOMATICALLY TESTING SECURITY ALARM DEVICES, 2023-08-03) teaches systems, apparatus and methods for automatically testing security alarm devices are disclosed according to various embodiments. In one example, a disclosed system comprises: a plurality of test chambers coupled on a frame, wherein each of the test chambers is configured to house a corresponding one of a plurality of security alarm devices to be tested; and a test computer coupled to the frame, wherein the computer has a processor and a non-transitory computer readable storage medium for automatically testing the plurality of security alarm devices at the same time using a test software, wherein each of the plurality of security alarm devices is connected to the test computer;
Reid et al. (Calibration System, 2022-11-03) teaches A verification probe system is configured to verify an automated test platform and includes: an integrated circuit test probe assembly; and a moveable platform configured to position the integrated circuit test probe assembly proximate one of more conductive pins included within a test socket assembly of the automated test platform;
Bautista (FLEXIBLE TEST SYSTEMS AND METHODS, 2022-02-24) teaches embodiments that facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a test system comprises pre-qualifying test components, functional test components, a controller, a transceiver, and a switch. The pre-qualifying test components are configured to perform pre-qualifying testing on a device under test. The functional test components are configured to perform functional testing on the device under test. The controller is configured to direct selection between the pre-qualifying testing and functional testing. The transceiver is configured to transmit and receive signals to/from the device under test. The switch is configured to selectively couple the transceiver to the pre-qualifying test components and functional test components;
Wolff et al. (SCALABLE PLATFORM FOR SYSTEM LEVEL TESTING, 2019-09-12) teaches a scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.
Chan et al. (Test Architecture Having Multiple FPGA Based Hardware Accelerator Blocks For Testing Multiple DUTs Independently, 2018-12-25) teaches automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components;
Champoux et al. (TEST ARCHITECTURE WITH AN FPGA BASED TEST BOARD TO SIMULATE A DUT OR END-POINT, 2018-07-12) teaches An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.
Chen et al. (AUTOMATED TEST PLATFORM, 2016-10-06) teaches an automated test platform for testing a first device under test includes N voltage sources for providing N different voltages. A cross matrix switching system is coupled to the N voltage sources, the cross matrix switch being configured to provide the N different voltages to M discrete test points within the first device under test, wherein M is larger than N. An N voltage measuring system is coupled to the first device under test, the N voltage measuring system being configured to measure the voltage potential present on the M discrete test points.
Chang et al. (System For Synchronously Controlling The Testing Of Pluralities Of Devices And The Method Of The Same, 2006-08-17) teaches a system for synchronously controlling the testing of pluralities of devices, comprising a server, a switch coupled to the server, and a testing instrument coupled to the server. Pluralities of computers are coupled to the server respectively, wherein the pluralities of devices are respectively connected to the pluralities of computers and the switch under testing. The parameters of the pluralities of devices include a first type test item that is testable by the pluralities of computers, and a second type test item that is testable by the testing instrument. The switch includes a RF switch. The server is connected to the testing instrument by a GPIB cable (or other instrument control interface and the server is connected to the pluralities of computers via local area network (LAN) such as Ethernet.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL J SINGLETARY whose telephone number is (571)272-4593. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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/MICHAEL J SINGLETARY/Examiner, Art Unit 2857