Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “15” has been used to designate both a layer in fig. 4A and “the supporting layer” for figures 4B to 4H. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao (US Patent 5,912,485).
Regarding claim 1, Chao teaches a method of fabricating a semiconductor structure, comprising: forming a plurality of capacitor holes (filled by 26, figs. 3A to 3D) extending through a stack of layers (14, 20, 22) in a stacking direction, the stack of layers comprising a first region (left half of the device) and a second region (right half), and the capacitor holes being located in the first region and the second region; forming a first electrode layer (26) over inside walls of the capacitor holes; forming a dielectric layer (44) on a side of the stack of layers in the first region and the second region; removing (figs. 3A to 3D) at least part of the dielectric layer in the second region; and forming a second electrode layer (56a and 56b) in the first region and the second region, a portion of the second electrode layer in the first region being separated (figs. 3A to 3D) from a portion of the second electrode layer in the second region, and the first electrode layer being connected with the second electrode layer in the second region (figs. 3A to 3D).
Regarding claim 2, Chao teaches the method of claim 1, wherein the first electrode layer in both the first region and the second region is separated into individual portions (figs. 3A to 3D).
Regarding claim 3, Chao teaches the method of claim 1, wherein the removing at least part of the dielectric layer in the second region comprises: removing the dielectric layer in the second region to expose the first electrode layer in the second region (figs. 3A to 3D).
Regarding claim 4, Chao teaches the method of claim 3, wherein the forming the second electrode layer in both the first region and the second region comprises: forming the second electrode layer on the side of the stack of layers, the second electrode layer located in the first region and the second region; covering the dielectric layer on a side away from the stack of layers and the exposed first electrode layer; filling the capacitor holes (figs. 3A to 3D); and forming a first trench (54 in the middle, fig. 3C) extending through the second electrode layer on the stack of layers in the stacking direction and extending in a first direction (into the paper since 54 must be three-dimensional), the first trench separating the portion of the second electrode layer in the first region from the portion of the second electrode layer in the second region in a second direction (horizontal direction), the first direction, the second direction, and the stacking direction (vertical direction) being perpendicular to each other.
Claim(s) 13-16 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao (US Patent 6,080,632).
Regarding claim 13, Chao teaches a semiconductor structure, comprising: a stack structure (14,20,22, figs. 3A to 3D) comprising a first region (left half of device) and a second region (right half); a first electrode layer (50a and 50b) located in the first region and the second region, the first electrode layer extending through the stack structure in the stacking direction and being separated into individual portions (50a and 50b); a dielectric layer (52a, fig. 3D) located at least in the first region; and a second electrode layer (42) located in the first region and the second region, a portion of the second electrode layer in the first region being separated (fig. 3B) from a portion of the second electrode layer in the second region, the first electrode layer being connected (at side surfaces of 50a and 50b) with the second electrode layer in the second region, and the first electrode layer and the second electrode layer having the dielectric layer disposed therebetween in the first region.
Regarding claim 14, Chao teaches the semiconductor structure of claim 13, wherein the first electrode layer in both the first region and the second region is separated into individual portions (figs. 3A to 3D).
Regarding claim 15, Chao teaches the semiconductor structure of claim 13, wherein the second electrode layer in the second region is separated into individual portions (figs. 3A to 3D).
Regarding claim 16, Chao teaches the semiconductor structure of claim 13, wherein: the dielectric layer is located over the stack structure in the first region and covers the first electrode layer in the first region on a side away from the stack structure, and the second electrode layer is located over the stack structure in the first region and the second region and covers the dielectric layer in the first region on a side away (at side surfaces of 50a and 50b) from the first electrode layer and the first electrode layer in the second region on the side away from the stack structure (figs. 3A to 3D).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chao (US Patent 6,080,632) and Kimura (US Patent 5,247,196).
Regarding claim 20, Chao teaches a memory, comprising: a semiconductor structure, comprising: a stack structure comprising a first region and a second region; a first electrode layer located in the first region and the second region, the first electrode layer extending through the stack structure in the stacking direction and being separated into individual portions; a dielectric layer located at least in the first region; and a second electrode layer located in the first region and the second region, a portion of the second electrode layer in the first region being separated from a portion of the second electrode layer in the second region, the first electrode layer being connected with the second electrode layer in the second region, and the first electrode layer and the second electrode layer having the dielectric layer disposed therebetween in the first region (figs. 3A to 3D, see rejection of claim13).
Chao does not teach a peripheral circuit structure electrically connected with the semiconductor structure.
In the same field of endeavor, Kimura teaches a peripheral circuit structure (the elements around the memory, fig. 5) electrically connected with the semiconductor structure (the memory device), for the benefit of facilitating memory input and output (column 1, lines 26-48).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to electrically connect a peripheral circuit structure with the semiconductor structure for the benefit of facilitating memory input and output.
Allowable Subject Matter
Claims 5-12 and 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“forming at least one second trench extending, in the stacking direction, through the portion of the second electrode layer on the stack of layers in the second region, the at least one second trench separating the second electrode layer in the second region into multiple disconnected portions” (claim 5);
“forming a plurality of spacer holes extending through the supporting layer into the stack of layers in the stacking direction; removing the sacrificial layers to form cavities, the spacer holes being located in the first region and the second region; and removing the portions of the supporting layer outside the capacitor holes, wherein the dielectric layer is located on the stack of layers in the first region and the second region and covers the inside walls of the cavities and the spacer holes” (claim 6);
“forming gate structures extending in the second direction; connecting at least the active parts in the first region, the gate structures extending through the active parts in the stacking direction and resulting in a plurality of channel structures” (claim 11);
“the dielectric layer…extends through portions of the stack structure in the first region and the second region in the stacking direction” (claim 17).
Conclusion
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899