Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(4) because reference character “15” has been used to designate both a layer in fig. 4A and “the supporting layer” for figures 4B to 4H. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-3,13-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chao (US Patent 5,912,485).
Regarding claim 1, Chao teaches a method of fabricating a semiconductor structure, comprising: forming a plurality of capacitor holes (54 fig. 3C) extending through a stack of layers (46 and 50) in a stacking direction, the stack of layers comprising a first region (left half of the device) and a second region (right half), and the capacitor holes being located in the first region and the second region; forming a first electrode layer (56a and 56b) over inside walls of the capacitor holes; forming a dielectric layer (28a and 28b, fig. 3B) on a sidewall of the stack of layers extending in the stacking direction in the first region and the second region; removing (fig. 3D) at least part of the dielectric layer in the second region; and forming a second electrode layer (46) in the first region and the second region, a portion (46a) of the second electrode layer in the first region being separated (figs. 3B to 3C) from a portion (46b) of the second electrode layer in the second region, and the first electrode layer (56b) being connected (fig. 3E) with the second electrode layer (46b) in the second region.
Regarding claim 2, Chao teaches the method of claim 1, wherein the first electrode layer in both the first region and the second region is separated into individual portions (figs. 3A to 3D).
Regarding claim 3, Chao teaches the method of claim 1, wherein the removing at least part of the dielectric layer in the second region comprises: removing the dielectric layer in the second region to expose the first electrode layer in the second region (figs. 3A to 3D).
Regarding claim 13, Chao teaches a semiconductor structure, comprising: a stack structure (26 and 46, fig. 3C) comprising a first region (left half of device) and a second region (right half); a first electrode layer (56a and 56b) located in the first region and the second region, the first electrode layer extending through the stack structure in the stacking direction and being separated into individual portions; a dielectric layer (58a, fig. 3E) located at least in the first region; and a second electrode layer (50 or 60) located in the first region and the second region, a portion (50a) of the second electrode layer in the first region being separated (3E) from a portion (50b) of the second electrode layer in the second region, the first electrode layer being connected (fig. 3E) with the second electrode layer in the second region, and the first electrode layer and the second electrode layer having the dielectric layer disposed therebetween (fig. 3E) in the first region.
Regarding claim 14, Chao teaches the semiconductor structure of claim 13, wherein the first electrode layer in both the first region and the second region is separated into individual portions (fig. 3E).
Regarding claim 15, Chao teaches the semiconductor structure of claim 13, wherein the second electrode layer in the second region is separated into individual portions (fig. 3E).
Regarding claim 16, Chao teaches the semiconductor structure of claim 13, wherein: the dielectric layer is located over the stack structure in the first region and covers the first electrode layer in the first region on a side away (see fig. 3E attached) from the stack structure, and the second electrode layer (60) is located over the stack structure in the first region and the second region and covers the dielectric layer in the first region on a side away (see fig. 3E attached) from the first electrode layer and the first electrode layer in the second region on the side away from the stack structure.
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Regarding claim 17, Chao teaches the semiconductor structure of claim 13, wherein: the dielectric layer (58, fig. 3E) is located over the stack structure in the first region and extends through portions of the stack structure in the first region and the second region in the stacking direction, and the second electrode layer (60) is located over the stack structure in the first region and the second region and covers the dielectric layer on a side away from the first electrode layer.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over by Chao (US Patent 5,912,485) and Kimura (US Patent 5,247,196).
Regarding claim 20, Chao teaches a memory, comprising: a semiconductor structure, comprising: a stack structure (26 and 46) comprising a first region and a second region (left and right regions in fig. 3E); a first electrode layer (56a and 56b) located in the first region and the second region, the first electrode layer extending through the stack structure in the stacking direction and being separated into individual portions; a dielectric layer (58a) located at least in the first region; and a second electrode layer (50a and 50b) located in the first region and the second region, a portion of the second electrode layer in the first region being separated from a portion of the second electrode layer in the second region, the first electrode layer being connected with the second electrode layer in the second region, and the first electrode layer and the second electrode layer having the dielectric layer disposed therebetween in the first region.
Chao does not teach a peripheral circuit structure electrically connected with the semiconductor structure.
In the same field of endeavor, Kimura teaches a peripheral circuit structure (the elements around the memory, fig. 5) electrically connected with the semiconductor structure (the memory device), for the benefit of facilitating memory input and output (column 1, lines 26-48).
Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to electrically connect a peripheral circuit structure with the semiconductor structure for the benefit of facilitating memory input and output.
Allowable Subject Matter
Claims 4-12 and 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not teach
“wherein the forming the second electrode layer in both the first region and the second region comprises…covering …the exposed first electrode layer; filling the capacitor holes;” (claim 4) and “a portion of the second electrode layer in the first region being separated from a portion of the second electrode layer in the second region” (claim 1);
“forming a plurality of spacer holes extending through the supporting layer into the stack of layers in the stacking direction; removing the sacrificial layers to form cavities, the spacer holes being located in the first region and the second region; and removing the portions of the supporting layer outside the capacitor holes, wherein the dielectric layer is located on the stack of layers in the first region and the second region and covers the inside walls of the cavities and the spacer holes” (claim 6);
“forming gate structures extending in the second direction; connecting at least the active parts in the first region, the gate structures extending through the active parts in the stacking direction and resulting in a plurality of channel structures” (claim 11);
“the stack structure comprises multiple stacked spacer layers, and the dielectric layer and the second electrode layer are also located between every two spacer layers adjacent in the stacking direction in the second region and the first region” (claim 18).
Response to Arguments
Applicant's arguments filed 6/9/26 have been fully considered but they are not persuasive because previously cited Chao teaches claims 1-3. See rejection above. Applicant’s arguments with respect to claim(s) 13-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST.
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/FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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