Detailed Action
Acknowledgements
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in reply to the Amendment filed on July 21, 2026.
Claim 5 is cancelled.
Claims 1-4 and 6-20 are pending.
Claims 1-4 and 6-20 are examined.
This Office Action is given Paper No. 20260910 for references purposes only.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 and 6-20 are rejected under 35 U.S.C. 103(a) as being unpatentable over McGinley et al. (US 7,967,193) in view of Monaghan et al. (EP 2,913,806).
Claims 1, 11
McGinley discloses:
a single motherboard (motherboard, see C16 L24-34) comprising:
an application processing environment (TSS, see C38 L56 – C39 L9);
a secure processing environment (trusted platform module, TPM, see C4 L14-40), wherein the secure processing environment comprises: a secure processor to execute security applications that authenticate (authenticate, see C6 L25-46, C6 L66 – C7 L16) peripheral device connections requested of the secure processing environment and that encrypt (establish encrypted communication, see C6 L35-46) peripheral communications over the peripheral device connections, wherein the secure processing environment includes peripheral ports for the peripheral device connections including a media handling peripheral device (portable storage device, see C31 L15-31);
a secure wired on-motherboard connection between the application processing environment (TSS, see C38 L56-67) and the secure processing environment (TPM, see C38 L56-67);
wherein the application processing environment (TSS, see C38 L56 – C39 L9) and the secure processing environment (TPM, see C38 L56 – C39 L9) are integrated together on the single motherboard (motherboard, see C38 L56 – C39 L9) as a secure transaction terminal gateway device.
McGinley does not disclose:
Peripheral ports;
Wherein the secure… boards.
Monaghan teaches:
peripheral ports (peripherals or ports, see [0052]);
wherein the secure processing environment (thin-client web-based application, see [0050]) handles all peripheral device communications (access the peripherals, see [0050]) for the peripheral devices via on-chip resources of the secure processing environment, thereby removing a necessity for the peripheral devices to include such resources on their own independent printed circuit boards.
McGinley discloses a single motherboard, an application processing environment, a secure processing environment, a secure wired on-motherboard connection, and the environments integrated on a single motherboard. McGinley does not disclose peripheral ports and the secure processing environment handling peripheral communications, but Monaghan does. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to combine the automated banking machine that operates responsive to data bearing records of McGinley with the peripheral ports and the secure processing environment handling peripheral communications of Monaghan because 1) a need exists for preventing unauthorized access to an automated teller machine (McGinley C2 L49-67); and 2) a need exists for frequent asset updates and customization of assets by client banks for their ATMs that is efficient (see Monaghan [0004-0005]). Having peripheral ports and the secure processing environment handling peripheral communications helps to prevent unauthorized access to the ATM, and allows for updates to the peripheral devices.
Claim 2
Furthermore, McGinley discloses:
The secure processing environment (trusted platform module, TPM, see C4 L14-40) includes a secure processor (computer chips, computer processor, see C16 L24-34) and the peripheral ports (port, see C31 L15-30) for the peripheral device connections to the secure processing environment.
Claim 3
Furthermore, Monaghan teaches:
The application processing environment includes an application processor (processor, see [0078-0079]) and a secure network port (peripherals or ports, see [0052]) to a secure external network (authorized server, see [0043]) that is external to the single motherboard.
Claim 4
Furthermore, Monaghan teaches:
The application processing environment includes an application secure port (peripherals or ports, see [0052]) for the secure wired on-motherboard connection and the secure processing environment includes a secure port (peripherals or ports, see [0052]) for the secure wired on-motherboard connection.
Claim 6
Furthermore, Monaghan teaches:
the application processing environment includes an application processor (processor, see [0078-0079]) that executes a media-based transaction application to indirectly communicate with peripheral devices (peripherals, e.g. keypad, card reader, see [0047]) of the peripheral device connections via the secure wired on-motherboard connection.
Claim 7
Furthermore, McGinley discloses:
the secure processing environment (trusted platform module, TPM, see C4 L14-40) includes a wireless transceiver (wireless communication transmitter/receiver, see C31 L15-30) and a secure processor to execute security applications that authenticate wireless device connections requested of the secure processing environment and that encrypt wireless communications over the wireless device connections.
Claims 8, 12
Furthermore, Monaghan teaches:
the application processing environment includes an application processor (processor, see [0078-0079]) that executes a media-based transaction application to indirectly communicate with wireless devices of the wireless device connections (wireless, see [0078]) via the secure wired on-motherboard connection.
Claims 9, 15
Furthermore, McGinley discloses:
The single motherboard (motherboard, see C16 L24-34) is an automated teller machine (ATM) motherboard for an ATM device (ATM, see C16 L24-34).
Claim 10
Furthermore, McGinley discloses:
the application processing environment is a first independent device (first computer chip, see C16 L24-34), and the secure processing environment is a second independent device (second computer chip, e.g. TPM SLD 9630 chip, see C16 L24-34), wherein the secure wired on-motherboard connection integrates the first independent device with the second independent device on a single printed circuit board (PCB) (motherboard, see C16 L24-34) as a secure transaction terminal gateway device.
Claim 13
Furthermore, McGinley discloses:
receiving the peripheral communications over peripheral ports (port, see C31 L15-30) on the security node.
Claim 14
Furthermore, McGinley discloses:
the secure processing environment (trusted platform module, TPM, see C4 L14-40) includes a secure processor (computer chips, computer processor, see C16 L24-34) to execute security applications that authenticate peripheral connections requested of the secure processing environment and that encrypt peripheral communications over the connections.
Claim 16
Furthermore, McGinley discloses:
controlling the application-based operations further includes interfacing, by the application node, with an external system (e.g. portable storage device, see C31 L15-30) that is external to the application node and the security node over an external network port on the application node.
Claim 17
Furthermore, McGinley discloses:
controlling the peripheral-based operations further includes authenticating (authenticate, see C6 L25-46, C6 L66 – C7 L16), by the security node, each peripheral device connected to the security node via a corresponding peripheral port of the security node and encrypting (establish encrypted communication, see C6 L35-46), by the security node, communications with a corresponding peripheral device during each authenticated connection.
Claim 18
Furthermore, McGinley discloses:
interfacing further includes encrypting (establish encrypted communication, see C6 L35-46), by the application node and by the security node, communications over the secure wired motherboard connection.
Claim 19
McGinley discloses:
providing a first device architecture comprising a first processor (first computer chip, see C16 L24-34), first applications (TSS, see C38 L56 – C39 L9) executed by the first processor, and a first secure port;
providing a second device architecture comprising a second processor (second computer chip, see C16 L24-34), second applications (trusted platform module, TPM, see C4 L14-40) executed by the second processor, second applications including security applications executed by the second processor to authenticate (authenticate, see C6 L25-46, C6 L66 – C7 L16) peripheral device connections requested of the second device architecture and to encrypt (establish encrypted communication, see C6 L35-46) peripheral communications over peripheral device connections through peripheral ports for peripheral device connections to the second device architecture including media-based connections to a media handling peripheral device (portable storage device, see C31 L15-31), and a second secure port;
integrating the first device architecture and the second device architecture on a single printed circuit board (PCB) (motherboard, see C16 L24-34) via a secure wired PCB connection between the first secure port and the second secure port;
wherein the first device architecture and the second device architecture are integrated together on the single PCB (motherboard, see C38 L56 – C39 L9) as a secure transaction terminal gateway device.
McGinley does not disclose:
Peripheral ports;
Executing… boards.
Monaghan teaches:
peripheral ports (peripherals or ports, see [0052]);
executing, by the second processor, control of all peripheral device communications (access the peripherals, see [0050]) for peripheral devices connected to the second device architecture via on-chip resources of the second device architecture, thereby removing a necessity for the peripheral devices to include such resources on their own independent printed circuit boards.
McGinley discloses a first device architecture, a second device architecture, integrating the first and second device architectures on a single circuit board, and integrating on the single PCB. McGinley does not disclose peripheral ports and the secure processing environment handling peripheral communications, but Monaghan does. It would have been obvious to one of ordinary skill in the art at the effective filing date of the invention to combine the automated banking machine that operates responsive to data bearing records of McGinley with the peripheral ports and the secure processing environment handling peripheral communications of Monaghan because 1) a need exists for preventing unauthorized access to an automated teller machine (McGinley C2 L49-67); and 2) a need exists for frequent asset updates and customization of assets by client banks for their ATMs that is efficient (see Monaghan [0004-0005]). Having peripheral ports and the secure processing environment handling peripheral communications helps to prevent unauthorized access to the ATM, and allows for updates to the peripheral devices.
Claim 20
Furthermore, McGinley discloses:
providing the single PCB as an automated teller machine (ATM) motherboard (motherboard, see C16 L24-34), wherein the peripheral device connections made to peripheral devices via the peripheral ports are authenticated (authenticate, see C6 L25-46, C6 L66 – C7 L16) by the second processor and direct communications during the peripheral device connections are encrypted (establish encrypted communication, see C6 L35-46) by the second processor.
Response to Arguments
Applicant argues that the prior art does not teach a secure processing environment that handles all peripheral device communications for the peripheral devices via on-chip resources of the secure processing environment, thereby removing the necessity for the peripheral devices to includes such resources on their own independent printed circuit boards. Rather, Applicant argues that McGinley teaches the peripheral devices independently include their own processes and firmware.
Please see revised rejection with new art Monaghan.
Claim Interpretation
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure (see attached form PTO-892).
McGraw, IV et al. (US 2021/0357906) discloses a touchless transaction on a transaction terminal.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry of a general nature or relating to the status of this application or concerning this communication or earlier communications from Examiner should be directed to Chrystina Zelaskiewicz whose telephone number is 571-270-3940. Examiner can normally be reached on Monday-Friday, 9:30am-5:00pm. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, Neha Patel can be reached at 571-270-1492.
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/CHRYSTINA E ZELASKIEWICZ/
Primary Examiner, Art Unit 3699
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