DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed on 09/26/2023 & 02/20/2025 has been considered and placed in the application file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Hancioglu et al. (U.S. 11,437,961).
Regarding claim 1, Hancioglu (hereinafter, Ref~961) discloses (e.g., please see Figs. 5-6 and related text for details) receiver circuitry (500 of Fig. 5 can obviously employed in said receiver circuitry, since it is being used in FRONT END as advertised), comprising:
an amplifier (see amplifier from 502 of Fig. 5);
a first chopper circuit (e.g., CH52 of Fig. 5) comprising a first output coupled to a first input of the amplifier;
a second chopper circuit (e.g., CH53 of Fig. 5) comprising a second input coupled to a second output of the amplifier and comprising a third output;
a sampling circuit (504 of Fig. 5 can be read as the claimed circuit OR at least it is functionally equivalent to it, since it has the same structure compared to the claimed one, namely a switching capacitor network) comprising a third input coupled to the third output of the second chopper circuit and a fourth input coupled to a clock signal generator (512 of Fig. 5); and
a divider circuit (not shown, but it would have been obvious to employ said divider or the like within the chopping control 512 of Fig. 5 in order to provide various/programable Fchop used by system as shown in the Figure depending on custom specifications) coupled to the clock signal generator, the first chopper circuit and the second chopper circuit, meeting claim 1.
Regarding claim 2, Ref~961 The receiver circuitry of claim 1, wherein the clock signal generator is configured to output a sampling clock frequency Fchop as shown in Fig. 8, MODULATOR CLOCK, meeting claim 2.
Regarding claim 3, Ref~961 supports the claimed “wherein the divider circuit is configured to provide a chopper frequency equal to one-half of the sampling clock frequency”, since these are normal design parameters/features as described in col. 7, line 35 through col. 8, line 5, meeting claim 3.
Regarding claim 4, Ref~961 discloses the receiver circuitry of claim 1, comprising:
an additional amplifier (see 526 of Fig. 5);
a third chopper circuit (CH56 of Fig. 5) comprising a fourth output coupled to a fifth input of the amplifier; and
a fourth chopper circuit (CH57 of Fig. 5) comprising a sixth input coupled to a fifth output of the amplifier as seen, meeting claim 4.
Allowable Subject Matter
Claims 5-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Allowable Subject Matter
Claims 10-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Claims 10-15 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “a clock divider circuit configured to provide a chopper frequency to the first chopper circuit and the second chopper circuit based on the sampling clock frequency, the chopper frequency configured to merge a first interference due to the first chopper circuit and a second interference due to the second chopper circuit” structurally and functionally interconnected with other limitations in the manner as cited in the claims.
Claims 16-20 are allowed over the prior art of record. The prior art of record, considered individually or in combination, fails to fairly teach or suggest the claimed circuit comprising, among other limitations and unobvious limitations of “a second sampling circuit coupled to the second set of chopper circuits and a second clock generator, and a to the second clock generator and the second set of chopper circuits” structurally and functionally interconnected with other limitations in the manner as cited in the claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HIEU P NGUYEN whose telephone number is 571-272-8577. The examiner can normally be reached on Monday-Friday 8:30AM-6:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/HIEU P NGUYEN/Primary Examiner, Art Unit 2843