DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-9 are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) were submitted on 09/27/2023 and 06/07/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5 and 7 are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Salling (US 20040212936 A1).
Regarding claim 1, Salling teaches a chip ([0036], chip real estate area), comprising:
an input/output (I/O) pin (e.g. PAD, fig.1B);
an electrostatic discharge (ESD) protection circuit (e.g. circuit of fig.1B) comprising a P-type device (i.e. pMOS transistor 113, fig.1B) and a first diode (e.g. diode connected directly to PAD, fig.1B), wherein the P-type device is coupled between the I/O pin and a ground voltage (e.g. 113 is connected between PAD and ground, fig.1B), and an anode of the first diode is directly connected to the I/O pin (e.g. anode of diode connected directly to pad, fig.1B);
wherein the ESD protection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin ([0054], Between source and drain is poly gate 222) (it is necessarily true that PAD is connected to p-type drain, a polygate and p-type anode of first diode, fig.1B).
Regarding claim 2, Salling teaches the chip of claim 1, wherein the I/O pin is used to receive a negative voltage from a device external to the chip (abstract, During an ESD event), and the negative voltage is lower than the ground voltage (abstract, to turn-on the MOS transistor) (it is necessarily true that PAD voltage should be a voltage lower than ground voltage connected to source of 113, for 113 to conduct).
Regarding claim 3, Salling teaches the chip of claim 1, wherein the P-type device is a P-type transistor (i.e. pMOS transistor 113, fig.1B).
Regarding claim 4, Salling teaches the chip of claim 1, wherein the P-type device is a P-type transistor (i.e. pMOS transistor 113, fig.1B), a drain electrode of the P-type transistor is directly connected to the I/O pin (e.g. drain of 113 is directly connected to PAD, fig.1B), a source electrode of the P-type transistor is coupled to the ground voltage (e.g. source of 113 is connected to ground, fig.1B); and the chip further comprises:
an ESD detection circuit (e.g. circuit comprising 113d, fig.1B), configured to detect a voltage level of the I/O pin ([0044], During an ESD event) to determine if generating a control signal to enable the P-type transistor ([0044], This voltage drop turns on strongly the lateral npn of transistor 103) ([0050], electrical connections and the reaction to an ESD pulse are analogous to the description in FIG. 1A).
Regarding claim 5, Salling teaches the chip of claim 4, wherein the ESD detection circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin (e.g. connections at 113d are NOT directly connected to PAD, fig.1B).
Regarding claim 7, Salling teaches the chip of claim 1, wherein a cathode of the first diode is coupled to a supply voltage or the ground voltage (e.g. cathode of first diode is coupled to ground via other diodes and resistor, fig.1B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Salling (US 20040212936 A1), and further in view of Ker (US 20020130390 A1).
Regarding claim 6, Salling teaches the chip of claim 1, further comprising:
an internal circuit ([0021], present ESD protection circuitry, therefore, does not add significant processing time or expense to the IC).
Salling does not teach directly connected to the I/O pin, wherein the internal circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.
Ker teaches in a similar field of endeavor of ESD protection circuit, an internal circuit directly connected to the I/O pin (e.g. pad 30 connected to internal circuit 32, fig.22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the directly connected I/O pin in Salling, as taught by Ker, as it provides the advantage of protecting the internal circuit, while using lesser components and smaller chip real estate.
Salling and Ker do not teach, wherein the internal circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin.
It would have been an obvious matter of design choice to have the internal circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin, since the applicant has not disclosed that the internal circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin solves any problem or is for a particular reason. It appears that the claimed invention would perform equally well with the internal circuit does not comprise any device whose N-type doping/diffusion is directly connected to the I/O pin, as it provides the advantage of protecting the gate of a n-type transistor.
Regarding claim 8, Salling teaches the chip of claim 1, wherein a cathode of the first diode is coupled to a supply voltage (e.g. cathode of first diode is connected to a supply voltage at the node connecting resistor and diode string, fig.1B).
Salling does not teach, the ESD protection circuit further comprises: a second diode, wherein an anode of the second diode is coupled to the ground voltage, and a cathode of the second diode is coupled to the P-type device.
Ker teaches in a similar field of endeavor of ESD protection circuit, a second diode (e.g. diode Dn3, fig.22), wherein an anode of the second diode is coupled to the ground voltage (e.g. anode of Dn3 is connected to ground, fig.22), and a cathode of the second diode is coupled to the P-type device (e.g. cathode of Dn3 is connected to PMOS MDp1, fig.22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ESD protection circuit further comprises: a second diode, wherein an anode of the second diode is coupled to the ground voltage, and a cathode of the second diode is coupled to the P-type device in Salling, as taught by Ker, as it provides the advantage of reducing input equivalent capacitance and provides robustness for high speed IC ESD protection.
Regarding claim 9, Salling teaches the chip of claim 1, wherein a cathode of the first diode is coupled to the ground voltage (e.g. cathode of first diode is connected to ground via other diodes and resistor, fig.1B).
Salling does not teach, the ESD protection circuit further comprises: a second diode, wherein an anode of the second diode is coupled to the ground voltage, and a cathode of the second diode is coupled to the P-type device.
Ker teaches in a similar field of endeavor of ESD protection circuit, a second diode (e.g. diode Dn3, fig.22), wherein an anode of the second diode is coupled to the ground voltage (e.g. anode of Dn3 is connected to ground, fig.22), and a cathode of the second diode is coupled to the P-type device (e.g. cathode of Dn3 is connected to PMOS MDp1, fig.22).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the ESD protection circuit further comprises: a second diode, wherein an anode of the second diode is coupled to the ground voltage, and a cathode of the second diode is coupled to the P-type device in Salling, as taught by Ker, as it provides the advantage of reducing input equivalent capacitance and provides robustness for high speed IC ESD protection.
Conclusion
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/SREEYA SREEVATSA/ Primary Examiner, Art Unit 2838 12/09/2025